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dc5d621c MK |
1 | /** @file\r |
2 | MSR Definitions for Intel processors based on the Sandy Bridge microarchitecture.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
dc5d621c MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
dc5d621c MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __SANDY_BRIDGE_MSR_H__\r | |
19 | #define __SANDY_BRIDGE_MSR_H__\r | |
20 | \r | |
e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
dc5d621c | 22 | \r |
f4c982bf JF |
23 | /**\r |
24 | Is Intel processors based on the Sandy Bridge microarchitecture?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_SANDY_BRIDGE_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x06 && \\r | |
34 | ( \\r | |
35 | DisplayModel == 0x2A || \\r | |
36 | DisplayModel == 0x2D \\r | |
37 | ) \\r | |
38 | )\r | |
39 | \r | |
dc5d621c MK |
40 | /**\r |
41 | Thread. SMI Counter (R/O).\r | |
42 | \r | |
43 | @param ECX MSR_SANDY_BRIDGE_SMI_COUNT (0x00000034)\r | |
44 | @param EAX Lower 32-bits of MSR value.\r | |
45 | Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r | |
46 | @param EDX Upper 32-bits of MSR value.\r | |
47 | Described by the type MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER.\r | |
48 | \r | |
49 | <b>Example usage</b>\r | |
50 | @code\r | |
51 | MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER Msr;\r | |
52 | \r | |
53 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_SMI_COUNT);\r | |
54 | @endcode\r | |
367f5c9c | 55 | @note MSR_SANDY_BRIDGE_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
dc5d621c | 56 | **/\r |
2f88bd3a | 57 | #define MSR_SANDY_BRIDGE_SMI_COUNT 0x00000034\r |
dc5d621c MK |
58 | \r |
59 | /**\r | |
60 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_SMI_COUNT\r | |
61 | **/\r | |
62 | typedef union {\r | |
63 | ///\r | |
64 | /// Individual bit fields\r | |
65 | ///\r | |
66 | struct {\r | |
67 | ///\r | |
68 | /// [Bits 31:0] SMI Count (R/O) Count SMIs.\r | |
69 | ///\r | |
2f88bd3a MK |
70 | UINT32 SMICount : 32;\r |
71 | UINT32 Reserved : 32;\r | |
dc5d621c MK |
72 | } Bits;\r |
73 | ///\r | |
74 | /// All bit fields as a 32-bit value\r | |
75 | ///\r | |
2f88bd3a | 76 | UINT32 Uint32;\r |
dc5d621c MK |
77 | ///\r |
78 | /// All bit fields as a 64-bit value\r | |
79 | ///\r | |
2f88bd3a | 80 | UINT64 Uint64;\r |
dc5d621c MK |
81 | } MSR_SANDY_BRIDGE_SMI_COUNT_REGISTER;\r |
82 | \r | |
dc5d621c | 83 | /**\r |
ba1a2d11 ED |
84 | Package. Platform Information Contains power management and other model\r |
85 | specific features enumeration. See http://biosbits.org.\r | |
dc5d621c MK |
86 | \r |
87 | @param ECX MSR_SANDY_BRIDGE_PLATFORM_INFO (0x000000CE)\r | |
88 | @param EAX Lower 32-bits of MSR value.\r | |
89 | Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
90 | @param EDX Upper 32-bits of MSR value.\r | |
91 | Described by the type MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER.\r | |
92 | \r | |
93 | <b>Example usage</b>\r | |
94 | @code\r | |
95 | MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER Msr;\r | |
96 | \r | |
97 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO);\r | |
98 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PLATFORM_INFO, Msr.Uint64);\r | |
99 | @endcode\r | |
367f5c9c | 100 | @note MSR_SANDY_BRIDGE_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
dc5d621c | 101 | **/\r |
2f88bd3a | 102 | #define MSR_SANDY_BRIDGE_PLATFORM_INFO 0x000000CE\r |
dc5d621c MK |
103 | \r |
104 | /**\r | |
105 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PLATFORM_INFO\r | |
106 | **/\r | |
107 | typedef union {\r | |
108 | ///\r | |
109 | /// Individual bit fields\r | |
110 | ///\r | |
111 | struct {\r | |
2f88bd3a | 112 | UINT32 Reserved1 : 8;\r |
dc5d621c MK |
113 | ///\r |
114 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
115 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
116 | /// MHz.\r | |
117 | ///\r | |
2f88bd3a MK |
118 | UINT32 MaximumNonTurboRatio : 8;\r |
119 | UINT32 Reserved2 : 12;\r | |
dc5d621c MK |
120 | ///\r |
121 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
122 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
123 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
124 | /// Turbo mode is disabled.\r | |
125 | ///\r | |
2f88bd3a | 126 | UINT32 RatioLimit : 1;\r |
dc5d621c MK |
127 | ///\r |
128 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
129 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
130 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
131 | /// programmable.\r | |
132 | ///\r | |
2f88bd3a MK |
133 | UINT32 TDPLimit : 1;\r |
134 | UINT32 Reserved3 : 2;\r | |
135 | UINT32 Reserved4 : 8;\r | |
dc5d621c MK |
136 | ///\r |
137 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
138 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
139 | /// units of 100MHz.\r | |
140 | ///\r | |
2f88bd3a MK |
141 | UINT32 MaximumEfficiencyRatio : 8;\r |
142 | UINT32 Reserved5 : 16;\r | |
dc5d621c MK |
143 | } Bits;\r |
144 | ///\r | |
145 | /// All bit fields as a 64-bit value\r | |
146 | ///\r | |
2f88bd3a | 147 | UINT64 Uint64;\r |
dc5d621c MK |
148 | } MSR_SANDY_BRIDGE_PLATFORM_INFO_REGISTER;\r |
149 | \r | |
dc5d621c MK |
150 | /**\r |
151 | Core. C-State Configuration Control (R/W) Note: C-state values are\r | |
152 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
153 | parameters or ACPI CStates. See http://biosbits.org.\r | |
154 | \r | |
155 | @param ECX MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
156 | @param EAX Lower 32-bits of MSR value.\r | |
157 | Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
158 | @param EDX Upper 32-bits of MSR value.\r | |
159 | Described by the type MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
160 | \r | |
161 | <b>Example usage</b>\r | |
162 | @code\r | |
163 | MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
164 | \r | |
165 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL);\r | |
166 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
167 | @endcode\r | |
367f5c9c | 168 | @note MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
dc5d621c MK |
169 | **/\r |
170 | #define MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL 0x000000E2\r | |
171 | \r | |
172 | /**\r | |
173 | MSR information returned for MSR index\r | |
174 | #MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL\r | |
175 | **/\r | |
176 | typedef union {\r | |
177 | ///\r | |
178 | /// Individual bit fields\r | |
179 | ///\r | |
180 | struct {\r | |
181 | ///\r | |
182 | /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r | |
183 | /// processor-specific C-state code name (consuming the least power). for\r | |
184 | /// the package. The default is set as factory-configured package C-state\r | |
185 | /// limit. The following C-state code name encodings are supported: 000b:\r | |
186 | /// C0/C1 (no package C-sate support) 001b: C2 010b: C6 no retention 011b:\r | |
187 | /// C6 retention 100b: C7 101b: C7s 111: No package C-state limit. Note:\r | |
188 | /// This field cannot be used to limit package C-state to C3.\r | |
189 | ///\r | |
2f88bd3a MK |
190 | UINT32 Limit : 3;\r |
191 | UINT32 Reserved1 : 7;\r | |
dc5d621c MK |
192 | ///\r |
193 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W) When set, will map\r | |
194 | /// IO_read instructions sent to IO register specified by\r | |
195 | /// MSR_PMG_IO_CAPTURE_BASE to MWAIT instructions.\r | |
196 | ///\r | |
2f88bd3a MK |
197 | UINT32 IO_MWAIT : 1;\r |
198 | UINT32 Reserved2 : 4;\r | |
dc5d621c MK |
199 | ///\r |
200 | /// [Bit 15] CFG Lock (R/WO) When set, lock bits 15:0 of this register\r | |
201 | /// until next reset.\r | |
202 | ///\r | |
2f88bd3a MK |
203 | UINT32 CFGLock : 1;\r |
204 | UINT32 Reserved3 : 9;\r | |
dc5d621c MK |
205 | ///\r |
206 | /// [Bit 25] C3 state auto demotion enable (R/W) When set, the processor\r | |
207 | /// will conditionally demote C6/C7 requests to C3 based on uncore\r | |
208 | /// auto-demote information.\r | |
209 | ///\r | |
2f88bd3a | 210 | UINT32 C3AutoDemotion : 1;\r |
dc5d621c MK |
211 | ///\r |
212 | /// [Bit 26] C1 state auto demotion enable (R/W) When set, the processor\r | |
213 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
214 | /// auto-demote information.\r | |
215 | ///\r | |
2f88bd3a | 216 | UINT32 C1AutoDemotion : 1;\r |
dc5d621c MK |
217 | ///\r |
218 | /// [Bit 27] Enable C3 undemotion (R/W) When set, enables undemotion from\r | |
219 | /// demoted C3.\r | |
220 | ///\r | |
2f88bd3a | 221 | UINT32 C3Undemotion : 1;\r |
dc5d621c MK |
222 | ///\r |
223 | /// [Bit 28] Enable C1 undemotion (R/W) When set, enables undemotion from\r | |
224 | /// demoted C1.\r | |
225 | ///\r | |
2f88bd3a MK |
226 | UINT32 C1Undemotion : 1;\r |
227 | UINT32 Reserved4 : 3;\r | |
228 | UINT32 Reserved5 : 32;\r | |
dc5d621c MK |
229 | } Bits;\r |
230 | ///\r | |
231 | /// All bit fields as a 32-bit value\r | |
232 | ///\r | |
2f88bd3a | 233 | UINT32 Uint32;\r |
dc5d621c MK |
234 | ///\r |
235 | /// All bit fields as a 64-bit value\r | |
236 | ///\r | |
2f88bd3a | 237 | UINT64 Uint64;\r |
dc5d621c MK |
238 | } MSR_SANDY_BRIDGE_PKG_CST_CONFIG_CONTROL_REGISTER;\r |
239 | \r | |
dc5d621c MK |
240 | /**\r |
241 | Core. Power Management IO Redirection in C-state (R/W) See\r | |
242 | http://biosbits.org.\r | |
243 | \r | |
244 | @param ECX MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
245 | @param EAX Lower 32-bits of MSR value.\r | |
246 | Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
247 | @param EDX Upper 32-bits of MSR value.\r | |
248 | Described by the type MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
249 | \r | |
250 | <b>Example usage</b>\r | |
251 | @code\r | |
252 | MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
253 | \r | |
254 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE);\r | |
255 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
256 | @endcode\r | |
367f5c9c | 257 | @note MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
dc5d621c | 258 | **/\r |
2f88bd3a | 259 | #define MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE 0x000000E4\r |
dc5d621c MK |
260 | \r |
261 | /**\r | |
262 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE\r | |
263 | **/\r | |
264 | typedef union {\r | |
265 | ///\r | |
266 | /// Individual bit fields\r | |
267 | ///\r | |
268 | struct {\r | |
269 | ///\r | |
270 | /// [Bits 15:0] LVL_2 Base Address (R/W) Specifies the base address\r | |
271 | /// visible to software for IO redirection. If IO MWAIT Redirection is\r | |
272 | /// enabled, reads to this address will be consumed by the power\r | |
273 | /// management logic and decoded to MWAIT instructions. When IO port\r | |
274 | /// address redirection is enabled, this is the IO port address reported\r | |
275 | /// to the OS/software.\r | |
276 | ///\r | |
2f88bd3a | 277 | UINT32 Lvl2Base : 16;\r |
dc5d621c MK |
278 | ///\r |
279 | /// [Bits 18:16] C-state Range (R/W) Specifies the encoding value of the\r | |
280 | /// maximum C-State code name to be included when IO read to MWAIT\r | |
281 | /// redirection is enabled by MSR_PKG_CST_CONFIG_CONTROL[bit10]: 000b - C3\r | |
282 | /// is the max C-State to include 001b - C6 is the max C-State to include\r | |
283 | /// 010b - C7 is the max C-State to include.\r | |
284 | ///\r | |
2f88bd3a MK |
285 | UINT32 CStateRange : 3;\r |
286 | UINT32 Reserved1 : 13;\r | |
287 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
288 | } Bits;\r |
289 | ///\r | |
290 | /// All bit fields as a 32-bit value\r | |
291 | ///\r | |
2f88bd3a | 292 | UINT32 Uint32;\r |
dc5d621c MK |
293 | ///\r |
294 | /// All bit fields as a 64-bit value\r | |
295 | ///\r | |
2f88bd3a | 296 | UINT64 Uint64;\r |
dc5d621c MK |
297 | } MSR_SANDY_BRIDGE_PMG_IO_CAPTURE_BASE_REGISTER;\r |
298 | \r | |
dc5d621c MK |
299 | /**\r |
300 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
301 | handler to handle unsuccessful read of this MSR.\r | |
302 | \r | |
303 | @param ECX MSR_SANDY_BRIDGE_FEATURE_CONFIG (0x0000013C)\r | |
304 | @param EAX Lower 32-bits of MSR value.\r | |
305 | Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r | |
306 | @param EDX Upper 32-bits of MSR value.\r | |
307 | Described by the type MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER.\r | |
308 | \r | |
309 | <b>Example usage</b>\r | |
310 | @code\r | |
311 | MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER Msr;\r | |
312 | \r | |
313 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG);\r | |
314 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_FEATURE_CONFIG, Msr.Uint64);\r | |
315 | @endcode\r | |
367f5c9c | 316 | @note MSR_SANDY_BRIDGE_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r |
dc5d621c | 317 | **/\r |
2f88bd3a | 318 | #define MSR_SANDY_BRIDGE_FEATURE_CONFIG 0x0000013C\r |
dc5d621c MK |
319 | \r |
320 | /**\r | |
321 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_FEATURE_CONFIG\r | |
322 | **/\r | |
323 | typedef union {\r | |
324 | ///\r | |
325 | /// Individual bit fields\r | |
326 | ///\r | |
327 | struct {\r | |
328 | ///\r | |
329 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
330 | /// MSR, the configuration of AES instruction set availability is as\r | |
331 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
332 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
333 | /// is not available if read is unsuccessful. If the configuration is not\r | |
334 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
335 | /// unintentionally writes 11b.\r | |
336 | ///\r | |
2f88bd3a MK |
337 | UINT32 AESConfiguration : 2;\r |
338 | UINT32 Reserved1 : 30;\r | |
339 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
340 | } Bits;\r |
341 | ///\r | |
342 | /// All bit fields as a 32-bit value\r | |
343 | ///\r | |
2f88bd3a | 344 | UINT32 Uint32;\r |
dc5d621c MK |
345 | ///\r |
346 | /// All bit fields as a 64-bit value\r | |
347 | ///\r | |
2f88bd3a | 348 | UINT64 Uint64;\r |
dc5d621c MK |
349 | } MSR_SANDY_BRIDGE_FEATURE_CONFIG_REGISTER;\r |
350 | \r | |
dc5d621c | 351 | /**\r |
ba1a2d11 | 352 | Core. See Table 2-2. If CPUID.0AH:EAX[15:8] = 8.\r |
dc5d621c MK |
353 | \r |
354 | @param ECX MSR_SANDY_BRIDGE_IA32_PERFEVTSELn\r | |
355 | @param EAX Lower 32-bits of MSR value.\r | |
356 | @param EDX Upper 32-bits of MSR value.\r | |
357 | \r | |
358 | <b>Example usage</b>\r | |
359 | @code\r | |
360 | UINT64 Msr;\r | |
361 | \r | |
362 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4);\r | |
363 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4, Msr);\r | |
364 | @endcode\r | |
367f5c9c JF |
365 | @note MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 is defined as IA32_PERFEVTSEL4 in SDM.\r |
366 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 is defined as IA32_PERFEVTSEL5 in SDM.\r | |
367 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 is defined as IA32_PERFEVTSEL6 in SDM.\r | |
368 | MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 is defined as IA32_PERFEVTSEL7 in SDM.\r | |
dc5d621c MK |
369 | @{\r |
370 | **/\r | |
2f88bd3a MK |
371 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL4 0x0000018A\r |
372 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL5 0x0000018B\r | |
373 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL6 0x0000018C\r | |
374 | #define MSR_SANDY_BRIDGE_IA32_PERFEVTSEL7 0x0000018D\r | |
dc5d621c MK |
375 | /// @}\r |
376 | \r | |
dc5d621c MK |
377 | /**\r |
378 | Package.\r | |
379 | \r | |
380 | @param ECX MSR_SANDY_BRIDGE_PERF_STATUS (0x00000198)\r | |
381 | @param EAX Lower 32-bits of MSR value.\r | |
382 | Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r | |
383 | @param EDX Upper 32-bits of MSR value.\r | |
384 | Described by the type MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER.\r | |
385 | \r | |
386 | <b>Example usage</b>\r | |
387 | @code\r | |
388 | MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER Msr;\r | |
389 | \r | |
390 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS);\r | |
391 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PERF_STATUS, Msr.Uint64);\r | |
392 | @endcode\r | |
367f5c9c | 393 | @note MSR_SANDY_BRIDGE_PERF_STATUS is defined as MSR_PERF_STATUS in SDM.\r |
dc5d621c | 394 | **/\r |
2f88bd3a | 395 | #define MSR_SANDY_BRIDGE_PERF_STATUS 0x00000198\r |
dc5d621c MK |
396 | \r |
397 | /**\r | |
398 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PERF_STATUS\r | |
399 | **/\r | |
400 | typedef union {\r | |
401 | ///\r | |
402 | /// Individual bit fields\r | |
403 | ///\r | |
404 | struct {\r | |
2f88bd3a | 405 | UINT32 Reserved1 : 32;\r |
dc5d621c MK |
406 | ///\r |
407 | /// [Bits 47:32] Core Voltage (R/O) P-state core voltage can be computed\r | |
408 | /// by MSR_PERF_STATUS[37:32] * (float) 1/(2^13).\r | |
409 | ///\r | |
2f88bd3a MK |
410 | UINT32 CoreVoltage : 16;\r |
411 | UINT32 Reserved2 : 16;\r | |
dc5d621c MK |
412 | } Bits;\r |
413 | ///\r | |
414 | /// All bit fields as a 64-bit value\r | |
415 | ///\r | |
2f88bd3a | 416 | UINT64 Uint64;\r |
dc5d621c MK |
417 | } MSR_SANDY_BRIDGE_PERF_STATUS_REGISTER;\r |
418 | \r | |
dc5d621c | 419 | /**\r |
ba1a2d11 | 420 | Thread. Clock Modulation (R/W) See Table 2-2. IA32_CLOCK_MODULATION MSR was\r |
dc5d621c MK |
421 | originally named IA32_THERM_CONTROL MSR.\r |
422 | \r | |
423 | @param ECX MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION (0x0000019A)\r | |
424 | @param EAX Lower 32-bits of MSR value.\r | |
425 | Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r | |
426 | @param EDX Upper 32-bits of MSR value.\r | |
427 | Described by the type MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER.\r | |
428 | \r | |
429 | <b>Example usage</b>\r | |
430 | @code\r | |
431 | MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER Msr;\r | |
432 | \r | |
433 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION);\r | |
434 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION, Msr.Uint64);\r | |
435 | @endcode\r | |
367f5c9c | 436 | @note MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION is defined as IA32_CLOCK_MODULATION in SDM.\r |
dc5d621c | 437 | **/\r |
2f88bd3a | 438 | #define MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION 0x0000019A\r |
dc5d621c MK |
439 | \r |
440 | /**\r | |
441 | MSR information returned for MSR index\r | |
442 | #MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION\r | |
443 | **/\r | |
444 | typedef union {\r | |
445 | ///\r | |
446 | /// Individual bit fields\r | |
447 | ///\r | |
448 | struct {\r | |
449 | ///\r | |
450 | /// [Bits 3:0] On demand Clock Modulation Duty Cycle (R/W) In 6.25%\r | |
451 | /// increment.\r | |
452 | ///\r | |
2f88bd3a | 453 | UINT32 OnDemandClockModulationDutyCycle : 4;\r |
dc5d621c MK |
454 | ///\r |
455 | /// [Bit 4] On demand Clock Modulation Enable (R/W).\r | |
456 | ///\r | |
2f88bd3a MK |
457 | UINT32 OnDemandClockModulationEnable : 1;\r |
458 | UINT32 Reserved1 : 27;\r | |
459 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
460 | } Bits;\r |
461 | ///\r | |
462 | /// All bit fields as a 32-bit value\r | |
463 | ///\r | |
2f88bd3a | 464 | UINT32 Uint32;\r |
dc5d621c MK |
465 | ///\r |
466 | /// All bit fields as a 64-bit value\r | |
467 | ///\r | |
2f88bd3a | 468 | UINT64 Uint64;\r |
dc5d621c MK |
469 | } MSR_SANDY_BRIDGE_IA32_CLOCK_MODULATION_REGISTER;\r |
470 | \r | |
dc5d621c MK |
471 | /**\r |
472 | Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
473 | functions to be enabled and disabled.\r | |
474 | \r | |
475 | @param ECX MSR_SANDY_BRIDGE_IA32_MISC_ENABLE (0x000001A0)\r | |
476 | @param EAX Lower 32-bits of MSR value.\r | |
477 | Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r | |
478 | @param EDX Upper 32-bits of MSR value.\r | |
479 | Described by the type MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER.\r | |
480 | \r | |
481 | <b>Example usage</b>\r | |
482 | @code\r | |
483 | MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER Msr;\r | |
484 | \r | |
485 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE);\r | |
486 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MISC_ENABLE, Msr.Uint64);\r | |
487 | @endcode\r | |
367f5c9c | 488 | @note MSR_SANDY_BRIDGE_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
dc5d621c | 489 | **/\r |
2f88bd3a | 490 | #define MSR_SANDY_BRIDGE_IA32_MISC_ENABLE 0x000001A0\r |
dc5d621c MK |
491 | \r |
492 | /**\r | |
493 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MISC_ENABLE\r | |
494 | **/\r | |
495 | typedef union {\r | |
496 | ///\r | |
497 | /// Individual bit fields\r | |
498 | ///\r | |
499 | struct {\r | |
500 | ///\r | |
ba1a2d11 | 501 | /// [Bit 0] Thread. Fast-Strings Enable See Table 2-2.\r |
dc5d621c | 502 | ///\r |
2f88bd3a MK |
503 | UINT32 FastStrings : 1;\r |
504 | UINT32 Reserved1 : 6;\r | |
dc5d621c | 505 | ///\r |
ba1a2d11 | 506 | /// [Bit 7] Thread. Performance Monitoring Available (R) See Table 2-2.\r |
dc5d621c | 507 | ///\r |
2f88bd3a MK |
508 | UINT32 PerformanceMonitoring : 1;\r |
509 | UINT32 Reserved2 : 3;\r | |
dc5d621c | 510 | ///\r |
ba1a2d11 | 511 | /// [Bit 11] Thread. Branch Trace Storage Unavailable (RO) See Table 2-2.\r |
dc5d621c | 512 | ///\r |
2f88bd3a | 513 | UINT32 BTS : 1;\r |
dc5d621c | 514 | ///\r |
0f16be6d | 515 | /// [Bit 12] Thread. Processor Event Based Sampling Unavailable (RO) See\r |
ba1a2d11 | 516 | /// Table 2-2.\r |
dc5d621c | 517 | ///\r |
2f88bd3a MK |
518 | UINT32 PEBS : 1;\r |
519 | UINT32 Reserved3 : 3;\r | |
dc5d621c MK |
520 | ///\r |
521 | /// [Bit 16] Package. Enhanced Intel SpeedStep Technology Enable (R/W) See\r | |
ba1a2d11 | 522 | /// Table 2-2.\r |
dc5d621c | 523 | ///\r |
2f88bd3a MK |
524 | UINT32 EIST : 1;\r |
525 | UINT32 Reserved4 : 1;\r | |
dc5d621c | 526 | ///\r |
ba1a2d11 | 527 | /// [Bit 18] Thread. ENABLE MONITOR FSM (R/W) See Table 2-2.\r |
dc5d621c | 528 | ///\r |
2f88bd3a MK |
529 | UINT32 MONITOR : 1;\r |
530 | UINT32 Reserved5 : 3;\r | |
dc5d621c | 531 | ///\r |
ba1a2d11 | 532 | /// [Bit 22] Thread. Limit CPUID Maxval (R/W) See Table 2-2.\r |
dc5d621c | 533 | ///\r |
2f88bd3a | 534 | UINT32 LimitCpuidMaxval : 1;\r |
dc5d621c | 535 | ///\r |
ba1a2d11 | 536 | /// [Bit 23] Thread. xTPR Message Disable (R/W) See Table 2-2.\r |
dc5d621c | 537 | ///\r |
2f88bd3a MK |
538 | UINT32 xTPR_Message_Disable : 1;\r |
539 | UINT32 Reserved6 : 8;\r | |
540 | UINT32 Reserved7 : 2;\r | |
dc5d621c | 541 | ///\r |
ba1a2d11 | 542 | /// [Bit 34] Thread. XD Bit Disable (R/W) See Table 2-2.\r |
dc5d621c | 543 | ///\r |
2f88bd3a MK |
544 | UINT32 XD : 1;\r |
545 | UINT32 Reserved8 : 3;\r | |
dc5d621c MK |
546 | ///\r |
547 | /// [Bit 38] Package. Turbo Mode Disable (R/W) When set to 1 on processors\r | |
548 | /// that support Intel Turbo Boost Technology, the turbo mode feature is\r | |
549 | /// disabled and the IDA_Enable feature flag will be clear (CPUID.06H:\r | |
550 | /// EAX[1]=0). When set to a 0 on processors that support IDA, CPUID.06H:\r | |
551 | /// EAX[1] reports the processor's support of turbo mode is enabled. Note:\r | |
552 | /// the power-on default value is used by BIOS to detect hardware support\r | |
553 | /// of turbo mode. If power-on default value is 1, turbo mode is available\r | |
554 | /// in the processor. If power-on default value is 0, turbo mode is not\r | |
555 | /// available.\r | |
556 | ///\r | |
2f88bd3a MK |
557 | UINT32 TurboModeDisable : 1;\r |
558 | UINT32 Reserved9 : 25;\r | |
dc5d621c MK |
559 | } Bits;\r |
560 | ///\r | |
561 | /// All bit fields as a 64-bit value\r | |
562 | ///\r | |
2f88bd3a | 563 | UINT64 Uint64;\r |
dc5d621c MK |
564 | } MSR_SANDY_BRIDGE_IA32_MISC_ENABLE_REGISTER;\r |
565 | \r | |
dc5d621c MK |
566 | /**\r |
567 | Unique.\r | |
568 | \r | |
569 | @param ECX MSR_SANDY_BRIDGE_TEMPERATURE_TARGET (0x000001A2)\r | |
570 | @param EAX Lower 32-bits of MSR value.\r | |
571 | Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
572 | @param EDX Upper 32-bits of MSR value.\r | |
573 | Described by the type MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER.\r | |
574 | \r | |
575 | <b>Example usage</b>\r | |
576 | @code\r | |
577 | MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER Msr;\r | |
578 | \r | |
579 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET);\r | |
580 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_TEMPERATURE_TARGET, Msr.Uint64);\r | |
581 | @endcode\r | |
367f5c9c | 582 | @note MSR_SANDY_BRIDGE_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
dc5d621c | 583 | **/\r |
2f88bd3a | 584 | #define MSR_SANDY_BRIDGE_TEMPERATURE_TARGET 0x000001A2\r |
dc5d621c MK |
585 | \r |
586 | /**\r | |
587 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_TEMPERATURE_TARGET\r | |
588 | **/\r | |
589 | typedef union {\r | |
590 | ///\r | |
591 | /// Individual bit fields\r | |
592 | ///\r | |
593 | struct {\r | |
2f88bd3a | 594 | UINT32 Reserved1 : 16;\r |
dc5d621c MK |
595 | ///\r |
596 | /// [Bits 23:16] Temperature Target (R) The minimum temperature at which\r | |
597 | /// PROCHOT# will be asserted. The value is degree C.\r | |
598 | ///\r | |
2f88bd3a MK |
599 | UINT32 TemperatureTarget : 8;\r |
600 | UINT32 Reserved2 : 8;\r | |
601 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
602 | } Bits;\r |
603 | ///\r | |
604 | /// All bit fields as a 32-bit value\r | |
605 | ///\r | |
2f88bd3a | 606 | UINT32 Uint32;\r |
dc5d621c MK |
607 | ///\r |
608 | /// All bit fields as a 64-bit value\r | |
609 | ///\r | |
2f88bd3a | 610 | UINT64 Uint64;\r |
dc5d621c MK |
611 | } MSR_SANDY_BRIDGE_TEMPERATURE_TARGET_REGISTER;\r |
612 | \r | |
dc5d621c MK |
613 | /**\r |
614 | Miscellaneous Feature Control (R/W).\r | |
615 | \r | |
616 | @param ECX MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL (0x000001A4)\r | |
617 | @param EAX Lower 32-bits of MSR value.\r | |
618 | Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r | |
619 | @param EDX Upper 32-bits of MSR value.\r | |
620 | Described by the type MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER.\r | |
621 | \r | |
622 | <b>Example usage</b>\r | |
623 | @code\r | |
624 | MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
625 | \r | |
626 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL);\r | |
627 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
628 | @endcode\r | |
367f5c9c | 629 | @note MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r |
dc5d621c | 630 | **/\r |
2f88bd3a | 631 | #define MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL 0x000001A4\r |
dc5d621c MK |
632 | \r |
633 | /**\r | |
634 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL\r | |
635 | **/\r | |
636 | typedef union {\r | |
637 | ///\r | |
638 | /// Individual bit fields\r | |
639 | ///\r | |
640 | struct {\r | |
641 | ///\r | |
642 | /// [Bit 0] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
643 | /// L2 hardware prefetcher, which fetches additional lines of code or data\r | |
644 | /// into the L2 cache.\r | |
645 | ///\r | |
2f88bd3a | 646 | UINT32 L2HardwarePrefetcherDisable : 1;\r |
dc5d621c MK |
647 | ///\r |
648 | /// [Bit 1] Core. L2 Adjacent Cache Line Prefetcher Disable (R/W) If 1,\r | |
649 | /// disables the adjacent cache line prefetcher, which fetches the cache\r | |
650 | /// line that comprises a cache line pair (128 bytes).\r | |
651 | ///\r | |
2f88bd3a | 652 | UINT32 L2AdjacentCacheLinePrefetcherDisable : 1;\r |
dc5d621c MK |
653 | ///\r |
654 | /// [Bit 2] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables\r | |
655 | /// the L1 data cache prefetcher, which fetches the next cache line into\r | |
656 | /// L1 data cache.\r | |
657 | ///\r | |
2f88bd3a | 658 | UINT32 DCUHardwarePrefetcherDisable : 1;\r |
dc5d621c MK |
659 | ///\r |
660 | /// [Bit 3] Core. DCU IP Prefetcher Disable (R/W) If 1, disables the L1\r | |
661 | /// data cache IP prefetcher, which uses sequential load history (based on\r | |
662 | /// instruction Pointer of previous loads) to determine whether to\r | |
663 | /// prefetch additional lines.\r | |
664 | ///\r | |
2f88bd3a MK |
665 | UINT32 DCUIPPrefetcherDisable : 1;\r |
666 | UINT32 Reserved1 : 28;\r | |
667 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
668 | } Bits;\r |
669 | ///\r | |
670 | /// All bit fields as a 32-bit value\r | |
671 | ///\r | |
2f88bd3a | 672 | UINT32 Uint32;\r |
dc5d621c MK |
673 | ///\r |
674 | /// All bit fields as a 64-bit value\r | |
675 | ///\r | |
2f88bd3a | 676 | UINT64 Uint64;\r |
dc5d621c MK |
677 | } MSR_SANDY_BRIDGE_MISC_FEATURE_CONTROL_REGISTER;\r |
678 | \r | |
dc5d621c MK |
679 | /**\r |
680 | Thread. Offcore Response Event Select Register (R/W).\r | |
681 | \r | |
682 | @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_0 (0x000001A6)\r | |
683 | @param EAX Lower 32-bits of MSR value.\r | |
684 | @param EDX Upper 32-bits of MSR value.\r | |
685 | \r | |
686 | <b>Example usage</b>\r | |
687 | @code\r | |
688 | UINT64 Msr;\r | |
689 | \r | |
690 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0);\r | |
691 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_0, Msr);\r | |
692 | @endcode\r | |
367f5c9c | 693 | @note MSR_SANDY_BRIDGE_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
dc5d621c | 694 | **/\r |
2f88bd3a | 695 | #define MSR_SANDY_BRIDGE_OFFCORE_RSP_0 0x000001A6\r |
dc5d621c MK |
696 | \r |
697 | /**\r | |
698 | Thread. Offcore Response Event Select Register (R/W).\r | |
699 | \r | |
700 | @param ECX MSR_SANDY_BRIDGE_OFFCORE_RSP_1 (0x000001A7)\r | |
701 | @param EAX Lower 32-bits of MSR value.\r | |
702 | @param EDX Upper 32-bits of MSR value.\r | |
703 | \r | |
704 | <b>Example usage</b>\r | |
705 | @code\r | |
706 | UINT64 Msr;\r | |
707 | \r | |
708 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1);\r | |
709 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_OFFCORE_RSP_1, Msr);\r | |
710 | @endcode\r | |
367f5c9c | 711 | @note MSR_SANDY_BRIDGE_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r |
dc5d621c | 712 | **/\r |
2f88bd3a | 713 | #define MSR_SANDY_BRIDGE_OFFCORE_RSP_1 0x000001A7\r |
dc5d621c MK |
714 | \r |
715 | /**\r | |
716 | See http://biosbits.org.\r | |
717 | \r | |
718 | @param ECX MSR_SANDY_BRIDGE_MISC_PWR_MGMT (0x000001AA)\r | |
719 | @param EAX Lower 32-bits of MSR value.\r | |
720 | @param EDX Upper 32-bits of MSR value.\r | |
721 | \r | |
722 | <b>Example usage</b>\r | |
723 | @code\r | |
724 | UINT64 Msr;\r | |
725 | \r | |
726 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT);\r | |
727 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_MISC_PWR_MGMT, Msr);\r | |
728 | @endcode\r | |
367f5c9c | 729 | @note MSR_SANDY_BRIDGE_MISC_PWR_MGMT is defined as MSR_MISC_PWR_MGMT in SDM.\r |
dc5d621c | 730 | **/\r |
2f88bd3a | 731 | #define MSR_SANDY_BRIDGE_MISC_PWR_MGMT 0x000001AA\r |
dc5d621c MK |
732 | \r |
733 | /**\r | |
ba1a2d11 ED |
734 | Thread. Last Branch Record Filtering Select Register (R/W) See Section\r |
735 | 17.9.2, "Filtering of Last Branch Records.".\r | |
dc5d621c MK |
736 | \r |
737 | @param ECX MSR_SANDY_BRIDGE_LBR_SELECT (0x000001C8)\r | |
738 | @param EAX Lower 32-bits of MSR value.\r | |
739 | Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r | |
740 | @param EDX Upper 32-bits of MSR value.\r | |
741 | Described by the type MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER.\r | |
742 | \r | |
743 | <b>Example usage</b>\r | |
744 | @code\r | |
745 | MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER Msr;\r | |
746 | \r | |
747 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT);\r | |
748 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LBR_SELECT, Msr.Uint64);\r | |
749 | @endcode\r | |
367f5c9c | 750 | @note MSR_SANDY_BRIDGE_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
dc5d621c | 751 | **/\r |
2f88bd3a | 752 | #define MSR_SANDY_BRIDGE_LBR_SELECT 0x000001C8\r |
dc5d621c MK |
753 | \r |
754 | /**\r | |
755 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_LBR_SELECT\r | |
756 | **/\r | |
757 | typedef union {\r | |
758 | ///\r | |
759 | /// Individual bit fields\r | |
760 | ///\r | |
761 | struct {\r | |
762 | ///\r | |
763 | /// [Bit 0] CPL_EQ_0.\r | |
764 | ///\r | |
2f88bd3a | 765 | UINT32 CPL_EQ_0 : 1;\r |
dc5d621c MK |
766 | ///\r |
767 | /// [Bit 1] CPL_NEQ_0.\r | |
768 | ///\r | |
2f88bd3a | 769 | UINT32 CPL_NEQ_0 : 1;\r |
dc5d621c MK |
770 | ///\r |
771 | /// [Bit 2] JCC.\r | |
772 | ///\r | |
2f88bd3a | 773 | UINT32 JCC : 1;\r |
dc5d621c MK |
774 | ///\r |
775 | /// [Bit 3] NEAR_REL_CALL.\r | |
776 | ///\r | |
2f88bd3a | 777 | UINT32 NEAR_REL_CALL : 1;\r |
dc5d621c MK |
778 | ///\r |
779 | /// [Bit 4] NEAR_IND_CALL.\r | |
780 | ///\r | |
2f88bd3a | 781 | UINT32 NEAR_IND_CALL : 1;\r |
dc5d621c MK |
782 | ///\r |
783 | /// [Bit 5] NEAR_RET.\r | |
784 | ///\r | |
2f88bd3a | 785 | UINT32 NEAR_RET : 1;\r |
dc5d621c MK |
786 | ///\r |
787 | /// [Bit 6] NEAR_IND_JMP.\r | |
788 | ///\r | |
2f88bd3a | 789 | UINT32 NEAR_IND_JMP : 1;\r |
dc5d621c MK |
790 | ///\r |
791 | /// [Bit 7] NEAR_REL_JMP.\r | |
792 | ///\r | |
2f88bd3a | 793 | UINT32 NEAR_REL_JMP : 1;\r |
dc5d621c MK |
794 | ///\r |
795 | /// [Bit 8] FAR_BRANCH.\r | |
796 | ///\r | |
2f88bd3a MK |
797 | UINT32 FAR_BRANCH : 1;\r |
798 | UINT32 Reserved1 : 23;\r | |
799 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
800 | } Bits;\r |
801 | ///\r | |
802 | /// All bit fields as a 32-bit value\r | |
803 | ///\r | |
2f88bd3a | 804 | UINT32 Uint32;\r |
dc5d621c MK |
805 | ///\r |
806 | /// All bit fields as a 64-bit value\r | |
807 | ///\r | |
2f88bd3a | 808 | UINT64 Uint64;\r |
dc5d621c MK |
809 | } MSR_SANDY_BRIDGE_LBR_SELECT_REGISTER;\r |
810 | \r | |
dc5d621c MK |
811 | /**\r |
812 | Thread. Last Branch Record Stack TOS (R/W) Contains an index (bits 0-3)\r | |
813 | that points to the MSR containing the most recent branch record. See\r | |
814 | MSR_LASTBRANCH_0_FROM_IP (at 680H).\r | |
815 | \r | |
816 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_TOS (0x000001C9)\r | |
817 | @param EAX Lower 32-bits of MSR value.\r | |
818 | @param EDX Upper 32-bits of MSR value.\r | |
819 | \r | |
820 | <b>Example usage</b>\r | |
821 | @code\r | |
822 | UINT64 Msr;\r | |
823 | \r | |
824 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS);\r | |
825 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_TOS, Msr);\r | |
826 | @endcode\r | |
367f5c9c | 827 | @note MSR_SANDY_BRIDGE_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
dc5d621c | 828 | **/\r |
2f88bd3a | 829 | #define MSR_SANDY_BRIDGE_LASTBRANCH_TOS 0x000001C9\r |
dc5d621c MK |
830 | \r |
831 | /**\r | |
832 | Thread. Last Exception Record From Linear IP (R) Contains a pointer to the\r | |
833 | last branch instruction that the processor executed prior to the last\r | |
834 | exception that was generated or the last interrupt that was handled.\r | |
835 | \r | |
836 | @param ECX MSR_SANDY_BRIDGE_LER_FROM_LIP (0x000001DD)\r | |
837 | @param EAX Lower 32-bits of MSR value.\r | |
838 | @param EDX Upper 32-bits of MSR value.\r | |
839 | \r | |
840 | <b>Example usage</b>\r | |
841 | @code\r | |
842 | UINT64 Msr;\r | |
843 | \r | |
844 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_FROM_LIP);\r | |
845 | @endcode\r | |
367f5c9c | 846 | @note MSR_SANDY_BRIDGE_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
dc5d621c | 847 | **/\r |
2f88bd3a | 848 | #define MSR_SANDY_BRIDGE_LER_FROM_LIP 0x000001DD\r |
dc5d621c MK |
849 | \r |
850 | /**\r | |
851 | Thread. Last Exception Record To Linear IP (R) This area contains a pointer\r | |
852 | to the target of the last branch instruction that the processor executed\r | |
853 | prior to the last exception that was generated or the last interrupt that\r | |
854 | was handled.\r | |
855 | \r | |
856 | @param ECX MSR_SANDY_BRIDGE_LER_TO_LIP (0x000001DE)\r | |
857 | @param EAX Lower 32-bits of MSR value.\r | |
858 | @param EDX Upper 32-bits of MSR value.\r | |
859 | \r | |
860 | <b>Example usage</b>\r | |
861 | @code\r | |
862 | UINT64 Msr;\r | |
863 | \r | |
864 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LER_TO_LIP);\r | |
865 | @endcode\r | |
367f5c9c | 866 | @note MSR_SANDY_BRIDGE_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
dc5d621c | 867 | **/\r |
2f88bd3a | 868 | #define MSR_SANDY_BRIDGE_LER_TO_LIP 0x000001DE\r |
dc5d621c MK |
869 | \r |
870 | /**\r | |
871 | Core. See http://biosbits.org.\r | |
872 | \r | |
873 | @param ECX MSR_SANDY_BRIDGE_POWER_CTL (0x000001FC)\r | |
874 | @param EAX Lower 32-bits of MSR value.\r | |
875 | @param EDX Upper 32-bits of MSR value.\r | |
876 | \r | |
877 | <b>Example usage</b>\r | |
878 | @code\r | |
879 | UINT64 Msr;\r | |
880 | \r | |
881 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_POWER_CTL);\r | |
882 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_POWER_CTL, Msr);\r | |
883 | @endcode\r | |
367f5c9c | 884 | @note MSR_SANDY_BRIDGE_POWER_CTL is defined as MSR_POWER_CTL in SDM.\r |
dc5d621c | 885 | **/\r |
2f88bd3a | 886 | #define MSR_SANDY_BRIDGE_POWER_CTL 0x000001FC\r |
dc5d621c MK |
887 | \r |
888 | /**\r | |
889 | Package. Always 0 (CMCI not supported).\r | |
890 | \r | |
0f16be6d | 891 | @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL2 (0x00000284)\r |
dc5d621c MK |
892 | @param EAX Lower 32-bits of MSR value.\r |
893 | @param EDX Upper 32-bits of MSR value.\r | |
894 | \r | |
895 | <b>Example usage</b>\r | |
896 | @code\r | |
897 | UINT64 Msr;\r | |
898 | \r | |
0f16be6d HW |
899 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2);\r |
900 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL2, Msr);\r | |
dc5d621c | 901 | @endcode\r |
0f16be6d | 902 | @note MSR_SANDY_BRIDGE_IA32_MC4_CTL2 is defined as IA32_MC4_CTL2 in SDM.\r |
dc5d621c | 903 | **/\r |
2f88bd3a | 904 | #define MSR_SANDY_BRIDGE_IA32_MC4_CTL2 0x00000284\r |
dc5d621c MK |
905 | \r |
906 | /**\r | |
ba1a2d11 | 907 | See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r |
dc5d621c | 908 | \r |
0f16be6d | 909 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS (0x0000038E)\r |
dc5d621c | 910 | @param EAX Lower 32-bits of MSR value.\r |
0f16be6d | 911 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
dc5d621c | 912 | @param EDX Upper 32-bits of MSR value.\r |
0f16be6d | 913 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER.\r |
dc5d621c MK |
914 | \r |
915 | <b>Example usage</b>\r | |
916 | @code\r | |
0f16be6d | 917 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER Msr;\r |
dc5d621c | 918 | \r |
0f16be6d HW |
919 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS);\r |
920 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
dc5d621c | 921 | @endcode\r |
0f16be6d | 922 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS is defined as IA32_PERF_GLOBAL_STATUS in SDM.\r |
dc5d621c | 923 | **/\r |
2f88bd3a | 924 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS 0x0000038E\r |
dc5d621c MK |
925 | \r |
926 | /**\r | |
927 | MSR information returned for MSR index\r | |
0f16be6d | 928 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS\r |
dc5d621c MK |
929 | **/\r |
930 | typedef union {\r | |
931 | ///\r | |
932 | /// Individual bit fields\r | |
933 | ///\r | |
934 | struct {\r | |
935 | ///\r | |
936 | /// [Bit 0] Thread. Ovf_PMC0.\r | |
937 | ///\r | |
2f88bd3a | 938 | UINT32 Ovf_PMC0 : 1;\r |
dc5d621c MK |
939 | ///\r |
940 | /// [Bit 1] Thread. Ovf_PMC1.\r | |
941 | ///\r | |
2f88bd3a | 942 | UINT32 Ovf_PMC1 : 1;\r |
dc5d621c MK |
943 | ///\r |
944 | /// [Bit 2] Thread. Ovf_PMC2.\r | |
945 | ///\r | |
2f88bd3a | 946 | UINT32 Ovf_PMC2 : 1;\r |
dc5d621c MK |
947 | ///\r |
948 | /// [Bit 3] Thread. Ovf_PMC3.\r | |
949 | ///\r | |
2f88bd3a | 950 | UINT32 Ovf_PMC3 : 1;\r |
dc5d621c MK |
951 | ///\r |
952 | /// [Bit 4] Core. Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r | |
953 | ///\r | |
2f88bd3a | 954 | UINT32 Ovf_PMC4 : 1;\r |
dc5d621c MK |
955 | ///\r |
956 | /// [Bit 5] Core. Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r | |
957 | ///\r | |
2f88bd3a | 958 | UINT32 Ovf_PMC5 : 1;\r |
dc5d621c MK |
959 | ///\r |
960 | /// [Bit 6] Core. Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r | |
961 | ///\r | |
2f88bd3a | 962 | UINT32 Ovf_PMC6 : 1;\r |
dc5d621c MK |
963 | ///\r |
964 | /// [Bit 7] Core. Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r | |
965 | ///\r | |
2f88bd3a MK |
966 | UINT32 Ovf_PMC7 : 1;\r |
967 | UINT32 Reserved1 : 24;\r | |
dc5d621c MK |
968 | ///\r |
969 | /// [Bit 32] Thread. Ovf_FixedCtr0.\r | |
970 | ///\r | |
2f88bd3a | 971 | UINT32 Ovf_FixedCtr0 : 1;\r |
dc5d621c MK |
972 | ///\r |
973 | /// [Bit 33] Thread. Ovf_FixedCtr1.\r | |
974 | ///\r | |
2f88bd3a | 975 | UINT32 Ovf_FixedCtr1 : 1;\r |
dc5d621c MK |
976 | ///\r |
977 | /// [Bit 34] Thread. Ovf_FixedCtr2.\r | |
978 | ///\r | |
2f88bd3a MK |
979 | UINT32 Ovf_FixedCtr2 : 1;\r |
980 | UINT32 Reserved2 : 26;\r | |
dc5d621c MK |
981 | ///\r |
982 | /// [Bit 61] Thread. Ovf_Uncore.\r | |
983 | ///\r | |
2f88bd3a | 984 | UINT32 Ovf_Uncore : 1;\r |
dc5d621c MK |
985 | ///\r |
986 | /// [Bit 62] Thread. Ovf_BufDSSAVE.\r | |
987 | ///\r | |
2f88bd3a | 988 | UINT32 Ovf_BufDSSAVE : 1;\r |
dc5d621c MK |
989 | ///\r |
990 | /// [Bit 63] Thread. CondChgd.\r | |
991 | ///\r | |
2f88bd3a | 992 | UINT32 CondChgd : 1;\r |
dc5d621c MK |
993 | } Bits;\r |
994 | ///\r | |
995 | /// All bit fields as a 64-bit value\r | |
996 | ///\r | |
2f88bd3a | 997 | UINT64 Uint64;\r |
0f16be6d | 998 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_STATUS_REGISTER;\r |
dc5d621c | 999 | \r |
dc5d621c | 1000 | /**\r |
ba1a2d11 | 1001 | Thread. See Table 2-2. See Section 18.6.2.2, "Global Counter Control\r |
dc5d621c MK |
1002 | Facilities.".\r |
1003 | \r | |
1004 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL (0x0000038F)\r | |
1005 | @param EAX Lower 32-bits of MSR value.\r | |
1006 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
1007 | @param EDX Upper 32-bits of MSR value.\r | |
1008 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER.\r | |
1009 | \r | |
1010 | <b>Example usage</b>\r | |
1011 | @code\r | |
1012 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
1013 | \r | |
1014 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL);\r | |
1015 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
1016 | @endcode\r | |
367f5c9c | 1017 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL is defined as IA32_PERF_GLOBAL_CTRL in SDM.\r |
dc5d621c | 1018 | **/\r |
2f88bd3a | 1019 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL 0x0000038F\r |
dc5d621c MK |
1020 | \r |
1021 | /**\r | |
1022 | MSR information returned for MSR index\r | |
1023 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL\r | |
1024 | **/\r | |
1025 | typedef union {\r | |
1026 | ///\r | |
1027 | /// Individual bit fields\r | |
1028 | ///\r | |
1029 | struct {\r | |
1030 | ///\r | |
1031 | /// [Bit 0] Thread. Set 1 to enable PMC0 to count.\r | |
1032 | ///\r | |
2f88bd3a | 1033 | UINT32 PCM0_EN : 1;\r |
dc5d621c MK |
1034 | ///\r |
1035 | /// [Bit 1] Thread. Set 1 to enable PMC1 to count.\r | |
1036 | ///\r | |
2f88bd3a | 1037 | UINT32 PCM1_EN : 1;\r |
dc5d621c MK |
1038 | ///\r |
1039 | /// [Bit 2] Thread. Set 1 to enable PMC2 to count.\r | |
1040 | ///\r | |
2f88bd3a | 1041 | UINT32 PCM2_EN : 1;\r |
dc5d621c MK |
1042 | ///\r |
1043 | /// [Bit 3] Thread. Set 1 to enable PMC3 to count.\r | |
1044 | ///\r | |
2f88bd3a | 1045 | UINT32 PCM3_EN : 1;\r |
dc5d621c MK |
1046 | ///\r |
1047 | /// [Bit 4] Core. Set 1 to enable PMC4 to count (if CPUID.0AH:EAX[15:8] >\r | |
1048 | /// 4).\r | |
1049 | ///\r | |
2f88bd3a | 1050 | UINT32 PCM4_EN : 1;\r |
dc5d621c MK |
1051 | ///\r |
1052 | /// [Bit 5] Core. Set 1 to enable PMC5 to count (if CPUID.0AH:EAX[15:8] >\r | |
1053 | /// 5).\r | |
1054 | ///\r | |
2f88bd3a | 1055 | UINT32 PCM5_EN : 1;\r |
dc5d621c MK |
1056 | ///\r |
1057 | /// [Bit 6] Core. Set 1 to enable PMC6 to count (if CPUID.0AH:EAX[15:8] >\r | |
1058 | /// 6).\r | |
1059 | ///\r | |
2f88bd3a | 1060 | UINT32 PCM6_EN : 1;\r |
dc5d621c MK |
1061 | ///\r |
1062 | /// [Bit 7] Core. Set 1 to enable PMC7 to count (if CPUID.0AH:EAX[15:8] >\r | |
1063 | /// 7).\r | |
1064 | ///\r | |
2f88bd3a MK |
1065 | UINT32 PCM7_EN : 1;\r |
1066 | UINT32 Reserved1 : 24;\r | |
dc5d621c MK |
1067 | ///\r |
1068 | /// [Bit 32] Thread. Set 1 to enable FixedCtr0 to count.\r | |
1069 | ///\r | |
2f88bd3a | 1070 | UINT32 FIXED_CTR0 : 1;\r |
dc5d621c MK |
1071 | ///\r |
1072 | /// [Bit 33] Thread. Set 1 to enable FixedCtr1 to count.\r | |
1073 | ///\r | |
2f88bd3a | 1074 | UINT32 FIXED_CTR1 : 1;\r |
dc5d621c MK |
1075 | ///\r |
1076 | /// [Bit 34] Thread. Set 1 to enable FixedCtr2 to count.\r | |
1077 | ///\r | |
2f88bd3a MK |
1078 | UINT32 FIXED_CTR2 : 1;\r |
1079 | UINT32 Reserved2 : 29;\r | |
dc5d621c MK |
1080 | } Bits;\r |
1081 | ///\r | |
1082 | /// All bit fields as a 64-bit value\r | |
1083 | ///\r | |
2f88bd3a | 1084 | UINT64 Uint64;\r |
dc5d621c MK |
1085 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_CTRL_REGISTER;\r |
1086 | \r | |
dc5d621c | 1087 | /**\r |
ba1a2d11 | 1088 | See Table 2-2. See Section 18.6.2.2, "Global Counter Control Facilities.".\r |
dc5d621c MK |
1089 | \r |
1090 | @param ECX MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL (0x00000390)\r | |
1091 | @param EAX Lower 32-bits of MSR value.\r | |
1092 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
1093 | @param EDX Upper 32-bits of MSR value.\r | |
1094 | Described by the type MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER.\r | |
1095 | \r | |
1096 | <b>Example usage</b>\r | |
1097 | @code\r | |
1098 | MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER Msr;\r | |
1099 | \r | |
1100 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL);\r | |
1101 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL, Msr.Uint64);\r | |
1102 | @endcode\r | |
367f5c9c | 1103 | @note MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL is defined as IA32_PERF_GLOBAL_OVF_CTRL in SDM.\r |
dc5d621c | 1104 | **/\r |
2f88bd3a | 1105 | #define MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL 0x00000390\r |
dc5d621c MK |
1106 | \r |
1107 | /**\r | |
1108 | MSR information returned for MSR index\r | |
1109 | #MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL\r | |
1110 | **/\r | |
1111 | typedef union {\r | |
1112 | ///\r | |
1113 | /// Individual bit fields\r | |
1114 | ///\r | |
1115 | struct {\r | |
1116 | ///\r | |
1117 | /// [Bit 0] Thread. Set 1 to clear Ovf_PMC0.\r | |
1118 | ///\r | |
2f88bd3a | 1119 | UINT32 Ovf_PMC0 : 1;\r |
dc5d621c MK |
1120 | ///\r |
1121 | /// [Bit 1] Thread. Set 1 to clear Ovf_PMC1.\r | |
1122 | ///\r | |
2f88bd3a | 1123 | UINT32 Ovf_PMC1 : 1;\r |
dc5d621c MK |
1124 | ///\r |
1125 | /// [Bit 2] Thread. Set 1 to clear Ovf_PMC2.\r | |
1126 | ///\r | |
2f88bd3a | 1127 | UINT32 Ovf_PMC2 : 1;\r |
dc5d621c MK |
1128 | ///\r |
1129 | /// [Bit 3] Thread. Set 1 to clear Ovf_PMC3.\r | |
1130 | ///\r | |
2f88bd3a | 1131 | UINT32 Ovf_PMC3 : 1;\r |
dc5d621c MK |
1132 | ///\r |
1133 | /// [Bit 4] Core. Set 1 to clear Ovf_PMC4 (if CPUID.0AH:EAX[15:8] > 4).\r | |
1134 | ///\r | |
2f88bd3a | 1135 | UINT32 Ovf_PMC4 : 1;\r |
dc5d621c MK |
1136 | ///\r |
1137 | /// [Bit 5] Core. Set 1 to clear Ovf_PMC5 (if CPUID.0AH:EAX[15:8] > 5).\r | |
1138 | ///\r | |
2f88bd3a | 1139 | UINT32 Ovf_PMC5 : 1;\r |
dc5d621c MK |
1140 | ///\r |
1141 | /// [Bit 6] Core. Set 1 to clear Ovf_PMC6 (if CPUID.0AH:EAX[15:8] > 6).\r | |
1142 | ///\r | |
2f88bd3a | 1143 | UINT32 Ovf_PMC6 : 1;\r |
dc5d621c MK |
1144 | ///\r |
1145 | /// [Bit 7] Core. Set 1 to clear Ovf_PMC7 (if CPUID.0AH:EAX[15:8] > 7).\r | |
1146 | ///\r | |
2f88bd3a MK |
1147 | UINT32 Ovf_PMC7 : 1;\r |
1148 | UINT32 Reserved1 : 24;\r | |
dc5d621c MK |
1149 | ///\r |
1150 | /// [Bit 32] Thread. Set 1 to clear Ovf_FixedCtr0.\r | |
1151 | ///\r | |
2f88bd3a | 1152 | UINT32 Ovf_FixedCtr0 : 1;\r |
dc5d621c MK |
1153 | ///\r |
1154 | /// [Bit 33] Thread. Set 1 to clear Ovf_FixedCtr1.\r | |
1155 | ///\r | |
2f88bd3a | 1156 | UINT32 Ovf_FixedCtr1 : 1;\r |
dc5d621c MK |
1157 | ///\r |
1158 | /// [Bit 34] Thread. Set 1 to clear Ovf_FixedCtr2.\r | |
1159 | ///\r | |
2f88bd3a MK |
1160 | UINT32 Ovf_FixedCtr2 : 1;\r |
1161 | UINT32 Reserved2 : 26;\r | |
dc5d621c MK |
1162 | ///\r |
1163 | /// [Bit 61] Thread. Set 1 to clear Ovf_Uncore.\r | |
1164 | ///\r | |
2f88bd3a | 1165 | UINT32 Ovf_Uncore : 1;\r |
dc5d621c MK |
1166 | ///\r |
1167 | /// [Bit 62] Thread. Set 1 to clear Ovf_BufDSSAVE.\r | |
1168 | ///\r | |
2f88bd3a | 1169 | UINT32 Ovf_BufDSSAVE : 1;\r |
dc5d621c MK |
1170 | ///\r |
1171 | /// [Bit 63] Thread. Set 1 to clear CondChgd.\r | |
1172 | ///\r | |
2f88bd3a | 1173 | UINT32 CondChgd : 1;\r |
dc5d621c MK |
1174 | } Bits;\r |
1175 | ///\r | |
1176 | /// All bit fields as a 64-bit value\r | |
1177 | ///\r | |
2f88bd3a | 1178 | UINT64 Uint64;\r |
dc5d621c MK |
1179 | } MSR_SANDY_BRIDGE_IA32_PERF_GLOBAL_OVF_CTRL_REGISTER;\r |
1180 | \r | |
dc5d621c | 1181 | /**\r |
ba1a2d11 | 1182 | Thread. See Section 18.3.1.1.1, "Processor Event Based Sampling (PEBS).".\r |
dc5d621c MK |
1183 | \r |
1184 | @param ECX MSR_SANDY_BRIDGE_PEBS_ENABLE (0x000003F1)\r | |
1185 | @param EAX Lower 32-bits of MSR value.\r | |
1186 | Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
1187 | @param EDX Upper 32-bits of MSR value.\r | |
1188 | Described by the type MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER.\r | |
1189 | \r | |
1190 | <b>Example usage</b>\r | |
1191 | @code\r | |
1192 | MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER Msr;\r | |
1193 | \r | |
1194 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE);\r | |
1195 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_ENABLE, Msr.Uint64);\r | |
1196 | @endcode\r | |
367f5c9c | 1197 | @note MSR_SANDY_BRIDGE_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
dc5d621c | 1198 | **/\r |
2f88bd3a | 1199 | #define MSR_SANDY_BRIDGE_PEBS_ENABLE 0x000003F1\r |
dc5d621c MK |
1200 | \r |
1201 | /**\r | |
1202 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_ENABLE\r | |
1203 | **/\r | |
1204 | typedef union {\r | |
1205 | ///\r | |
1206 | /// Individual bit fields\r | |
1207 | ///\r | |
1208 | struct {\r | |
1209 | ///\r | |
1210 | /// [Bit 0] Enable PEBS on IA32_PMC0. (R/W).\r | |
1211 | ///\r | |
2f88bd3a | 1212 | UINT32 PEBS_EN_PMC0 : 1;\r |
dc5d621c MK |
1213 | ///\r |
1214 | /// [Bit 1] Enable PEBS on IA32_PMC1. (R/W).\r | |
1215 | ///\r | |
2f88bd3a | 1216 | UINT32 PEBS_EN_PMC1 : 1;\r |
dc5d621c MK |
1217 | ///\r |
1218 | /// [Bit 2] Enable PEBS on IA32_PMC2. (R/W).\r | |
1219 | ///\r | |
2f88bd3a | 1220 | UINT32 PEBS_EN_PMC2 : 1;\r |
dc5d621c MK |
1221 | ///\r |
1222 | /// [Bit 3] Enable PEBS on IA32_PMC3. (R/W).\r | |
1223 | ///\r | |
2f88bd3a MK |
1224 | UINT32 PEBS_EN_PMC3 : 1;\r |
1225 | UINT32 Reserved1 : 28;\r | |
dc5d621c MK |
1226 | ///\r |
1227 | /// [Bit 32] Enable Load Latency on IA32_PMC0. (R/W).\r | |
1228 | ///\r | |
2f88bd3a | 1229 | UINT32 LL_EN_PMC0 : 1;\r |
dc5d621c MK |
1230 | ///\r |
1231 | /// [Bit 33] Enable Load Latency on IA32_PMC1. (R/W).\r | |
1232 | ///\r | |
2f88bd3a | 1233 | UINT32 LL_EN_PMC1 : 1;\r |
dc5d621c MK |
1234 | ///\r |
1235 | /// [Bit 34] Enable Load Latency on IA32_PMC2. (R/W).\r | |
1236 | ///\r | |
2f88bd3a | 1237 | UINT32 LL_EN_PMC2 : 1;\r |
dc5d621c MK |
1238 | ///\r |
1239 | /// [Bit 35] Enable Load Latency on IA32_PMC3. (R/W).\r | |
1240 | ///\r | |
2f88bd3a MK |
1241 | UINT32 LL_EN_PMC3 : 1;\r |
1242 | UINT32 Reserved2 : 27;\r | |
dc5d621c MK |
1243 | ///\r |
1244 | /// [Bit 63] Enable Precise Store. (R/W).\r | |
1245 | ///\r | |
2f88bd3a | 1246 | UINT32 PS_EN : 1;\r |
dc5d621c MK |
1247 | } Bits;\r |
1248 | ///\r | |
1249 | /// All bit fields as a 64-bit value\r | |
1250 | ///\r | |
2f88bd3a | 1251 | UINT64 Uint64;\r |
dc5d621c MK |
1252 | } MSR_SANDY_BRIDGE_PEBS_ENABLE_REGISTER;\r |
1253 | \r | |
dc5d621c | 1254 | /**\r |
ba1a2d11 | 1255 | Thread. See Section 18.3.1.1.2, "Load Latency Performance Monitoring\r |
dc5d621c MK |
1256 | Facility.".\r |
1257 | \r | |
1258 | @param ECX MSR_SANDY_BRIDGE_PEBS_LD_LAT (0x000003F6)\r | |
1259 | @param EAX Lower 32-bits of MSR value.\r | |
1260 | Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r | |
1261 | @param EDX Upper 32-bits of MSR value.\r | |
1262 | Described by the type MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER.\r | |
1263 | \r | |
1264 | <b>Example usage</b>\r | |
1265 | @code\r | |
1266 | MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER Msr;\r | |
1267 | \r | |
1268 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT);\r | |
1269 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_LD_LAT, Msr.Uint64);\r | |
1270 | @endcode\r | |
367f5c9c | 1271 | @note MSR_SANDY_BRIDGE_PEBS_LD_LAT is defined as MSR_PEBS_LD_LAT in SDM.\r |
dc5d621c | 1272 | **/\r |
2f88bd3a | 1273 | #define MSR_SANDY_BRIDGE_PEBS_LD_LAT 0x000003F6\r |
dc5d621c MK |
1274 | \r |
1275 | /**\r | |
1276 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_LD_LAT\r | |
1277 | **/\r | |
1278 | typedef union {\r | |
1279 | ///\r | |
1280 | /// Individual bit fields\r | |
1281 | ///\r | |
1282 | struct {\r | |
1283 | ///\r | |
1284 | /// [Bits 15:0] Minimum threshold latency value of tagged load operation\r | |
1285 | /// that will be counted. (R/W).\r | |
1286 | ///\r | |
2f88bd3a MK |
1287 | UINT32 MinimumThreshold : 16;\r |
1288 | UINT32 Reserved1 : 16;\r | |
1289 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
1290 | } Bits;\r |
1291 | ///\r | |
1292 | /// All bit fields as a 32-bit value\r | |
1293 | ///\r | |
2f88bd3a | 1294 | UINT32 Uint32;\r |
dc5d621c MK |
1295 | ///\r |
1296 | /// All bit fields as a 64-bit value\r | |
1297 | ///\r | |
2f88bd3a | 1298 | UINT64 Uint64;\r |
dc5d621c MK |
1299 | } MSR_SANDY_BRIDGE_PEBS_LD_LAT_REGISTER;\r |
1300 | \r | |
dc5d621c MK |
1301 | /**\r |
1302 | Package. Note: C-state values are processor specific C-state code names,\r | |
1303 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C3\r | |
1304 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1305 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
1306 | \r | |
1307 | @param ECX MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY (0x000003F8)\r | |
1308 | @param EAX Lower 32-bits of MSR value.\r | |
1309 | @param EDX Upper 32-bits of MSR value.\r | |
1310 | \r | |
1311 | <b>Example usage</b>\r | |
1312 | @code\r | |
1313 | UINT64 Msr;\r | |
1314 | \r | |
1315 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY);\r | |
1316 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY, Msr);\r | |
1317 | @endcode\r | |
367f5c9c | 1318 | @note MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r |
dc5d621c | 1319 | **/\r |
2f88bd3a | 1320 | #define MSR_SANDY_BRIDGE_PKG_C3_RESIDENCY 0x000003F8\r |
dc5d621c MK |
1321 | \r |
1322 | /**\r | |
1323 | Package. Note: C-state values are processor specific C-state code names,\r | |
1324 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C6\r | |
1325 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1326 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
1327 | \r | |
1328 | @param ECX MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY (0x000003F9)\r | |
1329 | @param EAX Lower 32-bits of MSR value.\r | |
1330 | @param EDX Upper 32-bits of MSR value.\r | |
1331 | \r | |
1332 | <b>Example usage</b>\r | |
1333 | @code\r | |
1334 | UINT64 Msr;\r | |
1335 | \r | |
1336 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY);\r | |
1337 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY, Msr);\r | |
1338 | @endcode\r | |
367f5c9c | 1339 | @note MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
dc5d621c | 1340 | **/\r |
2f88bd3a | 1341 | #define MSR_SANDY_BRIDGE_PKG_C6_RESIDENCY 0x000003F9\r |
dc5d621c MK |
1342 | \r |
1343 | /**\r | |
1344 | Package. Note: C-state values are processor specific C-state code names,\r | |
1345 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C7\r | |
1346 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1347 | processor-specific C7 states. Count at the same frequency as the TSC.\r | |
1348 | \r | |
1349 | @param ECX MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY (0x000003FA)\r | |
1350 | @param EAX Lower 32-bits of MSR value.\r | |
1351 | @param EDX Upper 32-bits of MSR value.\r | |
1352 | \r | |
1353 | <b>Example usage</b>\r | |
1354 | @code\r | |
1355 | UINT64 Msr;\r | |
1356 | \r | |
1357 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY);\r | |
1358 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY, Msr);\r | |
1359 | @endcode\r | |
367f5c9c | 1360 | @note MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r |
dc5d621c | 1361 | **/\r |
2f88bd3a | 1362 | #define MSR_SANDY_BRIDGE_PKG_C7_RESIDENCY 0x000003FA\r |
dc5d621c MK |
1363 | \r |
1364 | /**\r | |
1365 | Core. Note: C-state values are processor specific C-state code names,\r | |
1366 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C3\r | |
1367 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1368 | processor-specific C3 states. Count at the same frequency as the TSC.\r | |
1369 | \r | |
1370 | @param ECX MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY (0x000003FC)\r | |
1371 | @param EAX Lower 32-bits of MSR value.\r | |
1372 | @param EDX Upper 32-bits of MSR value.\r | |
1373 | \r | |
1374 | <b>Example usage</b>\r | |
1375 | @code\r | |
1376 | UINT64 Msr;\r | |
1377 | \r | |
1378 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY);\r | |
1379 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY, Msr);\r | |
1380 | @endcode\r | |
367f5c9c | 1381 | @note MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY is defined as MSR_CORE_C3_RESIDENCY in SDM.\r |
dc5d621c | 1382 | **/\r |
2f88bd3a | 1383 | #define MSR_SANDY_BRIDGE_CORE_C3_RESIDENCY 0x000003FC\r |
dc5d621c MK |
1384 | \r |
1385 | /**\r | |
1386 | Core. Note: C-state values are processor specific C-state code names,\r | |
1387 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C6\r | |
1388 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1389 | processor-specific C6 states. Count at the same frequency as the TSC.\r | |
1390 | \r | |
1391 | @param ECX MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY (0x000003FD)\r | |
1392 | @param EAX Lower 32-bits of MSR value.\r | |
1393 | @param EDX Upper 32-bits of MSR value.\r | |
1394 | \r | |
1395 | <b>Example usage</b>\r | |
1396 | @code\r | |
1397 | UINT64 Msr;\r | |
1398 | \r | |
1399 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY);\r | |
1400 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY, Msr);\r | |
1401 | @endcode\r | |
367f5c9c | 1402 | @note MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
dc5d621c | 1403 | **/\r |
2f88bd3a | 1404 | #define MSR_SANDY_BRIDGE_CORE_C6_RESIDENCY 0x000003FD\r |
dc5d621c MK |
1405 | \r |
1406 | /**\r | |
1407 | Core. Note: C-state values are processor specific C-state code names,\r | |
1408 | unrelated to MWAIT extension C-state parameters or ACPI CStates. CORE C7\r | |
1409 | Residency Counter. (R/O) Value since last reset that this core is in\r | |
1410 | processor-specific C7 states. Count at the same frequency as the TSC.\r | |
1411 | \r | |
1412 | @param ECX MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY (0x000003FE)\r | |
1413 | @param EAX Lower 32-bits of MSR value.\r | |
1414 | @param EDX Upper 32-bits of MSR value.\r | |
1415 | \r | |
1416 | <b>Example usage</b>\r | |
1417 | @code\r | |
1418 | UINT64 Msr;\r | |
1419 | \r | |
1420 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY);\r | |
1421 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY, Msr);\r | |
1422 | @endcode\r | |
367f5c9c | 1423 | @note MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY is defined as MSR_CORE_C7_RESIDENCY in SDM.\r |
dc5d621c | 1424 | **/\r |
2f88bd3a | 1425 | #define MSR_SANDY_BRIDGE_CORE_C7_RESIDENCY 0x000003FE\r |
dc5d621c MK |
1426 | \r |
1427 | /**\r | |
1428 | Core. See Section 15.3.2.1, "IA32_MCi_CTL MSRs.".\r | |
1429 | \r | |
0f16be6d | 1430 | @param ECX MSR_SANDY_BRIDGE_IA32_MC4_CTL (0x00000410)\r |
dc5d621c | 1431 | @param EAX Lower 32-bits of MSR value.\r |
0f16be6d | 1432 | Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r |
dc5d621c | 1433 | @param EDX Upper 32-bits of MSR value.\r |
0f16be6d | 1434 | Described by the type MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER.\r |
dc5d621c MK |
1435 | \r |
1436 | <b>Example usage</b>\r | |
1437 | @code\r | |
0f16be6d | 1438 | MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER Msr;\r |
dc5d621c | 1439 | \r |
0f16be6d HW |
1440 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL);\r |
1441 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_IA32_MC4_CTL, Msr.Uint64);\r | |
dc5d621c | 1442 | @endcode\r |
0f16be6d | 1443 | @note MSR_SANDY_BRIDGE_IA32_MC4_CTL is defined as IA32_MC4_CTL in SDM.\r |
dc5d621c | 1444 | **/\r |
2f88bd3a | 1445 | #define MSR_SANDY_BRIDGE_IA32_MC4_CTL 0x00000410\r |
dc5d621c MK |
1446 | \r |
1447 | /**\r | |
0f16be6d | 1448 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_IA32_MC4_CTL\r |
dc5d621c MK |
1449 | **/\r |
1450 | typedef union {\r | |
1451 | ///\r | |
1452 | /// Individual bit fields\r | |
1453 | ///\r | |
1454 | struct {\r | |
1455 | ///\r | |
1456 | /// [Bit 0] PCU Hardware Error (R/W) When set, enables signaling of PCU\r | |
1457 | /// hardware detected errors.\r | |
1458 | ///\r | |
2f88bd3a | 1459 | UINT32 PCUHardwareError : 1;\r |
dc5d621c MK |
1460 | ///\r |
1461 | /// [Bit 1] PCU Controller Error (R/W) When set, enables signaling of PCU\r | |
1462 | /// controller detected errors.\r | |
1463 | ///\r | |
2f88bd3a | 1464 | UINT32 PCUControllerError : 1;\r |
dc5d621c MK |
1465 | ///\r |
1466 | /// [Bit 2] PCU Firmware Error (R/W) When set, enables signaling of PCU\r | |
1467 | /// firmware detected errors.\r | |
1468 | ///\r | |
2f88bd3a MK |
1469 | UINT32 PCUFirmwareError : 1;\r |
1470 | UINT32 Reserved1 : 29;\r | |
1471 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
1472 | } Bits;\r |
1473 | ///\r | |
1474 | /// All bit fields as a 32-bit value\r | |
1475 | ///\r | |
2f88bd3a | 1476 | UINT32 Uint32;\r |
dc5d621c MK |
1477 | ///\r |
1478 | /// All bit fields as a 64-bit value\r | |
1479 | ///\r | |
2f88bd3a | 1480 | UINT64 Uint64;\r |
0f16be6d | 1481 | } MSR_SANDY_BRIDGE_IA32_MC4_CTL_REGISTER;\r |
dc5d621c | 1482 | \r |
dc5d621c | 1483 | /**\r |
ba1a2d11 | 1484 | Thread. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r |
dc5d621c MK |
1485 | \r |
1486 | @param ECX MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
1487 | @param EAX Lower 32-bits of MSR value.\r | |
1488 | @param EDX Upper 32-bits of MSR value.\r | |
1489 | \r | |
1490 | <b>Example usage</b>\r | |
1491 | @code\r | |
1492 | UINT64 Msr;\r | |
1493 | \r | |
1494 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM);\r | |
1495 | @endcode\r | |
367f5c9c | 1496 | @note MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r |
dc5d621c MK |
1497 | **/\r |
1498 | #define MSR_SANDY_BRIDGE_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r | |
1499 | \r | |
dc5d621c MK |
1500 | /**\r |
1501 | Package. Unit Multipliers used in RAPL Interfaces (R/O) See Section 14.9.1,\r | |
1502 | "RAPL Interfaces.".\r | |
1503 | \r | |
1504 | @param ECX MSR_SANDY_BRIDGE_RAPL_POWER_UNIT (0x00000606)\r | |
1505 | @param EAX Lower 32-bits of MSR value.\r | |
1506 | @param EDX Upper 32-bits of MSR value.\r | |
1507 | \r | |
1508 | <b>Example usage</b>\r | |
1509 | @code\r | |
1510 | UINT64 Msr;\r | |
1511 | \r | |
1512 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_RAPL_POWER_UNIT);\r | |
1513 | @endcode\r | |
367f5c9c | 1514 | @note MSR_SANDY_BRIDGE_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
dc5d621c | 1515 | **/\r |
2f88bd3a | 1516 | #define MSR_SANDY_BRIDGE_RAPL_POWER_UNIT 0x00000606\r |
dc5d621c MK |
1517 | \r |
1518 | /**\r | |
1519 | Package. Package C3 Interrupt Response Limit (R/W) Note: C-state values are\r | |
1520 | processor specific C-state code names, unrelated to MWAIT extension C-state\r | |
1521 | parameters or ACPI CStates.\r | |
1522 | \r | |
1523 | @param ECX MSR_SANDY_BRIDGE_PKGC3_IRTL (0x0000060A)\r | |
1524 | @param EAX Lower 32-bits of MSR value.\r | |
1525 | Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r | |
1526 | @param EDX Upper 32-bits of MSR value.\r | |
1527 | Described by the type MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER.\r | |
1528 | \r | |
1529 | <b>Example usage</b>\r | |
1530 | @code\r | |
1531 | MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER Msr;\r | |
1532 | \r | |
1533 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL);\r | |
1534 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC3_IRTL, Msr.Uint64);\r | |
1535 | @endcode\r | |
367f5c9c | 1536 | @note MSR_SANDY_BRIDGE_PKGC3_IRTL is defined as MSR_PKGC3_IRTL in SDM.\r |
dc5d621c | 1537 | **/\r |
2f88bd3a | 1538 | #define MSR_SANDY_BRIDGE_PKGC3_IRTL 0x0000060A\r |
dc5d621c MK |
1539 | \r |
1540 | /**\r | |
1541 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC3_IRTL\r | |
1542 | **/\r | |
1543 | typedef union {\r | |
1544 | ///\r | |
1545 | /// Individual bit fields\r | |
1546 | ///\r | |
1547 | struct {\r | |
1548 | ///\r | |
1549 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
1550 | /// that should be used to decide if the package should be put into a\r | |
1551 | /// package C3 state.\r | |
1552 | ///\r | |
2f88bd3a | 1553 | UINT32 TimeLimit : 10;\r |
dc5d621c MK |
1554 | ///\r |
1555 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r | |
1556 | /// unit of the interrupt response time limit. The following time unit\r | |
1557 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r | |
1558 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r | |
1559 | ///\r | |
2f88bd3a MK |
1560 | UINT32 TimeUnit : 3;\r |
1561 | UINT32 Reserved1 : 2;\r | |
dc5d621c MK |
1562 | ///\r |
1563 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
1564 | /// valid and can be used by the processor for package C-sate management.\r | |
1565 | ///\r | |
2f88bd3a MK |
1566 | UINT32 Valid : 1;\r |
1567 | UINT32 Reserved2 : 16;\r | |
1568 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
1569 | } Bits;\r |
1570 | ///\r | |
1571 | /// All bit fields as a 32-bit value\r | |
1572 | ///\r | |
2f88bd3a | 1573 | UINT32 Uint32;\r |
dc5d621c MK |
1574 | ///\r |
1575 | /// All bit fields as a 64-bit value\r | |
1576 | ///\r | |
2f88bd3a | 1577 | UINT64 Uint64;\r |
dc5d621c MK |
1578 | } MSR_SANDY_BRIDGE_PKGC3_IRTL_REGISTER;\r |
1579 | \r | |
dc5d621c MK |
1580 | /**\r |
1581 | Package. Package C6 Interrupt Response Limit (R/W) This MSR defines the\r | |
1582 | budget allocated for the package to exit from C6 to a C0 state, where\r | |
1583 | interrupt request can be delivered to the core and serviced. Additional\r | |
1584 | core-exit latency amy be applicable depending on the actual C-state the core\r | |
1585 | is in. Note: C-state values are processor specific C-state code names,\r | |
1586 | unrelated to MWAIT extension C-state parameters or ACPI CStates.\r | |
1587 | \r | |
1588 | @param ECX MSR_SANDY_BRIDGE_PKGC6_IRTL (0x0000060B)\r | |
1589 | @param EAX Lower 32-bits of MSR value.\r | |
1590 | Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r | |
1591 | @param EDX Upper 32-bits of MSR value.\r | |
1592 | Described by the type MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER.\r | |
1593 | \r | |
1594 | <b>Example usage</b>\r | |
1595 | @code\r | |
1596 | MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER Msr;\r | |
1597 | \r | |
1598 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL);\r | |
1599 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC6_IRTL, Msr.Uint64);\r | |
1600 | @endcode\r | |
367f5c9c | 1601 | @note MSR_SANDY_BRIDGE_PKGC6_IRTL is defined as MSR_PKGC6_IRTL in SDM.\r |
dc5d621c | 1602 | **/\r |
2f88bd3a | 1603 | #define MSR_SANDY_BRIDGE_PKGC6_IRTL 0x0000060B\r |
dc5d621c MK |
1604 | \r |
1605 | /**\r | |
1606 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC6_IRTL\r | |
1607 | **/\r | |
1608 | typedef union {\r | |
1609 | ///\r | |
1610 | /// Individual bit fields\r | |
1611 | ///\r | |
1612 | struct {\r | |
1613 | ///\r | |
1614 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
1615 | /// that should be used to decide if the package should be put into a\r | |
1616 | /// package C6 state.\r | |
1617 | ///\r | |
2f88bd3a | 1618 | UINT32 TimeLimit : 10;\r |
dc5d621c MK |
1619 | ///\r |
1620 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r | |
1621 | /// unit of the interrupt response time limit. The following time unit\r | |
1622 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r | |
1623 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r | |
1624 | ///\r | |
2f88bd3a MK |
1625 | UINT32 TimeUnit : 3;\r |
1626 | UINT32 Reserved1 : 2;\r | |
dc5d621c MK |
1627 | ///\r |
1628 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
1629 | /// valid and can be used by the processor for package C-sate management.\r | |
1630 | ///\r | |
2f88bd3a MK |
1631 | UINT32 Valid : 1;\r |
1632 | UINT32 Reserved2 : 16;\r | |
1633 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
1634 | } Bits;\r |
1635 | ///\r | |
1636 | /// All bit fields as a 32-bit value\r | |
1637 | ///\r | |
2f88bd3a | 1638 | UINT32 Uint32;\r |
dc5d621c MK |
1639 | ///\r |
1640 | /// All bit fields as a 64-bit value\r | |
1641 | ///\r | |
2f88bd3a | 1642 | UINT64 Uint64;\r |
dc5d621c MK |
1643 | } MSR_SANDY_BRIDGE_PKGC6_IRTL_REGISTER;\r |
1644 | \r | |
dc5d621c MK |
1645 | /**\r |
1646 | Package. Note: C-state values are processor specific C-state code names,\r | |
1647 | unrelated to MWAIT extension C-state parameters or ACPI CStates. Package C2\r | |
1648 | Residency Counter. (R/O) Value since last reset that this package is in\r | |
1649 | processor-specific C2 states. Count at the same frequency as the TSC.\r | |
1650 | \r | |
1651 | @param ECX MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY (0x0000060D)\r | |
1652 | @param EAX Lower 32-bits of MSR value.\r | |
1653 | @param EDX Upper 32-bits of MSR value.\r | |
1654 | \r | |
1655 | <b>Example usage</b>\r | |
1656 | @code\r | |
1657 | UINT64 Msr;\r | |
1658 | \r | |
1659 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY);\r | |
1660 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY, Msr);\r | |
1661 | @endcode\r | |
367f5c9c | 1662 | @note MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
dc5d621c | 1663 | **/\r |
2f88bd3a | 1664 | #define MSR_SANDY_BRIDGE_PKG_C2_RESIDENCY 0x0000060D\r |
dc5d621c MK |
1665 | \r |
1666 | /**\r | |
1667 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
1668 | RAPL Domain.".\r | |
1669 | \r | |
1670 | @param ECX MSR_SANDY_BRIDGE_PKG_POWER_LIMIT (0x00000610)\r | |
1671 | @param EAX Lower 32-bits of MSR value.\r | |
1672 | @param EDX Upper 32-bits of MSR value.\r | |
1673 | \r | |
1674 | <b>Example usage</b>\r | |
1675 | @code\r | |
1676 | UINT64 Msr;\r | |
1677 | \r | |
1678 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT);\r | |
1679 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_LIMIT, Msr);\r | |
1680 | @endcode\r | |
367f5c9c | 1681 | @note MSR_SANDY_BRIDGE_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r |
dc5d621c | 1682 | **/\r |
2f88bd3a | 1683 | #define MSR_SANDY_BRIDGE_PKG_POWER_LIMIT 0x00000610\r |
dc5d621c MK |
1684 | \r |
1685 | /**\r | |
1686 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1687 | \r | |
1688 | @param ECX MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS (0x00000611)\r | |
1689 | @param EAX Lower 32-bits of MSR value.\r | |
1690 | @param EDX Upper 32-bits of MSR value.\r | |
1691 | \r | |
1692 | <b>Example usage</b>\r | |
1693 | @code\r | |
1694 | UINT64 Msr;\r | |
1695 | \r | |
1696 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS);\r | |
1697 | @endcode\r | |
367f5c9c | 1698 | @note MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r |
dc5d621c | 1699 | **/\r |
2f88bd3a | 1700 | #define MSR_SANDY_BRIDGE_PKG_ENERGY_STATUS 0x00000611\r |
dc5d621c MK |
1701 | \r |
1702 | /**\r | |
1703 | Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r | |
1704 | Domain.".\r | |
1705 | \r | |
1706 | @param ECX MSR_SANDY_BRIDGE_PKG_POWER_INFO (0x00000614)\r | |
1707 | @param EAX Lower 32-bits of MSR value.\r | |
1708 | @param EDX Upper 32-bits of MSR value.\r | |
1709 | \r | |
1710 | <b>Example usage</b>\r | |
1711 | @code\r | |
1712 | UINT64 Msr;\r | |
1713 | \r | |
1714 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO);\r | |
1715 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKG_POWER_INFO, Msr);\r | |
1716 | @endcode\r | |
367f5c9c | 1717 | @note MSR_SANDY_BRIDGE_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r |
dc5d621c | 1718 | **/\r |
2f88bd3a | 1719 | #define MSR_SANDY_BRIDGE_PKG_POWER_INFO 0x00000614\r |
dc5d621c MK |
1720 | \r |
1721 | /**\r | |
1722 | Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
1723 | RAPL Domains.".\r | |
1724 | \r | |
1725 | @param ECX MSR_SANDY_BRIDGE_PP0_POWER_LIMIT (0x00000638)\r | |
1726 | @param EAX Lower 32-bits of MSR value.\r | |
1727 | @param EDX Upper 32-bits of MSR value.\r | |
1728 | \r | |
1729 | <b>Example usage</b>\r | |
1730 | @code\r | |
1731 | UINT64 Msr;\r | |
1732 | \r | |
1733 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT);\r | |
1734 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POWER_LIMIT, Msr);\r | |
1735 | @endcode\r | |
367f5c9c | 1736 | @note MSR_SANDY_BRIDGE_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r |
dc5d621c | 1737 | **/\r |
2f88bd3a | 1738 | #define MSR_SANDY_BRIDGE_PP0_POWER_LIMIT 0x00000638\r |
dc5d621c MK |
1739 | \r |
1740 | /**\r | |
1741 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1742 | Domains.".\r | |
1743 | \r | |
1744 | @param ECX MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS (0x00000639)\r | |
1745 | @param EAX Lower 32-bits of MSR value.\r | |
1746 | @param EDX Upper 32-bits of MSR value.\r | |
1747 | \r | |
1748 | <b>Example usage</b>\r | |
1749 | @code\r | |
1750 | UINT64 Msr;\r | |
1751 | \r | |
1752 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS);\r | |
1753 | @endcode\r | |
367f5c9c | 1754 | @note MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r |
dc5d621c | 1755 | **/\r |
2f88bd3a | 1756 | #define MSR_SANDY_BRIDGE_PP0_ENERGY_STATUS 0x00000639\r |
dc5d621c MK |
1757 | \r |
1758 | /**\r | |
1759 | Thread. Last Branch Record n From IP (R/W) One of sixteen pairs of last\r | |
1760 | branch record registers on the last branch record stack. This part of the\r | |
1761 | stack contains pointers to the source instruction. See also: - Last Branch\r | |
0f16be6d HW |
1762 | Record Stack TOS at 1C9H - Section 17.7.1 and record format in Section\r |
1763 | 17.4.8.1.\r | |
dc5d621c MK |
1764 | \r |
1765 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_FROM_IP\r | |
1766 | @param EAX Lower 32-bits of MSR value.\r | |
1767 | @param EDX Upper 32-bits of MSR value.\r | |
1768 | \r | |
1769 | <b>Example usage</b>\r | |
1770 | @code\r | |
1771 | UINT64 Msr;\r | |
1772 | \r | |
1773 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP);\r | |
1774 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP, Msr);\r | |
1775 | @endcode\r | |
367f5c9c JF |
1776 | @note MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP is defined as MSR_LASTBRANCH_0_FROM_IP in SDM.\r |
1777 | MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP is defined as MSR_LASTBRANCH_1_FROM_IP in SDM.\r | |
1778 | MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP is defined as MSR_LASTBRANCH_2_FROM_IP in SDM.\r | |
1779 | MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP is defined as MSR_LASTBRANCH_3_FROM_IP in SDM.\r | |
1780 | MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP is defined as MSR_LASTBRANCH_4_FROM_IP in SDM.\r | |
1781 | MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP is defined as MSR_LASTBRANCH_5_FROM_IP in SDM.\r | |
1782 | MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP is defined as MSR_LASTBRANCH_6_FROM_IP in SDM.\r | |
1783 | MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP is defined as MSR_LASTBRANCH_7_FROM_IP in SDM.\r | |
1784 | MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP is defined as MSR_LASTBRANCH_8_FROM_IP in SDM.\r | |
1785 | MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP is defined as MSR_LASTBRANCH_9_FROM_IP in SDM.\r | |
1786 | MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP is defined as MSR_LASTBRANCH_10_FROM_IP in SDM.\r | |
1787 | MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP is defined as MSR_LASTBRANCH_11_FROM_IP in SDM.\r | |
1788 | MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP is defined as MSR_LASTBRANCH_12_FROM_IP in SDM.\r | |
1789 | MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP is defined as MSR_LASTBRANCH_13_FROM_IP in SDM.\r | |
1790 | MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP is defined as MSR_LASTBRANCH_14_FROM_IP in SDM.\r | |
1791 | MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP is defined as MSR_LASTBRANCH_15_FROM_IP in SDM.\r | |
dc5d621c MK |
1792 | @{\r |
1793 | **/\r | |
2f88bd3a MK |
1794 | #define MSR_SANDY_BRIDGE_LASTBRANCH_0_FROM_IP 0x00000680\r |
1795 | #define MSR_SANDY_BRIDGE_LASTBRANCH_1_FROM_IP 0x00000681\r | |
1796 | #define MSR_SANDY_BRIDGE_LASTBRANCH_2_FROM_IP 0x00000682\r | |
1797 | #define MSR_SANDY_BRIDGE_LASTBRANCH_3_FROM_IP 0x00000683\r | |
1798 | #define MSR_SANDY_BRIDGE_LASTBRANCH_4_FROM_IP 0x00000684\r | |
1799 | #define MSR_SANDY_BRIDGE_LASTBRANCH_5_FROM_IP 0x00000685\r | |
1800 | #define MSR_SANDY_BRIDGE_LASTBRANCH_6_FROM_IP 0x00000686\r | |
1801 | #define MSR_SANDY_BRIDGE_LASTBRANCH_7_FROM_IP 0x00000687\r | |
1802 | #define MSR_SANDY_BRIDGE_LASTBRANCH_8_FROM_IP 0x00000688\r | |
1803 | #define MSR_SANDY_BRIDGE_LASTBRANCH_9_FROM_IP 0x00000689\r | |
1804 | #define MSR_SANDY_BRIDGE_LASTBRANCH_10_FROM_IP 0x0000068A\r | |
1805 | #define MSR_SANDY_BRIDGE_LASTBRANCH_11_FROM_IP 0x0000068B\r | |
1806 | #define MSR_SANDY_BRIDGE_LASTBRANCH_12_FROM_IP 0x0000068C\r | |
1807 | #define MSR_SANDY_BRIDGE_LASTBRANCH_13_FROM_IP 0x0000068D\r | |
1808 | #define MSR_SANDY_BRIDGE_LASTBRANCH_14_FROM_IP 0x0000068E\r | |
1809 | #define MSR_SANDY_BRIDGE_LASTBRANCH_15_FROM_IP 0x0000068F\r | |
dc5d621c MK |
1810 | /// @}\r |
1811 | \r | |
dc5d621c MK |
1812 | /**\r |
1813 | Thread. Last Branch Record n To IP (R/W) One of sixteen pairs of last branch\r | |
1814 | record registers on the last branch record stack. This part of the stack\r | |
1815 | contains pointers to the destination instruction.\r | |
1816 | \r | |
1817 | @param ECX MSR_SANDY_BRIDGE_LASTBRANCH_n_TO_IP\r | |
1818 | @param EAX Lower 32-bits of MSR value.\r | |
1819 | @param EDX Upper 32-bits of MSR value.\r | |
1820 | \r | |
1821 | <b>Example usage</b>\r | |
1822 | @code\r | |
1823 | UINT64 Msr;\r | |
1824 | \r | |
1825 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP);\r | |
1826 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP, Msr);\r | |
1827 | @endcode\r | |
367f5c9c JF |
1828 | @note MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP is defined as MSR_LASTBRANCH_0_TO_IP in SDM.\r |
1829 | MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP is defined as MSR_LASTBRANCH_1_TO_IP in SDM.\r | |
1830 | MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP is defined as MSR_LASTBRANCH_2_TO_IP in SDM.\r | |
1831 | MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP is defined as MSR_LASTBRANCH_3_TO_IP in SDM.\r | |
1832 | MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP is defined as MSR_LASTBRANCH_4_TO_IP in SDM.\r | |
1833 | MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP is defined as MSR_LASTBRANCH_5_TO_IP in SDM.\r | |
1834 | MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP is defined as MSR_LASTBRANCH_6_TO_IP in SDM.\r | |
1835 | MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP is defined as MSR_LASTBRANCH_7_TO_IP in SDM.\r | |
1836 | MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP is defined as MSR_LASTBRANCH_8_TO_IP in SDM.\r | |
1837 | MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP is defined as MSR_LASTBRANCH_9_TO_IP in SDM.\r | |
1838 | MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP is defined as MSR_LASTBRANCH_10_TO_IP in SDM.\r | |
1839 | MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP is defined as MSR_LASTBRANCH_11_TO_IP in SDM.\r | |
1840 | MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP is defined as MSR_LASTBRANCH_12_TO_IP in SDM.\r | |
1841 | MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP is defined as MSR_LASTBRANCH_13_TO_IP in SDM.\r | |
1842 | MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP is defined as MSR_LASTBRANCH_14_TO_IP in SDM.\r | |
1843 | MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP is defined as MSR_LASTBRANCH_15_TO_IP in SDM.\r | |
dc5d621c MK |
1844 | @{\r |
1845 | **/\r | |
2f88bd3a MK |
1846 | #define MSR_SANDY_BRIDGE_LASTBRANCH_0_TO_IP 0x000006C0\r |
1847 | #define MSR_SANDY_BRIDGE_LASTBRANCH_1_TO_IP 0x000006C1\r | |
1848 | #define MSR_SANDY_BRIDGE_LASTBRANCH_2_TO_IP 0x000006C2\r | |
1849 | #define MSR_SANDY_BRIDGE_LASTBRANCH_3_TO_IP 0x000006C3\r | |
1850 | #define MSR_SANDY_BRIDGE_LASTBRANCH_4_TO_IP 0x000006C4\r | |
1851 | #define MSR_SANDY_BRIDGE_LASTBRANCH_5_TO_IP 0x000006C5\r | |
1852 | #define MSR_SANDY_BRIDGE_LASTBRANCH_6_TO_IP 0x000006C6\r | |
1853 | #define MSR_SANDY_BRIDGE_LASTBRANCH_7_TO_IP 0x000006C7\r | |
1854 | #define MSR_SANDY_BRIDGE_LASTBRANCH_8_TO_IP 0x000006C8\r | |
1855 | #define MSR_SANDY_BRIDGE_LASTBRANCH_9_TO_IP 0x000006C9\r | |
1856 | #define MSR_SANDY_BRIDGE_LASTBRANCH_10_TO_IP 0x000006CA\r | |
1857 | #define MSR_SANDY_BRIDGE_LASTBRANCH_11_TO_IP 0x000006CB\r | |
1858 | #define MSR_SANDY_BRIDGE_LASTBRANCH_12_TO_IP 0x000006CC\r | |
1859 | #define MSR_SANDY_BRIDGE_LASTBRANCH_13_TO_IP 0x000006CD\r | |
1860 | #define MSR_SANDY_BRIDGE_LASTBRANCH_14_TO_IP 0x000006CE\r | |
1861 | #define MSR_SANDY_BRIDGE_LASTBRANCH_15_TO_IP 0x000006CF\r | |
dc5d621c MK |
1862 | /// @}\r |
1863 | \r | |
dc5d621c MK |
1864 | /**\r |
1865 | Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r | |
1866 | RW if MSR_PLATFORM_INFO.[28] = 1.\r | |
1867 | \r | |
1868 | @param ECX MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT (0x000001AD)\r | |
1869 | @param EAX Lower 32-bits of MSR value.\r | |
1870 | Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r | |
1871 | @param EDX Upper 32-bits of MSR value.\r | |
1872 | Described by the type MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER.\r | |
1873 | \r | |
1874 | <b>Example usage</b>\r | |
1875 | @code\r | |
1876 | MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
1877 | \r | |
1878 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT);\r | |
1879 | @endcode\r | |
367f5c9c | 1880 | @note MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
dc5d621c | 1881 | **/\r |
2f88bd3a | 1882 | #define MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT 0x000001AD\r |
dc5d621c MK |
1883 | \r |
1884 | /**\r | |
1885 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT\r | |
1886 | **/\r | |
1887 | typedef union {\r | |
1888 | ///\r | |
1889 | /// Individual bit fields\r | |
1890 | ///\r | |
1891 | struct {\r | |
1892 | ///\r | |
1893 | /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r | |
1894 | /// limit of 1 core active.\r | |
1895 | ///\r | |
2f88bd3a | 1896 | UINT32 Maximum1C : 8;\r |
dc5d621c MK |
1897 | ///\r |
1898 | /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r | |
1899 | /// limit of 2 core active.\r | |
1900 | ///\r | |
2f88bd3a | 1901 | UINT32 Maximum2C : 8;\r |
dc5d621c MK |
1902 | ///\r |
1903 | /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r | |
1904 | /// limit of 3 core active.\r | |
1905 | ///\r | |
2f88bd3a | 1906 | UINT32 Maximum3C : 8;\r |
dc5d621c MK |
1907 | ///\r |
1908 | /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r | |
1909 | /// limit of 4 core active.\r | |
1910 | ///\r | |
2f88bd3a | 1911 | UINT32 Maximum4C : 8;\r |
dc5d621c MK |
1912 | ///\r |
1913 | /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r | |
1914 | /// limit of 5 core active.\r | |
1915 | ///\r | |
2f88bd3a | 1916 | UINT32 Maximum5C : 8;\r |
dc5d621c MK |
1917 | ///\r |
1918 | /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r | |
1919 | /// limit of 6 core active.\r | |
1920 | ///\r | |
2f88bd3a | 1921 | UINT32 Maximum6C : 8;\r |
dc5d621c MK |
1922 | ///\r |
1923 | /// [Bits 55:48] Package. Maximum Ratio Limit for 7C Maximum turbo ratio\r | |
1924 | /// limit of 7 core active.\r | |
1925 | ///\r | |
2f88bd3a | 1926 | UINT32 Maximum7C : 8;\r |
dc5d621c MK |
1927 | ///\r |
1928 | /// [Bits 63:56] Package. Maximum Ratio Limit for 8C Maximum turbo ratio\r | |
1929 | /// limit of 8 core active.\r | |
1930 | ///\r | |
2f88bd3a | 1931 | UINT32 Maximum8C : 8;\r |
dc5d621c MK |
1932 | } Bits;\r |
1933 | ///\r | |
1934 | /// All bit fields as a 64-bit value\r | |
1935 | ///\r | |
2f88bd3a | 1936 | UINT64 Uint64;\r |
dc5d621c MK |
1937 | } MSR_SANDY_BRIDGE_TURBO_RATIO_LIMIT_REGISTER;\r |
1938 | \r | |
dc5d621c MK |
1939 | /**\r |
1940 | Package. Uncore PMU global control.\r | |
1941 | \r | |
1942 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL (0x00000391)\r | |
1943 | @param EAX Lower 32-bits of MSR value.\r | |
1944 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
1945 | @param EDX Upper 32-bits of MSR value.\r | |
1946 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER.\r | |
1947 | \r | |
1948 | <b>Example usage</b>\r | |
1949 | @code\r | |
1950 | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER Msr;\r | |
1951 | \r | |
1952 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL);\r | |
1953 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL, Msr.Uint64);\r | |
1954 | @endcode\r | |
367f5c9c | 1955 | @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL is defined as MSR_UNC_PERF_GLOBAL_CTRL in SDM.\r |
dc5d621c | 1956 | **/\r |
2f88bd3a | 1957 | #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL 0x00000391\r |
dc5d621c MK |
1958 | \r |
1959 | /**\r | |
1960 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL\r | |
1961 | **/\r | |
1962 | typedef union {\r | |
1963 | ///\r | |
1964 | /// Individual bit fields\r | |
1965 | ///\r | |
1966 | struct {\r | |
1967 | ///\r | |
0f16be6d | 1968 | /// [Bit 0] Slice 0 select.\r |
dc5d621c | 1969 | ///\r |
2f88bd3a | 1970 | UINT32 PMI_Sel_Slice0 : 1;\r |
dc5d621c | 1971 | ///\r |
0f16be6d | 1972 | /// [Bit 1] Slice 1 select.\r |
dc5d621c | 1973 | ///\r |
2f88bd3a | 1974 | UINT32 PMI_Sel_Slice1 : 1;\r |
dc5d621c | 1975 | ///\r |
0f16be6d | 1976 | /// [Bit 2] Slice 2 select.\r |
dc5d621c | 1977 | ///\r |
2f88bd3a | 1978 | UINT32 PMI_Sel_Slice2 : 1;\r |
dc5d621c | 1979 | ///\r |
0f16be6d | 1980 | /// [Bit 3] Slice 3 select.\r |
dc5d621c | 1981 | ///\r |
2f88bd3a | 1982 | UINT32 PMI_Sel_Slice3 : 1;\r |
0f16be6d HW |
1983 | ///\r |
1984 | /// [Bit 4] Slice 4 select.\r | |
1985 | ///\r | |
2f88bd3a MK |
1986 | UINT32 PMI_Sel_Slice4 : 1;\r |
1987 | UINT32 Reserved1 : 14;\r | |
1988 | UINT32 Reserved2 : 10;\r | |
dc5d621c MK |
1989 | ///\r |
1990 | /// [Bit 29] Enable all uncore counters.\r | |
1991 | ///\r | |
2f88bd3a | 1992 | UINT32 EN : 1;\r |
dc5d621c MK |
1993 | ///\r |
1994 | /// [Bit 30] Enable wake on PMI.\r | |
1995 | ///\r | |
2f88bd3a | 1996 | UINT32 WakePMI : 1;\r |
dc5d621c MK |
1997 | ///\r |
1998 | /// [Bit 31] Enable Freezing counter when overflow.\r | |
1999 | ///\r | |
2f88bd3a MK |
2000 | UINT32 FREEZE : 1;\r |
2001 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
2002 | } Bits;\r |
2003 | ///\r | |
2004 | /// All bit fields as a 32-bit value\r | |
2005 | ///\r | |
2f88bd3a | 2006 | UINT32 Uint32;\r |
dc5d621c MK |
2007 | ///\r |
2008 | /// All bit fields as a 64-bit value\r | |
2009 | ///\r | |
2f88bd3a | 2010 | UINT64 Uint64;\r |
dc5d621c MK |
2011 | } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_CTRL_REGISTER;\r |
2012 | \r | |
dc5d621c MK |
2013 | /**\r |
2014 | Package. Uncore PMU main status.\r | |
2015 | \r | |
2016 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS (0x00000392)\r | |
2017 | @param EAX Lower 32-bits of MSR value.\r | |
2018 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
2019 | @param EDX Upper 32-bits of MSR value.\r | |
2020 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER.\r | |
2021 | \r | |
2022 | <b>Example usage</b>\r | |
2023 | @code\r | |
2024 | MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER Msr;\r | |
2025 | \r | |
2026 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS);\r | |
2027 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS, Msr.Uint64);\r | |
2028 | @endcode\r | |
367f5c9c | 2029 | @note MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS is defined as MSR_UNC_PERF_GLOBAL_STATUS in SDM.\r |
dc5d621c MK |
2030 | **/\r |
2031 | #define MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS 0x00000392\r | |
2032 | \r | |
2033 | /**\r | |
2034 | MSR information returned for MSR index\r | |
2035 | #MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS\r | |
2036 | **/\r | |
2037 | typedef union {\r | |
2038 | ///\r | |
2039 | /// Individual bit fields\r | |
2040 | ///\r | |
2041 | struct {\r | |
2042 | ///\r | |
2043 | /// [Bit 0] Fixed counter overflowed.\r | |
2044 | ///\r | |
2f88bd3a | 2045 | UINT32 Fixed : 1;\r |
dc5d621c MK |
2046 | ///\r |
2047 | /// [Bit 1] An ARB counter overflowed.\r | |
2048 | ///\r | |
2f88bd3a MK |
2049 | UINT32 ARB : 1;\r |
2050 | UINT32 Reserved1 : 1;\r | |
dc5d621c MK |
2051 | ///\r |
2052 | /// [Bit 3] A CBox counter overflowed (on any slice).\r | |
2053 | ///\r | |
2f88bd3a MK |
2054 | UINT32 CBox : 1;\r |
2055 | UINT32 Reserved2 : 28;\r | |
2056 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
2057 | } Bits;\r |
2058 | ///\r | |
2059 | /// All bit fields as a 32-bit value\r | |
2060 | ///\r | |
2f88bd3a | 2061 | UINT32 Uint32;\r |
dc5d621c MK |
2062 | ///\r |
2063 | /// All bit fields as a 64-bit value\r | |
2064 | ///\r | |
2f88bd3a | 2065 | UINT64 Uint64;\r |
dc5d621c MK |
2066 | } MSR_SANDY_BRIDGE_UNC_PERF_GLOBAL_STATUS_REGISTER;\r |
2067 | \r | |
dc5d621c MK |
2068 | /**\r |
2069 | Package. Uncore fixed counter control (R/W).\r | |
2070 | \r | |
2071 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL (0x00000394)\r | |
2072 | @param EAX Lower 32-bits of MSR value.\r | |
2073 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
2074 | @param EDX Upper 32-bits of MSR value.\r | |
2075 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER.\r | |
2076 | \r | |
2077 | <b>Example usage</b>\r | |
2078 | @code\r | |
2079 | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER Msr;\r | |
2080 | \r | |
2081 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL);\r | |
2082 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL, Msr.Uint64);\r | |
2083 | @endcode\r | |
367f5c9c | 2084 | @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL is defined as MSR_UNC_PERF_FIXED_CTRL in SDM.\r |
dc5d621c | 2085 | **/\r |
2f88bd3a | 2086 | #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL 0x00000394\r |
dc5d621c MK |
2087 | \r |
2088 | /**\r | |
2089 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL\r | |
2090 | **/\r | |
2091 | typedef union {\r | |
2092 | ///\r | |
2093 | /// Individual bit fields\r | |
2094 | ///\r | |
2095 | struct {\r | |
2f88bd3a | 2096 | UINT32 Reserved1 : 20;\r |
dc5d621c MK |
2097 | ///\r |
2098 | /// [Bit 20] Enable overflow propagation.\r | |
2099 | ///\r | |
2f88bd3a MK |
2100 | UINT32 EnableOverflow : 1;\r |
2101 | UINT32 Reserved2 : 1;\r | |
dc5d621c MK |
2102 | ///\r |
2103 | /// [Bit 22] Enable counting.\r | |
2104 | ///\r | |
2f88bd3a MK |
2105 | UINT32 EnableCounting : 1;\r |
2106 | UINT32 Reserved3 : 9;\r | |
2107 | UINT32 Reserved4 : 32;\r | |
dc5d621c MK |
2108 | } Bits;\r |
2109 | ///\r | |
2110 | /// All bit fields as a 32-bit value\r | |
2111 | ///\r | |
2f88bd3a | 2112 | UINT32 Uint32;\r |
dc5d621c MK |
2113 | ///\r |
2114 | /// All bit fields as a 64-bit value\r | |
2115 | ///\r | |
2f88bd3a | 2116 | UINT64 Uint64;\r |
dc5d621c MK |
2117 | } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTRL_REGISTER;\r |
2118 | \r | |
dc5d621c MK |
2119 | /**\r |
2120 | Package. Uncore fixed counter.\r | |
2121 | \r | |
2122 | @param ECX MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR (0x00000395)\r | |
2123 | @param EAX Lower 32-bits of MSR value.\r | |
2124 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r | |
2125 | @param EDX Upper 32-bits of MSR value.\r | |
2126 | Described by the type MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER.\r | |
2127 | \r | |
2128 | <b>Example usage</b>\r | |
2129 | @code\r | |
2130 | MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER Msr;\r | |
2131 | \r | |
2132 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR);\r | |
2133 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR, Msr.Uint64);\r | |
2134 | @endcode\r | |
367f5c9c | 2135 | @note MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR is defined as MSR_UNC_PERF_FIXED_CTR in SDM.\r |
dc5d621c | 2136 | **/\r |
2f88bd3a | 2137 | #define MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR 0x00000395\r |
dc5d621c MK |
2138 | \r |
2139 | /**\r | |
2140 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR\r | |
2141 | **/\r | |
2142 | typedef union {\r | |
2143 | ///\r | |
2144 | /// Individual bit fields\r | |
2145 | ///\r | |
2146 | struct {\r | |
2147 | ///\r | |
2148 | /// [Bits 31:0] Current count.\r | |
2149 | ///\r | |
2f88bd3a | 2150 | UINT32 CurrentCount : 32;\r |
dc5d621c MK |
2151 | ///\r |
2152 | /// [Bits 47:32] Current count.\r | |
2153 | ///\r | |
2f88bd3a MK |
2154 | UINT32 CurrentCountHi : 16;\r |
2155 | UINT32 Reserved : 16;\r | |
dc5d621c MK |
2156 | } Bits;\r |
2157 | ///\r | |
2158 | /// All bit fields as a 64-bit value\r | |
2159 | ///\r | |
2f88bd3a | 2160 | UINT64 Uint64;\r |
dc5d621c MK |
2161 | } MSR_SANDY_BRIDGE_UNC_PERF_FIXED_CTR_REGISTER;\r |
2162 | \r | |
dc5d621c MK |
2163 | /**\r |
2164 | Package. Uncore C-Box configuration information (R/O).\r | |
2165 | \r | |
2166 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_CONFIG (0x00000396)\r | |
2167 | @param EAX Lower 32-bits of MSR value.\r | |
2168 | Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r | |
2169 | @param EDX Upper 32-bits of MSR value.\r | |
2170 | Described by the type MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER.\r | |
2171 | \r | |
2172 | <b>Example usage</b>\r | |
2173 | @code\r | |
2174 | MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER Msr;\r | |
2175 | \r | |
2176 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_CONFIG);\r | |
2177 | @endcode\r | |
367f5c9c | 2178 | @note MSR_SANDY_BRIDGE_UNC_CBO_CONFIG is defined as MSR_UNC_CBO_CONFIG in SDM.\r |
dc5d621c | 2179 | **/\r |
2f88bd3a | 2180 | #define MSR_SANDY_BRIDGE_UNC_CBO_CONFIG 0x00000396\r |
dc5d621c MK |
2181 | \r |
2182 | /**\r | |
2183 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_UNC_CBO_CONFIG\r | |
2184 | **/\r | |
2185 | typedef union {\r | |
2186 | ///\r | |
2187 | /// Individual bit fields\r | |
2188 | ///\r | |
2189 | struct {\r | |
2190 | ///\r | |
0f16be6d HW |
2191 | /// [Bits 3:0] Report the number of C-Box units with performance counters,\r |
2192 | /// including processor cores and processor graphics".\r | |
dc5d621c | 2193 | ///\r |
2f88bd3a MK |
2194 | UINT32 CBox : 4;\r |
2195 | UINT32 Reserved1 : 28;\r | |
2196 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
2197 | } Bits;\r |
2198 | ///\r | |
2199 | /// All bit fields as a 32-bit value\r | |
2200 | ///\r | |
2f88bd3a | 2201 | UINT32 Uint32;\r |
dc5d621c MK |
2202 | ///\r |
2203 | /// All bit fields as a 64-bit value\r | |
2204 | ///\r | |
2f88bd3a | 2205 | UINT64 Uint64;\r |
dc5d621c MK |
2206 | } MSR_SANDY_BRIDGE_UNC_CBO_CONFIG_REGISTER;\r |
2207 | \r | |
dc5d621c MK |
2208 | /**\r |
2209 | Package. Uncore Arb unit, performance counter 0.\r | |
2210 | \r | |
2211 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 (0x000003B0)\r | |
2212 | @param EAX Lower 32-bits of MSR value.\r | |
2213 | @param EDX Upper 32-bits of MSR value.\r | |
2214 | \r | |
2215 | <b>Example usage</b>\r | |
2216 | @code\r | |
2217 | UINT64 Msr;\r | |
2218 | \r | |
2219 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0);\r | |
2220 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0, Msr);\r | |
2221 | @endcode\r | |
367f5c9c | 2222 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 is defined as MSR_UNC_ARB_PERFCTR0 in SDM.\r |
dc5d621c | 2223 | **/\r |
2f88bd3a | 2224 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR0 0x000003B0\r |
dc5d621c MK |
2225 | \r |
2226 | /**\r | |
2227 | Package. Uncore Arb unit, performance counter 1.\r | |
2228 | \r | |
2229 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 (0x000003B1)\r | |
2230 | @param EAX Lower 32-bits of MSR value.\r | |
2231 | @param EDX Upper 32-bits of MSR value.\r | |
2232 | \r | |
2233 | <b>Example usage</b>\r | |
2234 | @code\r | |
2235 | UINT64 Msr;\r | |
2236 | \r | |
2237 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1);\r | |
2238 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1, Msr);\r | |
2239 | @endcode\r | |
367f5c9c | 2240 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 is defined as MSR_UNC_ARB_PERFCTR1 in SDM.\r |
dc5d621c | 2241 | **/\r |
2f88bd3a | 2242 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFCTR1 0x000003B1\r |
dc5d621c MK |
2243 | \r |
2244 | /**\r | |
2245 | Package. Uncore Arb unit, counter 0 event select MSR.\r | |
2246 | \r | |
2247 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 (0x000003B2)\r | |
2248 | @param EAX Lower 32-bits of MSR value.\r | |
2249 | @param EDX Upper 32-bits of MSR value.\r | |
2250 | \r | |
2251 | <b>Example usage</b>\r | |
2252 | @code\r | |
2253 | UINT64 Msr;\r | |
2254 | \r | |
2255 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0);\r | |
2256 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0, Msr);\r | |
2257 | @endcode\r | |
367f5c9c | 2258 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 is defined as MSR_UNC_ARB_PERFEVTSEL0 in SDM.\r |
dc5d621c | 2259 | **/\r |
2f88bd3a | 2260 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL0 0x000003B2\r |
dc5d621c MK |
2261 | \r |
2262 | /**\r | |
2263 | Package. Uncore Arb unit, counter 1 event select MSR.\r | |
2264 | \r | |
2265 | @param ECX MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 (0x000003B3)\r | |
2266 | @param EAX Lower 32-bits of MSR value.\r | |
2267 | @param EDX Upper 32-bits of MSR value.\r | |
2268 | \r | |
2269 | <b>Example usage</b>\r | |
2270 | @code\r | |
2271 | UINT64 Msr;\r | |
2272 | \r | |
2273 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1);\r | |
2274 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1, Msr);\r | |
2275 | @endcode\r | |
367f5c9c | 2276 | @note MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 is defined as MSR_UNC_ARB_PERFEVTSEL1 in SDM.\r |
dc5d621c | 2277 | **/\r |
2f88bd3a | 2278 | #define MSR_SANDY_BRIDGE_UNC_ARB_PERFEVTSEL1 0x000003B3\r |
dc5d621c MK |
2279 | \r |
2280 | /**\r | |
2281 | Package. Package C7 Interrupt Response Limit (R/W) This MSR defines the\r | |
2282 | budget allocated for the package to exit from C7 to a C0 state, where\r | |
2283 | interrupt request can be delivered to the core and serviced. Additional\r | |
2284 | core-exit latency amy be applicable depending on the actual C-state the core\r | |
2285 | is in. Note: C-state values are processor specific C-state code names,\r | |
2286 | unrelated to MWAIT extension C-state parameters or ACPI CStates.\r | |
2287 | \r | |
2288 | @param ECX MSR_SANDY_BRIDGE_PKGC7_IRTL (0x0000060C)\r | |
2289 | @param EAX Lower 32-bits of MSR value.\r | |
2290 | Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r | |
2291 | @param EDX Upper 32-bits of MSR value.\r | |
2292 | Described by the type MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER.\r | |
2293 | \r | |
2294 | <b>Example usage</b>\r | |
2295 | @code\r | |
2296 | MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER Msr;\r | |
2297 | \r | |
2298 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL);\r | |
2299 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PKGC7_IRTL, Msr.Uint64);\r | |
2300 | @endcode\r | |
367f5c9c | 2301 | @note MSR_SANDY_BRIDGE_PKGC7_IRTL is defined as MSR_PKGC7_IRTL in SDM.\r |
dc5d621c | 2302 | **/\r |
2f88bd3a | 2303 | #define MSR_SANDY_BRIDGE_PKGC7_IRTL 0x0000060C\r |
dc5d621c MK |
2304 | \r |
2305 | /**\r | |
2306 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PKGC7_IRTL\r | |
2307 | **/\r | |
2308 | typedef union {\r | |
2309 | ///\r | |
2310 | /// Individual bit fields\r | |
2311 | ///\r | |
2312 | struct {\r | |
2313 | ///\r | |
2314 | /// [Bits 9:0] Interrupt response time limit (R/W) Specifies the limit\r | |
2315 | /// that should be used to decide if the package should be put into a\r | |
2316 | /// package C7 state.\r | |
2317 | ///\r | |
2f88bd3a | 2318 | UINT32 TimeLimit : 10;\r |
dc5d621c MK |
2319 | ///\r |
2320 | /// [Bits 12:10] Time Unit (R/W) Specifies the encoding value of time\r | |
2321 | /// unit of the interrupt response time limit. The following time unit\r | |
2322 | /// encodings are supported: 000b: 1 ns 001b: 32 ns 010b: 1024 ns 011b:\r | |
2323 | /// 32768 ns 100b: 1048576 ns 101b: 33554432 ns.\r | |
2324 | ///\r | |
2f88bd3a MK |
2325 | UINT32 TimeUnit : 3;\r |
2326 | UINT32 Reserved1 : 2;\r | |
dc5d621c MK |
2327 | ///\r |
2328 | /// [Bit 15] Valid (R/W) Indicates whether the values in bits 12:0 are\r | |
2329 | /// valid and can be used by the processor for package C-sate management.\r | |
2330 | ///\r | |
2f88bd3a MK |
2331 | UINT32 Valid : 1;\r |
2332 | UINT32 Reserved2 : 16;\r | |
2333 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
2334 | } Bits;\r |
2335 | ///\r | |
2336 | /// All bit fields as a 32-bit value\r | |
2337 | ///\r | |
2f88bd3a | 2338 | UINT32 Uint32;\r |
dc5d621c MK |
2339 | ///\r |
2340 | /// All bit fields as a 64-bit value\r | |
2341 | ///\r | |
2f88bd3a | 2342 | UINT64 Uint64;\r |
dc5d621c MK |
2343 | } MSR_SANDY_BRIDGE_PKGC7_IRTL_REGISTER;\r |
2344 | \r | |
dc5d621c MK |
2345 | /**\r |
2346 | Package. PP0 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r | |
2347 | Domains.".\r | |
2348 | \r | |
2349 | @param ECX MSR_SANDY_BRIDGE_PP0_POLICY (0x0000063A)\r | |
2350 | @param EAX Lower 32-bits of MSR value.\r | |
2351 | @param EDX Upper 32-bits of MSR value.\r | |
2352 | \r | |
2353 | <b>Example usage</b>\r | |
2354 | @code\r | |
2355 | UINT64 Msr;\r | |
2356 | \r | |
2357 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY);\r | |
2358 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP0_POLICY, Msr);\r | |
2359 | @endcode\r | |
367f5c9c | 2360 | @note MSR_SANDY_BRIDGE_PP0_POLICY is defined as MSR_PP0_POLICY in SDM.\r |
dc5d621c | 2361 | **/\r |
2f88bd3a | 2362 | #define MSR_SANDY_BRIDGE_PP0_POLICY 0x0000063A\r |
dc5d621c MK |
2363 | \r |
2364 | /**\r | |
2365 | Package. PP1 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
2366 | RAPL Domains.".\r | |
2367 | \r | |
2368 | @param ECX MSR_SANDY_BRIDGE_PP1_POWER_LIMIT (0x00000640)\r | |
2369 | @param EAX Lower 32-bits of MSR value.\r | |
2370 | @param EDX Upper 32-bits of MSR value.\r | |
2371 | \r | |
2372 | <b>Example usage</b>\r | |
2373 | @code\r | |
2374 | UINT64 Msr;\r | |
2375 | \r | |
2376 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT);\r | |
2377 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POWER_LIMIT, Msr);\r | |
2378 | @endcode\r | |
367f5c9c | 2379 | @note MSR_SANDY_BRIDGE_PP1_POWER_LIMIT is defined as MSR_PP1_POWER_LIMIT in SDM.\r |
dc5d621c | 2380 | **/\r |
2f88bd3a | 2381 | #define MSR_SANDY_BRIDGE_PP1_POWER_LIMIT 0x00000640\r |
dc5d621c MK |
2382 | \r |
2383 | /**\r | |
2384 | Package. PP1 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
2385 | Domains.".\r | |
2386 | \r | |
2387 | @param ECX MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS (0x00000641)\r | |
2388 | @param EAX Lower 32-bits of MSR value.\r | |
2389 | @param EDX Upper 32-bits of MSR value.\r | |
2390 | \r | |
2391 | <b>Example usage</b>\r | |
2392 | @code\r | |
2393 | UINT64 Msr;\r | |
2394 | \r | |
2395 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS);\r | |
2396 | @endcode\r | |
367f5c9c | 2397 | @note MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS is defined as MSR_PP1_ENERGY_STATUS in SDM.\r |
dc5d621c | 2398 | **/\r |
2f88bd3a | 2399 | #define MSR_SANDY_BRIDGE_PP1_ENERGY_STATUS 0x00000641\r |
dc5d621c MK |
2400 | \r |
2401 | /**\r | |
2402 | Package. PP1 Balance Policy (R/W) See Section 14.9.4, "PP0/PP1 RAPL\r | |
2403 | Domains.".\r | |
2404 | \r | |
2405 | @param ECX MSR_SANDY_BRIDGE_PP1_POLICY (0x00000642)\r | |
2406 | @param EAX Lower 32-bits of MSR value.\r | |
2407 | @param EDX Upper 32-bits of MSR value.\r | |
2408 | \r | |
2409 | <b>Example usage</b>\r | |
2410 | @code\r | |
2411 | UINT64 Msr;\r | |
2412 | \r | |
2413 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY);\r | |
2414 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PP1_POLICY, Msr);\r | |
2415 | @endcode\r | |
367f5c9c | 2416 | @note MSR_SANDY_BRIDGE_PP1_POLICY is defined as MSR_PP1_POLICY in SDM.\r |
dc5d621c | 2417 | **/\r |
2f88bd3a | 2418 | #define MSR_SANDY_BRIDGE_PP1_POLICY 0x00000642\r |
dc5d621c MK |
2419 | \r |
2420 | /**\r | |
0f16be6d | 2421 | Package. Uncore C-Box 0, counter n event select MSR.\r |
dc5d621c | 2422 | \r |
0f16be6d | 2423 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSELn\r |
dc5d621c MK |
2424 | @param EAX Lower 32-bits of MSR value.\r |
2425 | @param EDX Upper 32-bits of MSR value.\r | |
2426 | \r | |
2427 | <b>Example usage</b>\r | |
2428 | @code\r | |
2429 | UINT64 Msr;\r | |
2430 | \r | |
2431 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0);\r | |
2432 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0, Msr);\r | |
2433 | @endcode\r | |
367f5c9c | 2434 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 is defined as MSR_UNC_CBO_0_PERFEVTSEL0 in SDM.\r |
0f16be6d HW |
2435 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 is defined as MSR_UNC_CBO_0_PERFEVTSEL1 in SDM.\r |
2436 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 is defined as MSR_UNC_CBO_0_PERFEVTSEL2 in SDM.\r | |
2437 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 is defined as MSR_UNC_CBO_0_PERFEVTSEL3 in SDM.\r | |
2438 | @{\r | |
dc5d621c | 2439 | **/\r |
2f88bd3a MK |
2440 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL0 0x00000700\r |
2441 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL1 0x00000701\r | |
2442 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL2 0x00000702\r | |
2443 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFEVTSEL3 0x00000703\r | |
0f16be6d | 2444 | /// @}\r |
dc5d621c | 2445 | \r |
dc5d621c | 2446 | /**\r |
0f16be6d | 2447 | Package. Uncore C-Box n, unit status for counter 0-3.\r |
dc5d621c | 2448 | \r |
0f16be6d | 2449 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_n_UNIT_STATUS\r |
dc5d621c MK |
2450 | @param EAX Lower 32-bits of MSR value.\r |
2451 | @param EDX Upper 32-bits of MSR value.\r | |
2452 | \r | |
2453 | <b>Example usage</b>\r | |
2454 | @code\r | |
2455 | UINT64 Msr;\r | |
2456 | \r | |
0f16be6d HW |
2457 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS);\r |
2458 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS, Msr);\r | |
dc5d621c | 2459 | @endcode\r |
0f16be6d HW |
2460 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS is defined as MSR_UNC_CBO_0_UNIT_STATUS in SDM.\r |
2461 | MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS is defined as MSR_UNC_CBO_1_UNIT_STATUS in SDM.\r | |
2462 | MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS is defined as MSR_UNC_CBO_2_UNIT_STATUS in SDM.\r | |
2463 | MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS is defined as MSR_UNC_CBO_3_UNIT_STATUS in SDM.\r | |
2464 | MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS is defined as MSR_UNC_CBO_4_UNIT_STATUS in SDM.\r | |
2465 | @{\r | |
dc5d621c | 2466 | **/\r |
2f88bd3a MK |
2467 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_UNIT_STATUS 0x00000705\r |
2468 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_UNIT_STATUS 0x00000715\r | |
2469 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_UNIT_STATUS 0x00000725\r | |
2470 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_UNIT_STATUS 0x00000735\r | |
2471 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_UNIT_STATUS 0x00000745\r | |
0f16be6d | 2472 | /// @}\r |
dc5d621c | 2473 | \r |
dc5d621c | 2474 | /**\r |
0f16be6d | 2475 | Package. Uncore C-Box 0, performance counter n.\r |
dc5d621c | 2476 | \r |
0f16be6d | 2477 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTRn\r |
dc5d621c MK |
2478 | @param EAX Lower 32-bits of MSR value.\r |
2479 | @param EDX Upper 32-bits of MSR value.\r | |
2480 | \r | |
2481 | <b>Example usage</b>\r | |
2482 | @code\r | |
2483 | UINT64 Msr;\r | |
2484 | \r | |
2485 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0);\r | |
2486 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0, Msr);\r | |
2487 | @endcode\r | |
367f5c9c | 2488 | @note MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 is defined as MSR_UNC_CBO_0_PERFCTR0 in SDM.\r |
0f16be6d HW |
2489 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 is defined as MSR_UNC_CBO_0_PERFCTR1 in SDM.\r |
2490 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 is defined as MSR_UNC_CBO_0_PERFCTR2 in SDM.\r | |
2491 | MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 is defined as MSR_UNC_CBO_0_PERFCTR3 in SDM.\r | |
2492 | @{\r | |
dc5d621c | 2493 | **/\r |
2f88bd3a MK |
2494 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR0 0x00000706\r |
2495 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR1 0x00000707\r | |
2496 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR2 0x00000708\r | |
2497 | #define MSR_SANDY_BRIDGE_UNC_CBO_0_PERFCTR3 0x00000709\r | |
0f16be6d | 2498 | /// @}\r |
dc5d621c | 2499 | \r |
dc5d621c | 2500 | /**\r |
0f16be6d | 2501 | Package. Uncore C-Box 1, counter n event select MSR.\r |
dc5d621c | 2502 | \r |
0f16be6d | 2503 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSELn\r |
dc5d621c MK |
2504 | @param EAX Lower 32-bits of MSR value.\r |
2505 | @param EDX Upper 32-bits of MSR value.\r | |
2506 | \r | |
2507 | <b>Example usage</b>\r | |
2508 | @code\r | |
2509 | UINT64 Msr;\r | |
2510 | \r | |
2511 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0);\r | |
2512 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0, Msr);\r | |
2513 | @endcode\r | |
367f5c9c | 2514 | @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 is defined as MSR_UNC_CBO_1_PERFEVTSEL0 in SDM.\r |
0f16be6d HW |
2515 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 is defined as MSR_UNC_CBO_1_PERFEVTSEL1 in SDM.\r |
2516 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 is defined as MSR_UNC_CBO_1_PERFEVTSEL2 in SDM.\r | |
2517 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 is defined as MSR_UNC_CBO_1_PERFEVTSEL3 in SDM.\r | |
2518 | @{\r | |
dc5d621c | 2519 | **/\r |
2f88bd3a MK |
2520 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL0 0x00000710\r |
2521 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL1 0x00000711\r | |
2522 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL2 0x00000712\r | |
2523 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFEVTSEL3 0x00000713\r | |
0f16be6d | 2524 | /// @}\r |
dc5d621c | 2525 | \r |
dc5d621c | 2526 | /**\r |
0f16be6d | 2527 | Package. Uncore C-Box 1, performance counter n.\r |
dc5d621c | 2528 | \r |
0f16be6d | 2529 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTRn\r |
dc5d621c MK |
2530 | @param EAX Lower 32-bits of MSR value.\r |
2531 | @param EDX Upper 32-bits of MSR value.\r | |
2532 | \r | |
2533 | <b>Example usage</b>\r | |
2534 | @code\r | |
2535 | UINT64 Msr;\r | |
2536 | \r | |
2537 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0);\r | |
2538 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0, Msr);\r | |
2539 | @endcode\r | |
367f5c9c | 2540 | @note MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 is defined as MSR_UNC_CBO_1_PERFCTR0 in SDM.\r |
0f16be6d HW |
2541 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 is defined as MSR_UNC_CBO_1_PERFCTR1 in SDM.\r |
2542 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 is defined as MSR_UNC_CBO_1_PERFCTR2 in SDM.\r | |
2543 | MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 is defined as MSR_UNC_CBO_1_PERFCTR3 in SDM.\r | |
2544 | @{\r | |
dc5d621c | 2545 | **/\r |
2f88bd3a MK |
2546 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR0 0x00000716\r |
2547 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR1 0x00000717\r | |
2548 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR2 0x00000718\r | |
2549 | #define MSR_SANDY_BRIDGE_UNC_CBO_1_PERFCTR3 0x00000719\r | |
0f16be6d | 2550 | /// @}\r |
dc5d621c | 2551 | \r |
dc5d621c | 2552 | /**\r |
0f16be6d | 2553 | Package. Uncore C-Box 2, counter n event select MSR.\r |
dc5d621c | 2554 | \r |
0f16be6d | 2555 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSELn\r |
dc5d621c MK |
2556 | @param EAX Lower 32-bits of MSR value.\r |
2557 | @param EDX Upper 32-bits of MSR value.\r | |
2558 | \r | |
2559 | <b>Example usage</b>\r | |
2560 | @code\r | |
2561 | UINT64 Msr;\r | |
2562 | \r | |
2563 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0);\r | |
2564 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0, Msr);\r | |
2565 | @endcode\r | |
367f5c9c | 2566 | @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 is defined as MSR_UNC_CBO_2_PERFEVTSEL0 in SDM.\r |
0f16be6d HW |
2567 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 is defined as MSR_UNC_CBO_2_PERFEVTSEL1 in SDM.\r |
2568 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 is defined as MSR_UNC_CBO_2_PERFEVTSEL2 in SDM.\r | |
2569 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 is defined as MSR_UNC_CBO_2_PERFEVTSEL3 in SDM.\r | |
2570 | @{\r | |
dc5d621c | 2571 | **/\r |
2f88bd3a MK |
2572 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL0 0x00000720\r |
2573 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL1 0x00000721\r | |
2574 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL2 0x00000722\r | |
2575 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFEVTSEL3 0x00000723\r | |
0f16be6d | 2576 | /// @}\r |
dc5d621c | 2577 | \r |
dc5d621c | 2578 | /**\r |
0f16be6d | 2579 | Package. Uncore C-Box 2, performance counter n.\r |
dc5d621c | 2580 | \r |
0f16be6d | 2581 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTRn\r |
dc5d621c MK |
2582 | @param EAX Lower 32-bits of MSR value.\r |
2583 | @param EDX Upper 32-bits of MSR value.\r | |
2584 | \r | |
2585 | <b>Example usage</b>\r | |
2586 | @code\r | |
2587 | UINT64 Msr;\r | |
2588 | \r | |
2589 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0);\r | |
2590 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0, Msr);\r | |
2591 | @endcode\r | |
367f5c9c | 2592 | @note MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 is defined as MSR_UNC_CBO_2_PERFCTR0 in SDM.\r |
0f16be6d HW |
2593 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 is defined as MSR_UNC_CBO_2_PERFCTR1 in SDM.\r |
2594 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 is defined as MSR_UNC_CBO_2_PERFCTR2 in SDM.\r | |
2595 | MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 is defined as MSR_UNC_CBO_2_PERFCTR3 in SDM.\r | |
2596 | @{\r | |
dc5d621c | 2597 | **/\r |
2f88bd3a MK |
2598 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR0 0x00000726\r |
2599 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR1 0x00000727\r | |
2600 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR2 0x00000728\r | |
2601 | #define MSR_SANDY_BRIDGE_UNC_CBO_2_PERFCTR3 0x00000729\r | |
0f16be6d | 2602 | /// @}\r |
dc5d621c | 2603 | \r |
dc5d621c | 2604 | /**\r |
0f16be6d | 2605 | Package. Uncore C-Box 3, counter n event select MSR.\r |
dc5d621c | 2606 | \r |
0f16be6d | 2607 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSELn\r |
dc5d621c MK |
2608 | @param EAX Lower 32-bits of MSR value.\r |
2609 | @param EDX Upper 32-bits of MSR value.\r | |
2610 | \r | |
2611 | <b>Example usage</b>\r | |
2612 | @code\r | |
2613 | UINT64 Msr;\r | |
2614 | \r | |
2615 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0);\r | |
2616 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0, Msr);\r | |
2617 | @endcode\r | |
367f5c9c | 2618 | @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 is defined as MSR_UNC_CBO_3_PERFEVTSEL0 in SDM.\r |
0f16be6d HW |
2619 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 is defined as MSR_UNC_CBO_3_PERFEVTSEL1 in SDM.\r |
2620 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 is defined as MSR_UNC_CBO_3_PERFEVTSEL2 in SDM.\r | |
2621 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 is defined as MSR_UNC_CBO_3_PERFEVTSEL3 in SDM.\r | |
2622 | @{\r | |
dc5d621c | 2623 | **/\r |
2f88bd3a MK |
2624 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL0 0x00000730\r |
2625 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL1 0x00000731\r | |
2626 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL2 0x00000732\r | |
2627 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFEVTSEL3 0x00000733\r | |
0f16be6d | 2628 | /// @}\r |
dc5d621c | 2629 | \r |
dc5d621c | 2630 | /**\r |
0f16be6d | 2631 | Package. Uncore C-Box 3, performance counter n.\r |
dc5d621c | 2632 | \r |
0f16be6d | 2633 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTRn\r |
dc5d621c MK |
2634 | @param EAX Lower 32-bits of MSR value.\r |
2635 | @param EDX Upper 32-bits of MSR value.\r | |
2636 | \r | |
2637 | <b>Example usage</b>\r | |
2638 | @code\r | |
2639 | UINT64 Msr;\r | |
2640 | \r | |
0f16be6d HW |
2641 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0);\r |
2642 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0, Msr);\r | |
dc5d621c | 2643 | @endcode\r |
0f16be6d HW |
2644 | @note MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 is defined as MSR_UNC_CBO_3_PERFCTR0 in SDM.\r |
2645 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 is defined as MSR_UNC_CBO_3_PERFCTR1 in SDM.\r | |
2646 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 is defined as MSR_UNC_CBO_3_PERFCTR2 in SDM.\r | |
2647 | MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 is defined as MSR_UNC_CBO_3_PERFCTR3 in SDM.\r | |
2648 | @{\r | |
dc5d621c | 2649 | **/\r |
2f88bd3a MK |
2650 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR0 0x00000736\r |
2651 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR1 0x00000737\r | |
2652 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR2 0x00000738\r | |
2653 | #define MSR_SANDY_BRIDGE_UNC_CBO_3_PERFCTR3 0x00000739\r | |
0f16be6d | 2654 | /// @}\r |
dc5d621c | 2655 | \r |
dc5d621c | 2656 | /**\r |
0f16be6d | 2657 | Package. Uncore C-Box 4, counter n event select MSR.\r |
dc5d621c | 2658 | \r |
0f16be6d | 2659 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSELn\r |
dc5d621c MK |
2660 | @param EAX Lower 32-bits of MSR value.\r |
2661 | @param EDX Upper 32-bits of MSR value.\r | |
2662 | \r | |
2663 | <b>Example usage</b>\r | |
2664 | @code\r | |
2665 | UINT64 Msr;\r | |
2666 | \r | |
0f16be6d HW |
2667 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0);\r |
2668 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0, Msr);\r | |
dc5d621c | 2669 | @endcode\r |
0f16be6d HW |
2670 | @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 is defined as MSR_UNC_CBO_4_PERFEVTSEL0 in SDM.\r |
2671 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 is defined as MSR_UNC_CBO_4_PERFEVTSEL1 in SDM.\r | |
2672 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 is defined as MSR_UNC_CBO_4_PERFEVTSEL2 in SDM.\r | |
2673 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 is defined as MSR_UNC_CBO_4_PERFEVTSEL3 in SDM.\r | |
2674 | @{\r | |
dc5d621c | 2675 | **/\r |
2f88bd3a MK |
2676 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL0 0x00000740\r |
2677 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL1 0x00000741\r | |
2678 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL2 0x00000742\r | |
2679 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFEVTSEL3 0x00000743\r | |
0f16be6d | 2680 | /// @}\r |
dc5d621c | 2681 | \r |
dc5d621c | 2682 | /**\r |
0f16be6d | 2683 | Package. Uncore C-Box 4, performance counter n.\r |
dc5d621c | 2684 | \r |
0f16be6d | 2685 | @param ECX MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTRn\r |
dc5d621c MK |
2686 | @param EAX Lower 32-bits of MSR value.\r |
2687 | @param EDX Upper 32-bits of MSR value.\r | |
2688 | \r | |
2689 | <b>Example usage</b>\r | |
2690 | @code\r | |
2691 | UINT64 Msr;\r | |
2692 | \r | |
0f16be6d HW |
2693 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0);\r |
2694 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0, Msr);\r | |
dc5d621c | 2695 | @endcode\r |
0f16be6d HW |
2696 | @note MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 is defined as MSR_UNC_CBO_4_PERFCTR0 in SDM.\r |
2697 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 is defined as MSR_UNC_CBO_4_PERFCTR1 in SDM.\r | |
2698 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 is defined as MSR_UNC_CBO_4_PERFCTR2 in SDM.\r | |
2699 | MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 is defined as MSR_UNC_CBO_4_PERFCTR3 in SDM.\r | |
2700 | @{\r | |
dc5d621c | 2701 | **/\r |
2f88bd3a MK |
2702 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR0 0x00000746\r |
2703 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR1 0x00000747\r | |
2704 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR2 0x00000748\r | |
2705 | #define MSR_SANDY_BRIDGE_UNC_CBO_4_PERFCTR3 0x00000749\r | |
0f16be6d | 2706 | /// @}\r |
dc5d621c | 2707 | \r |
dc5d621c MK |
2708 | /**\r |
2709 | Package. MC Bank Error Configuration (R/W).\r | |
2710 | \r | |
2711 | @param ECX MSR_SANDY_BRIDGE_ERROR_CONTROL (0x0000017F)\r | |
2712 | @param EAX Lower 32-bits of MSR value.\r | |
2713 | Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
2714 | @param EDX Upper 32-bits of MSR value.\r | |
2715 | Described by the type MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER.\r | |
2716 | \r | |
2717 | <b>Example usage</b>\r | |
2718 | @code\r | |
2719 | MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER Msr;\r | |
2720 | \r | |
2721 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL);\r | |
2722 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_ERROR_CONTROL, Msr.Uint64);\r | |
2723 | @endcode\r | |
367f5c9c | 2724 | @note MSR_SANDY_BRIDGE_ERROR_CONTROL is defined as MSR_ERROR_CONTROL in SDM.\r |
dc5d621c | 2725 | **/\r |
2f88bd3a | 2726 | #define MSR_SANDY_BRIDGE_ERROR_CONTROL 0x0000017F\r |
dc5d621c MK |
2727 | \r |
2728 | /**\r | |
2729 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_ERROR_CONTROL\r | |
2730 | **/\r | |
2731 | typedef union {\r | |
2732 | ///\r | |
2733 | /// Individual bit fields\r | |
2734 | ///\r | |
2735 | struct {\r | |
2f88bd3a | 2736 | UINT32 Reserved1 : 1;\r |
dc5d621c MK |
2737 | ///\r |
2738 | /// [Bit 1] MemError Log Enable (R/W) When set, enables IMC status bank\r | |
2739 | /// to log additional info in bits 36:32.\r | |
2740 | ///\r | |
2f88bd3a MK |
2741 | UINT32 MemErrorLogEnable : 1;\r |
2742 | UINT32 Reserved2 : 30;\r | |
2743 | UINT32 Reserved3 : 32;\r | |
dc5d621c MK |
2744 | } Bits;\r |
2745 | ///\r | |
2746 | /// All bit fields as a 32-bit value\r | |
2747 | ///\r | |
2f88bd3a | 2748 | UINT32 Uint32;\r |
dc5d621c MK |
2749 | ///\r |
2750 | /// All bit fields as a 64-bit value\r | |
2751 | ///\r | |
2f88bd3a | 2752 | UINT64 Uint64;\r |
dc5d621c MK |
2753 | } MSR_SANDY_BRIDGE_ERROR_CONTROL_REGISTER;\r |
2754 | \r | |
dc5d621c MK |
2755 | /**\r |
2756 | Package.\r | |
2757 | \r | |
2758 | @param ECX MSR_SANDY_BRIDGE_PEBS_NUM_ALT (0x0000039C)\r | |
2759 | @param EAX Lower 32-bits of MSR value.\r | |
2760 | Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r | |
2761 | @param EDX Upper 32-bits of MSR value.\r | |
2762 | Described by the type MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER.\r | |
2763 | \r | |
2764 | <b>Example usage</b>\r | |
2765 | @code\r | |
2766 | MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER Msr;\r | |
2767 | \r | |
2768 | Msr.Uint64 = AsmReadMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT);\r | |
2769 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PEBS_NUM_ALT, Msr.Uint64);\r | |
2770 | @endcode\r | |
367f5c9c | 2771 | @note MSR_SANDY_BRIDGE_PEBS_NUM_ALT is defined as MSR_PEBS_NUM_ALT in SDM.\r |
dc5d621c | 2772 | **/\r |
2f88bd3a | 2773 | #define MSR_SANDY_BRIDGE_PEBS_NUM_ALT 0x0000039C\r |
dc5d621c MK |
2774 | \r |
2775 | /**\r | |
2776 | MSR information returned for MSR index #MSR_SANDY_BRIDGE_PEBS_NUM_ALT\r | |
2777 | **/\r | |
2778 | typedef union {\r | |
2779 | ///\r | |
2780 | /// Individual bit fields\r | |
2781 | ///\r | |
2782 | struct {\r | |
2783 | ///\r | |
2784 | /// [Bit 0] ENABLE_PEBS_NUM_ALT (RW) Write 1 to enable alternate PEBS\r | |
2785 | /// counting logic for specific events requiring additional configuration,\r | |
ba1a2d11 | 2786 | /// see Table 19-17.\r |
dc5d621c | 2787 | ///\r |
2f88bd3a MK |
2788 | UINT32 ENABLE_PEBS_NUM_ALT : 1;\r |
2789 | UINT32 Reserved1 : 31;\r | |
2790 | UINT32 Reserved2 : 32;\r | |
dc5d621c MK |
2791 | } Bits;\r |
2792 | ///\r | |
2793 | /// All bit fields as a 32-bit value\r | |
2794 | ///\r | |
2f88bd3a | 2795 | UINT32 Uint32;\r |
dc5d621c MK |
2796 | ///\r |
2797 | /// All bit fields as a 64-bit value\r | |
2798 | ///\r | |
2f88bd3a | 2799 | UINT64 Uint64;\r |
dc5d621c MK |
2800 | } MSR_SANDY_BRIDGE_PEBS_NUM_ALT_REGISTER;\r |
2801 | \r | |
dc5d621c MK |
2802 | /**\r |
2803 | Package. Package RAPL Perf Status (R/O).\r | |
2804 | \r | |
2805 | @param ECX MSR_SANDY_BRIDGE_PKG_PERF_STATUS (0x00000613)\r | |
2806 | @param EAX Lower 32-bits of MSR value.\r | |
2807 | @param EDX Upper 32-bits of MSR value.\r | |
2808 | \r | |
2809 | <b>Example usage</b>\r | |
2810 | @code\r | |
2811 | UINT64 Msr;\r | |
2812 | \r | |
2813 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PKG_PERF_STATUS);\r | |
2814 | @endcode\r | |
367f5c9c | 2815 | @note MSR_SANDY_BRIDGE_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
dc5d621c | 2816 | **/\r |
2f88bd3a | 2817 | #define MSR_SANDY_BRIDGE_PKG_PERF_STATUS 0x00000613\r |
dc5d621c MK |
2818 | \r |
2819 | /**\r | |
2820 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
2821 | Domain.".\r | |
2822 | \r | |
2823 | @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT (0x00000618)\r | |
2824 | @param EAX Lower 32-bits of MSR value.\r | |
2825 | @param EDX Upper 32-bits of MSR value.\r | |
2826 | \r | |
2827 | <b>Example usage</b>\r | |
2828 | @code\r | |
2829 | UINT64 Msr;\r | |
2830 | \r | |
2831 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT);\r | |
2832 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT, Msr);\r | |
2833 | @endcode\r | |
367f5c9c | 2834 | @note MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
dc5d621c | 2835 | **/\r |
2f88bd3a | 2836 | #define MSR_SANDY_BRIDGE_DRAM_POWER_LIMIT 0x00000618\r |
dc5d621c MK |
2837 | \r |
2838 | /**\r | |
2839 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
2840 | \r | |
2841 | @param ECX MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS (0x00000619)\r | |
2842 | @param EAX Lower 32-bits of MSR value.\r | |
2843 | @param EDX Upper 32-bits of MSR value.\r | |
2844 | \r | |
2845 | <b>Example usage</b>\r | |
2846 | @code\r | |
2847 | UINT64 Msr;\r | |
2848 | \r | |
2849 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS);\r | |
2850 | @endcode\r | |
367f5c9c | 2851 | @note MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
dc5d621c | 2852 | **/\r |
2f88bd3a | 2853 | #define MSR_SANDY_BRIDGE_DRAM_ENERGY_STATUS 0x00000619\r |
dc5d621c MK |
2854 | \r |
2855 | /**\r | |
2856 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
2857 | RAPL Domain.".\r | |
2858 | \r | |
2859 | @param ECX MSR_SANDY_BRIDGE_DRAM_PERF_STATUS (0x0000061B)\r | |
2860 | @param EAX Lower 32-bits of MSR value.\r | |
2861 | @param EDX Upper 32-bits of MSR value.\r | |
2862 | \r | |
2863 | <b>Example usage</b>\r | |
2864 | @code\r | |
2865 | UINT64 Msr;\r | |
2866 | \r | |
2867 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_PERF_STATUS);\r | |
2868 | @endcode\r | |
367f5c9c | 2869 | @note MSR_SANDY_BRIDGE_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
dc5d621c | 2870 | **/\r |
2f88bd3a | 2871 | #define MSR_SANDY_BRIDGE_DRAM_PERF_STATUS 0x0000061B\r |
dc5d621c MK |
2872 | \r |
2873 | /**\r | |
2874 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
2875 | \r | |
2876 | @param ECX MSR_SANDY_BRIDGE_DRAM_POWER_INFO (0x0000061C)\r | |
2877 | @param EAX Lower 32-bits of MSR value.\r | |
2878 | @param EDX Upper 32-bits of MSR value.\r | |
2879 | \r | |
2880 | <b>Example usage</b>\r | |
2881 | @code\r | |
2882 | UINT64 Msr;\r | |
2883 | \r | |
2884 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO);\r | |
2885 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_DRAM_POWER_INFO, Msr);\r | |
2886 | @endcode\r | |
367f5c9c | 2887 | @note MSR_SANDY_BRIDGE_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
dc5d621c | 2888 | **/\r |
2f88bd3a | 2889 | #define MSR_SANDY_BRIDGE_DRAM_POWER_INFO 0x0000061C\r |
dc5d621c MK |
2890 | \r |
2891 | /**\r | |
2892 | Package. Uncore U-box UCLK fixed counter control.\r | |
2893 | \r | |
2894 | @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL (0x00000C08)\r | |
2895 | @param EAX Lower 32-bits of MSR value.\r | |
2896 | @param EDX Upper 32-bits of MSR value.\r | |
2897 | \r | |
2898 | <b>Example usage</b>\r | |
2899 | @code\r | |
2900 | UINT64 Msr;\r | |
2901 | \r | |
2902 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL);\r | |
2903 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL, Msr);\r | |
2904 | @endcode\r | |
367f5c9c | 2905 | @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL is defined as MSR_U_PMON_UCLK_FIXED_CTL in SDM.\r |
dc5d621c | 2906 | **/\r |
2f88bd3a | 2907 | #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTL 0x00000C08\r |
dc5d621c MK |
2908 | \r |
2909 | /**\r | |
2910 | Package. Uncore U-box UCLK fixed counter.\r | |
2911 | \r | |
2912 | @param ECX MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR (0x00000C09)\r | |
2913 | @param EAX Lower 32-bits of MSR value.\r | |
2914 | @param EDX Upper 32-bits of MSR value.\r | |
2915 | \r | |
2916 | <b>Example usage</b>\r | |
2917 | @code\r | |
2918 | UINT64 Msr;\r | |
2919 | \r | |
2920 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR);\r | |
2921 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR, Msr);\r | |
2922 | @endcode\r | |
367f5c9c | 2923 | @note MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR is defined as MSR_U_PMON_UCLK_FIXED_CTR in SDM.\r |
dc5d621c | 2924 | **/\r |
2f88bd3a | 2925 | #define MSR_SANDY_BRIDGE_U_PMON_UCLK_FIXED_CTR 0x00000C09\r |
dc5d621c MK |
2926 | \r |
2927 | /**\r | |
2928 | Package. Uncore U-box perfmon event select for U-box counter 0.\r | |
2929 | \r | |
2930 | @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 (0x00000C10)\r | |
2931 | @param EAX Lower 32-bits of MSR value.\r | |
2932 | @param EDX Upper 32-bits of MSR value.\r | |
2933 | \r | |
2934 | <b>Example usage</b>\r | |
2935 | @code\r | |
2936 | UINT64 Msr;\r | |
2937 | \r | |
2938 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0);\r | |
2939 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0, Msr);\r | |
2940 | @endcode\r | |
367f5c9c | 2941 | @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 is defined as MSR_U_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 2942 | **/\r |
2f88bd3a | 2943 | #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL0 0x00000C10\r |
dc5d621c MK |
2944 | \r |
2945 | /**\r | |
2946 | Package. Uncore U-box perfmon event select for U-box counter 1.\r | |
2947 | \r | |
2948 | @param ECX MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 (0x00000C11)\r | |
2949 | @param EAX Lower 32-bits of MSR value.\r | |
2950 | @param EDX Upper 32-bits of MSR value.\r | |
2951 | \r | |
2952 | <b>Example usage</b>\r | |
2953 | @code\r | |
2954 | UINT64 Msr;\r | |
2955 | \r | |
2956 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1);\r | |
2957 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1, Msr);\r | |
2958 | @endcode\r | |
367f5c9c | 2959 | @note MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 is defined as MSR_U_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 2960 | **/\r |
2f88bd3a | 2961 | #define MSR_SANDY_BRIDGE_U_PMON_EVNTSEL1 0x00000C11\r |
dc5d621c MK |
2962 | \r |
2963 | /**\r | |
2964 | Package. Uncore U-box perfmon counter 0.\r | |
2965 | \r | |
2966 | @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR0 (0x00000C16)\r | |
2967 | @param EAX Lower 32-bits of MSR value.\r | |
2968 | @param EDX Upper 32-bits of MSR value.\r | |
2969 | \r | |
2970 | <b>Example usage</b>\r | |
2971 | @code\r | |
2972 | UINT64 Msr;\r | |
2973 | \r | |
2974 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0);\r | |
2975 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR0, Msr);\r | |
2976 | @endcode\r | |
367f5c9c | 2977 | @note MSR_SANDY_BRIDGE_U_PMON_CTR0 is defined as MSR_U_PMON_CTR0 in SDM.\r |
dc5d621c | 2978 | **/\r |
2f88bd3a | 2979 | #define MSR_SANDY_BRIDGE_U_PMON_CTR0 0x00000C16\r |
dc5d621c MK |
2980 | \r |
2981 | /**\r | |
2982 | Package. Uncore U-box perfmon counter 1.\r | |
2983 | \r | |
2984 | @param ECX MSR_SANDY_BRIDGE_U_PMON_CTR1 (0x00000C17)\r | |
2985 | @param EAX Lower 32-bits of MSR value.\r | |
2986 | @param EDX Upper 32-bits of MSR value.\r | |
2987 | \r | |
2988 | <b>Example usage</b>\r | |
2989 | @code\r | |
2990 | UINT64 Msr;\r | |
2991 | \r | |
2992 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1);\r | |
2993 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_U_PMON_CTR1, Msr);\r | |
2994 | @endcode\r | |
367f5c9c | 2995 | @note MSR_SANDY_BRIDGE_U_PMON_CTR1 is defined as MSR_U_PMON_CTR1 in SDM.\r |
dc5d621c | 2996 | **/\r |
2f88bd3a | 2997 | #define MSR_SANDY_BRIDGE_U_PMON_CTR1 0x00000C17\r |
dc5d621c MK |
2998 | \r |
2999 | /**\r | |
3000 | Package. Uncore PCU perfmon for PCU-box-wide control.\r | |
3001 | \r | |
3002 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL (0x00000C24)\r | |
3003 | @param EAX Lower 32-bits of MSR value.\r | |
3004 | @param EDX Upper 32-bits of MSR value.\r | |
3005 | \r | |
3006 | <b>Example usage</b>\r | |
3007 | @code\r | |
3008 | UINT64 Msr;\r | |
3009 | \r | |
3010 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL);\r | |
3011 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL, Msr);\r | |
3012 | @endcode\r | |
367f5c9c | 3013 | @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL is defined as MSR_PCU_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3014 | **/\r |
2f88bd3a | 3015 | #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_CTL 0x00000C24\r |
dc5d621c MK |
3016 | \r |
3017 | /**\r | |
3018 | Package. Uncore PCU perfmon event select for PCU counter 0.\r | |
3019 | \r | |
3020 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 (0x00000C30)\r | |
3021 | @param EAX Lower 32-bits of MSR value.\r | |
3022 | @param EDX Upper 32-bits of MSR value.\r | |
3023 | \r | |
3024 | <b>Example usage</b>\r | |
3025 | @code\r | |
3026 | UINT64 Msr;\r | |
3027 | \r | |
3028 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0);\r | |
3029 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0, Msr);\r | |
3030 | @endcode\r | |
367f5c9c | 3031 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 is defined as MSR_PCU_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3032 | **/\r |
2f88bd3a | 3033 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL0 0x00000C30\r |
dc5d621c MK |
3034 | \r |
3035 | /**\r | |
3036 | Package. Uncore PCU perfmon event select for PCU counter 1.\r | |
3037 | \r | |
3038 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 (0x00000C31)\r | |
3039 | @param EAX Lower 32-bits of MSR value.\r | |
3040 | @param EDX Upper 32-bits of MSR value.\r | |
3041 | \r | |
3042 | <b>Example usage</b>\r | |
3043 | @code\r | |
3044 | UINT64 Msr;\r | |
3045 | \r | |
3046 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1);\r | |
3047 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1, Msr);\r | |
3048 | @endcode\r | |
367f5c9c | 3049 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 is defined as MSR_PCU_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3050 | **/\r |
2f88bd3a | 3051 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL1 0x00000C31\r |
dc5d621c MK |
3052 | \r |
3053 | /**\r | |
3054 | Package. Uncore PCU perfmon event select for PCU counter 2.\r | |
3055 | \r | |
3056 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 (0x00000C32)\r | |
3057 | @param EAX Lower 32-bits of MSR value.\r | |
3058 | @param EDX Upper 32-bits of MSR value.\r | |
3059 | \r | |
3060 | <b>Example usage</b>\r | |
3061 | @code\r | |
3062 | UINT64 Msr;\r | |
3063 | \r | |
3064 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2);\r | |
3065 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2, Msr);\r | |
3066 | @endcode\r | |
367f5c9c | 3067 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 is defined as MSR_PCU_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3068 | **/\r |
2f88bd3a | 3069 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL2 0x00000C32\r |
dc5d621c MK |
3070 | \r |
3071 | /**\r | |
3072 | Package. Uncore PCU perfmon event select for PCU counter 3.\r | |
3073 | \r | |
3074 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 (0x00000C33)\r | |
3075 | @param EAX Lower 32-bits of MSR value.\r | |
3076 | @param EDX Upper 32-bits of MSR value.\r | |
3077 | \r | |
3078 | <b>Example usage</b>\r | |
3079 | @code\r | |
3080 | UINT64 Msr;\r | |
3081 | \r | |
3082 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3);\r | |
3083 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3, Msr);\r | |
3084 | @endcode\r | |
367f5c9c | 3085 | @note MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 is defined as MSR_PCU_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3086 | **/\r |
2f88bd3a | 3087 | #define MSR_SANDY_BRIDGE_PCU_PMON_EVNTSEL3 0x00000C33\r |
dc5d621c MK |
3088 | \r |
3089 | /**\r | |
3090 | Package. Uncore PCU perfmon box-wide filter.\r | |
3091 | \r | |
3092 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER (0x00000C34)\r | |
3093 | @param EAX Lower 32-bits of MSR value.\r | |
3094 | @param EDX Upper 32-bits of MSR value.\r | |
3095 | \r | |
3096 | <b>Example usage</b>\r | |
3097 | @code\r | |
3098 | UINT64 Msr;\r | |
3099 | \r | |
3100 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER);\r | |
3101 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER, Msr);\r | |
3102 | @endcode\r | |
367f5c9c | 3103 | @note MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER is defined as MSR_PCU_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 3104 | **/\r |
2f88bd3a | 3105 | #define MSR_SANDY_BRIDGE_PCU_PMON_BOX_FILTER 0x00000C34\r |
dc5d621c MK |
3106 | \r |
3107 | /**\r | |
3108 | Package. Uncore PCU perfmon counter 0.\r | |
3109 | \r | |
3110 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR0 (0x00000C36)\r | |
3111 | @param EAX Lower 32-bits of MSR value.\r | |
3112 | @param EDX Upper 32-bits of MSR value.\r | |
3113 | \r | |
3114 | <b>Example usage</b>\r | |
3115 | @code\r | |
3116 | UINT64 Msr;\r | |
3117 | \r | |
3118 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0);\r | |
3119 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR0, Msr);\r | |
3120 | @endcode\r | |
367f5c9c | 3121 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR0 is defined as MSR_PCU_PMON_CTR0 in SDM.\r |
dc5d621c | 3122 | **/\r |
2f88bd3a | 3123 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR0 0x00000C36\r |
dc5d621c MK |
3124 | \r |
3125 | /**\r | |
3126 | Package. Uncore PCU perfmon counter 1.\r | |
3127 | \r | |
3128 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR1 (0x00000C37)\r | |
3129 | @param EAX Lower 32-bits of MSR value.\r | |
3130 | @param EDX Upper 32-bits of MSR value.\r | |
3131 | \r | |
3132 | <b>Example usage</b>\r | |
3133 | @code\r | |
3134 | UINT64 Msr;\r | |
3135 | \r | |
3136 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1);\r | |
3137 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR1, Msr);\r | |
3138 | @endcode\r | |
367f5c9c | 3139 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR1 is defined as MSR_PCU_PMON_CTR1 in SDM.\r |
dc5d621c | 3140 | **/\r |
2f88bd3a | 3141 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR1 0x00000C37\r |
dc5d621c MK |
3142 | \r |
3143 | /**\r | |
3144 | Package. Uncore PCU perfmon counter 2.\r | |
3145 | \r | |
3146 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR2 (0x00000C38)\r | |
3147 | @param EAX Lower 32-bits of MSR value.\r | |
3148 | @param EDX Upper 32-bits of MSR value.\r | |
3149 | \r | |
3150 | <b>Example usage</b>\r | |
3151 | @code\r | |
3152 | UINT64 Msr;\r | |
3153 | \r | |
3154 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2);\r | |
3155 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR2, Msr);\r | |
3156 | @endcode\r | |
367f5c9c | 3157 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR2 is defined as MSR_PCU_PMON_CTR2 in SDM.\r |
dc5d621c | 3158 | **/\r |
2f88bd3a | 3159 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR2 0x00000C38\r |
dc5d621c MK |
3160 | \r |
3161 | /**\r | |
3162 | Package. Uncore PCU perfmon counter 3.\r | |
3163 | \r | |
3164 | @param ECX MSR_SANDY_BRIDGE_PCU_PMON_CTR3 (0x00000C39)\r | |
3165 | @param EAX Lower 32-bits of MSR value.\r | |
3166 | @param EDX Upper 32-bits of MSR value.\r | |
3167 | \r | |
3168 | <b>Example usage</b>\r | |
3169 | @code\r | |
3170 | UINT64 Msr;\r | |
3171 | \r | |
3172 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3);\r | |
3173 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_PCU_PMON_CTR3, Msr);\r | |
3174 | @endcode\r | |
367f5c9c | 3175 | @note MSR_SANDY_BRIDGE_PCU_PMON_CTR3 is defined as MSR_PCU_PMON_CTR3 in SDM.\r |
dc5d621c | 3176 | **/\r |
2f88bd3a | 3177 | #define MSR_SANDY_BRIDGE_PCU_PMON_CTR3 0x00000C39\r |
dc5d621c MK |
3178 | \r |
3179 | /**\r | |
3180 | Package. Uncore C-box 0 perfmon local box wide control.\r | |
3181 | \r | |
3182 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL (0x00000D04)\r | |
3183 | @param EAX Lower 32-bits of MSR value.\r | |
3184 | @param EDX Upper 32-bits of MSR value.\r | |
3185 | \r | |
3186 | <b>Example usage</b>\r | |
3187 | @code\r | |
3188 | UINT64 Msr;\r | |
3189 | \r | |
3190 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL);\r | |
3191 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL, Msr);\r | |
3192 | @endcode\r | |
367f5c9c | 3193 | @note MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL is defined as MSR_C0_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3194 | **/\r |
2f88bd3a | 3195 | #define MSR_SANDY_BRIDGE_C0_PMON_BOX_CTL 0x00000D04\r |
dc5d621c MK |
3196 | \r |
3197 | /**\r | |
3198 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 0.\r | |
3199 | \r | |
3200 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 (0x00000D10)\r | |
3201 | @param EAX Lower 32-bits of MSR value.\r | |
3202 | @param EDX Upper 32-bits of MSR value.\r | |
3203 | \r | |
3204 | <b>Example usage</b>\r | |
3205 | @code\r | |
3206 | UINT64 Msr;\r | |
3207 | \r | |
3208 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0);\r | |
3209 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0, Msr);\r | |
3210 | @endcode\r | |
367f5c9c | 3211 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 is defined as MSR_C0_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3212 | **/\r |
2f88bd3a | 3213 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL0 0x00000D10\r |
dc5d621c MK |
3214 | \r |
3215 | /**\r | |
3216 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 1.\r | |
3217 | \r | |
3218 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 (0x00000D11)\r | |
3219 | @param EAX Lower 32-bits of MSR value.\r | |
3220 | @param EDX Upper 32-bits of MSR value.\r | |
3221 | \r | |
3222 | <b>Example usage</b>\r | |
3223 | @code\r | |
3224 | UINT64 Msr;\r | |
3225 | \r | |
3226 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1);\r | |
3227 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1, Msr);\r | |
3228 | @endcode\r | |
367f5c9c | 3229 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 is defined as MSR_C0_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3230 | **/\r |
2f88bd3a | 3231 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL1 0x00000D11\r |
dc5d621c MK |
3232 | \r |
3233 | /**\r | |
3234 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 2.\r | |
3235 | \r | |
3236 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 (0x00000D12)\r | |
3237 | @param EAX Lower 32-bits of MSR value.\r | |
3238 | @param EDX Upper 32-bits of MSR value.\r | |
3239 | \r | |
3240 | <b>Example usage</b>\r | |
3241 | @code\r | |
3242 | UINT64 Msr;\r | |
3243 | \r | |
3244 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2);\r | |
3245 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2, Msr);\r | |
3246 | @endcode\r | |
367f5c9c | 3247 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 is defined as MSR_C0_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3248 | **/\r |
2f88bd3a | 3249 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL2 0x00000D12\r |
dc5d621c MK |
3250 | \r |
3251 | /**\r | |
3252 | Package. Uncore C-box 0 perfmon event select for C-box 0 counter 3.\r | |
3253 | \r | |
3254 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 (0x00000D13)\r | |
3255 | @param EAX Lower 32-bits of MSR value.\r | |
3256 | @param EDX Upper 32-bits of MSR value.\r | |
3257 | \r | |
3258 | <b>Example usage</b>\r | |
3259 | @code\r | |
3260 | UINT64 Msr;\r | |
3261 | \r | |
3262 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3);\r | |
3263 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3, Msr);\r | |
3264 | @endcode\r | |
367f5c9c | 3265 | @note MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 is defined as MSR_C0_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3266 | **/\r |
2f88bd3a | 3267 | #define MSR_SANDY_BRIDGE_C0_PMON_EVNTSEL3 0x00000D13\r |
dc5d621c MK |
3268 | \r |
3269 | /**\r | |
3270 | Package. Uncore C-box 0 perfmon box wide filter.\r | |
3271 | \r | |
3272 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER (0x00000D14)\r | |
3273 | @param EAX Lower 32-bits of MSR value.\r | |
3274 | @param EDX Upper 32-bits of MSR value.\r | |
3275 | \r | |
3276 | <b>Example usage</b>\r | |
3277 | @code\r | |
3278 | UINT64 Msr;\r | |
3279 | \r | |
3280 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER);\r | |
3281 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER, Msr);\r | |
3282 | @endcode\r | |
367f5c9c | 3283 | @note MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER is defined as MSR_C0_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 3284 | **/\r |
2f88bd3a | 3285 | #define MSR_SANDY_BRIDGE_C0_PMON_BOX_FILTER 0x00000D14\r |
dc5d621c MK |
3286 | \r |
3287 | /**\r | |
3288 | Package. Uncore C-box 0 perfmon counter 0.\r | |
3289 | \r | |
3290 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR0 (0x00000D16)\r | |
3291 | @param EAX Lower 32-bits of MSR value.\r | |
3292 | @param EDX Upper 32-bits of MSR value.\r | |
3293 | \r | |
3294 | <b>Example usage</b>\r | |
3295 | @code\r | |
3296 | UINT64 Msr;\r | |
3297 | \r | |
3298 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0);\r | |
3299 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR0, Msr);\r | |
3300 | @endcode\r | |
367f5c9c | 3301 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR0 is defined as MSR_C0_PMON_CTR0 in SDM.\r |
dc5d621c | 3302 | **/\r |
2f88bd3a | 3303 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR0 0x00000D16\r |
dc5d621c MK |
3304 | \r |
3305 | /**\r | |
3306 | Package. Uncore C-box 0 perfmon counter 1.\r | |
3307 | \r | |
3308 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR1 (0x00000D17)\r | |
3309 | @param EAX Lower 32-bits of MSR value.\r | |
3310 | @param EDX Upper 32-bits of MSR value.\r | |
3311 | \r | |
3312 | <b>Example usage</b>\r | |
3313 | @code\r | |
3314 | UINT64 Msr;\r | |
3315 | \r | |
3316 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1);\r | |
3317 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR1, Msr);\r | |
3318 | @endcode\r | |
367f5c9c | 3319 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR1 is defined as MSR_C0_PMON_CTR1 in SDM.\r |
dc5d621c | 3320 | **/\r |
2f88bd3a | 3321 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR1 0x00000D17\r |
dc5d621c MK |
3322 | \r |
3323 | /**\r | |
3324 | Package. Uncore C-box 0 perfmon counter 2.\r | |
3325 | \r | |
3326 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR2 (0x00000D18)\r | |
3327 | @param EAX Lower 32-bits of MSR value.\r | |
3328 | @param EDX Upper 32-bits of MSR value.\r | |
3329 | \r | |
3330 | <b>Example usage</b>\r | |
3331 | @code\r | |
3332 | UINT64 Msr;\r | |
3333 | \r | |
3334 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2);\r | |
3335 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR2, Msr);\r | |
3336 | @endcode\r | |
367f5c9c | 3337 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR2 is defined as MSR_C0_PMON_CTR2 in SDM.\r |
dc5d621c | 3338 | **/\r |
2f88bd3a | 3339 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR2 0x00000D18\r |
dc5d621c MK |
3340 | \r |
3341 | /**\r | |
3342 | Package. Uncore C-box 0 perfmon counter 3.\r | |
3343 | \r | |
3344 | @param ECX MSR_SANDY_BRIDGE_C0_PMON_CTR3 (0x00000D19)\r | |
3345 | @param EAX Lower 32-bits of MSR value.\r | |
3346 | @param EDX Upper 32-bits of MSR value.\r | |
3347 | \r | |
3348 | <b>Example usage</b>\r | |
3349 | @code\r | |
3350 | UINT64 Msr;\r | |
3351 | \r | |
3352 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3);\r | |
3353 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C0_PMON_CTR3, Msr);\r | |
3354 | @endcode\r | |
367f5c9c | 3355 | @note MSR_SANDY_BRIDGE_C0_PMON_CTR3 is defined as MSR_C0_PMON_CTR3 in SDM.\r |
dc5d621c | 3356 | **/\r |
2f88bd3a | 3357 | #define MSR_SANDY_BRIDGE_C0_PMON_CTR3 0x00000D19\r |
dc5d621c MK |
3358 | \r |
3359 | /**\r | |
3360 | Package. Uncore C-box 1 perfmon local box wide control.\r | |
3361 | \r | |
3362 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL (0x00000D24)\r | |
3363 | @param EAX Lower 32-bits of MSR value.\r | |
3364 | @param EDX Upper 32-bits of MSR value.\r | |
3365 | \r | |
3366 | <b>Example usage</b>\r | |
3367 | @code\r | |
3368 | UINT64 Msr;\r | |
3369 | \r | |
3370 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL);\r | |
3371 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL, Msr);\r | |
3372 | @endcode\r | |
367f5c9c | 3373 | @note MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL is defined as MSR_C1_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3374 | **/\r |
2f88bd3a | 3375 | #define MSR_SANDY_BRIDGE_C1_PMON_BOX_CTL 0x00000D24\r |
dc5d621c MK |
3376 | \r |
3377 | /**\r | |
3378 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 0.\r | |
3379 | \r | |
3380 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 (0x00000D30)\r | |
3381 | @param EAX Lower 32-bits of MSR value.\r | |
3382 | @param EDX Upper 32-bits of MSR value.\r | |
3383 | \r | |
3384 | <b>Example usage</b>\r | |
3385 | @code\r | |
3386 | UINT64 Msr;\r | |
3387 | \r | |
3388 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0);\r | |
3389 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0, Msr);\r | |
3390 | @endcode\r | |
367f5c9c | 3391 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 is defined as MSR_C1_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3392 | **/\r |
2f88bd3a | 3393 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL0 0x00000D30\r |
dc5d621c MK |
3394 | \r |
3395 | /**\r | |
3396 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 1.\r | |
3397 | \r | |
3398 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 (0x00000D31)\r | |
3399 | @param EAX Lower 32-bits of MSR value.\r | |
3400 | @param EDX Upper 32-bits of MSR value.\r | |
3401 | \r | |
3402 | <b>Example usage</b>\r | |
3403 | @code\r | |
3404 | UINT64 Msr;\r | |
3405 | \r | |
3406 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1);\r | |
3407 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1, Msr);\r | |
3408 | @endcode\r | |
367f5c9c | 3409 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 is defined as MSR_C1_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3410 | **/\r |
2f88bd3a | 3411 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL1 0x00000D31\r |
dc5d621c MK |
3412 | \r |
3413 | /**\r | |
3414 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 2.\r | |
3415 | \r | |
3416 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 (0x00000D32)\r | |
3417 | @param EAX Lower 32-bits of MSR value.\r | |
3418 | @param EDX Upper 32-bits of MSR value.\r | |
3419 | \r | |
3420 | <b>Example usage</b>\r | |
3421 | @code\r | |
3422 | UINT64 Msr;\r | |
3423 | \r | |
3424 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2);\r | |
3425 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2, Msr);\r | |
3426 | @endcode\r | |
367f5c9c | 3427 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 is defined as MSR_C1_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3428 | **/\r |
2f88bd3a | 3429 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL2 0x00000D32\r |
dc5d621c MK |
3430 | \r |
3431 | /**\r | |
3432 | Package. Uncore C-box 1 perfmon event select for C-box 1 counter 3.\r | |
3433 | \r | |
3434 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 (0x00000D33)\r | |
3435 | @param EAX Lower 32-bits of MSR value.\r | |
3436 | @param EDX Upper 32-bits of MSR value.\r | |
3437 | \r | |
3438 | <b>Example usage</b>\r | |
3439 | @code\r | |
3440 | UINT64 Msr;\r | |
3441 | \r | |
3442 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3);\r | |
3443 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3, Msr);\r | |
3444 | @endcode\r | |
367f5c9c | 3445 | @note MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 is defined as MSR_C1_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3446 | **/\r |
2f88bd3a | 3447 | #define MSR_SANDY_BRIDGE_C1_PMON_EVNTSEL3 0x00000D33\r |
dc5d621c MK |
3448 | \r |
3449 | /**\r | |
3450 | Package. Uncore C-box 1 perfmon box wide filter.\r | |
3451 | \r | |
3452 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER (0x00000D34)\r | |
3453 | @param EAX Lower 32-bits of MSR value.\r | |
3454 | @param EDX Upper 32-bits of MSR value.\r | |
3455 | \r | |
3456 | <b>Example usage</b>\r | |
3457 | @code\r | |
3458 | UINT64 Msr;\r | |
3459 | \r | |
3460 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER);\r | |
3461 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER, Msr);\r | |
3462 | @endcode\r | |
367f5c9c | 3463 | @note MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER is defined as MSR_C1_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 3464 | **/\r |
2f88bd3a | 3465 | #define MSR_SANDY_BRIDGE_C1_PMON_BOX_FILTER 0x00000D34\r |
dc5d621c MK |
3466 | \r |
3467 | /**\r | |
3468 | Package. Uncore C-box 1 perfmon counter 0.\r | |
3469 | \r | |
3470 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR0 (0x00000D36)\r | |
3471 | @param EAX Lower 32-bits of MSR value.\r | |
3472 | @param EDX Upper 32-bits of MSR value.\r | |
3473 | \r | |
3474 | <b>Example usage</b>\r | |
3475 | @code\r | |
3476 | UINT64 Msr;\r | |
3477 | \r | |
3478 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0);\r | |
3479 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR0, Msr);\r | |
3480 | @endcode\r | |
367f5c9c | 3481 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR0 is defined as MSR_C1_PMON_CTR0 in SDM.\r |
dc5d621c | 3482 | **/\r |
2f88bd3a | 3483 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR0 0x00000D36\r |
dc5d621c MK |
3484 | \r |
3485 | /**\r | |
3486 | Package. Uncore C-box 1 perfmon counter 1.\r | |
3487 | \r | |
3488 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR1 (0x00000D37)\r | |
3489 | @param EAX Lower 32-bits of MSR value.\r | |
3490 | @param EDX Upper 32-bits of MSR value.\r | |
3491 | \r | |
3492 | <b>Example usage</b>\r | |
3493 | @code\r | |
3494 | UINT64 Msr;\r | |
3495 | \r | |
3496 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1);\r | |
3497 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR1, Msr);\r | |
3498 | @endcode\r | |
367f5c9c | 3499 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR1 is defined as MSR_C1_PMON_CTR1 in SDM.\r |
dc5d621c | 3500 | **/\r |
2f88bd3a | 3501 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR1 0x00000D37\r |
dc5d621c MK |
3502 | \r |
3503 | /**\r | |
3504 | Package. Uncore C-box 1 perfmon counter 2.\r | |
3505 | \r | |
3506 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR2 (0x00000D38)\r | |
3507 | @param EAX Lower 32-bits of MSR value.\r | |
3508 | @param EDX Upper 32-bits of MSR value.\r | |
3509 | \r | |
3510 | <b>Example usage</b>\r | |
3511 | @code\r | |
3512 | UINT64 Msr;\r | |
3513 | \r | |
3514 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2);\r | |
3515 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR2, Msr);\r | |
3516 | @endcode\r | |
367f5c9c | 3517 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR2 is defined as MSR_C1_PMON_CTR2 in SDM.\r |
dc5d621c | 3518 | **/\r |
2f88bd3a | 3519 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR2 0x00000D38\r |
dc5d621c MK |
3520 | \r |
3521 | /**\r | |
3522 | Package. Uncore C-box 1 perfmon counter 3.\r | |
3523 | \r | |
3524 | @param ECX MSR_SANDY_BRIDGE_C1_PMON_CTR3 (0x00000D39)\r | |
3525 | @param EAX Lower 32-bits of MSR value.\r | |
3526 | @param EDX Upper 32-bits of MSR value.\r | |
3527 | \r | |
3528 | <b>Example usage</b>\r | |
3529 | @code\r | |
3530 | UINT64 Msr;\r | |
3531 | \r | |
3532 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3);\r | |
3533 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C1_PMON_CTR3, Msr);\r | |
3534 | @endcode\r | |
367f5c9c | 3535 | @note MSR_SANDY_BRIDGE_C1_PMON_CTR3 is defined as MSR_C1_PMON_CTR3 in SDM.\r |
dc5d621c | 3536 | **/\r |
2f88bd3a | 3537 | #define MSR_SANDY_BRIDGE_C1_PMON_CTR3 0x00000D39\r |
dc5d621c MK |
3538 | \r |
3539 | /**\r | |
3540 | Package. Uncore C-box 2 perfmon local box wide control.\r | |
3541 | \r | |
3542 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL (0x00000D44)\r | |
3543 | @param EAX Lower 32-bits of MSR value.\r | |
3544 | @param EDX Upper 32-bits of MSR value.\r | |
3545 | \r | |
3546 | <b>Example usage</b>\r | |
3547 | @code\r | |
3548 | UINT64 Msr;\r | |
3549 | \r | |
3550 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL);\r | |
3551 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL, Msr);\r | |
3552 | @endcode\r | |
367f5c9c | 3553 | @note MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL is defined as MSR_C2_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3554 | **/\r |
2f88bd3a | 3555 | #define MSR_SANDY_BRIDGE_C2_PMON_BOX_CTL 0x00000D44\r |
dc5d621c MK |
3556 | \r |
3557 | /**\r | |
3558 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 0.\r | |
3559 | \r | |
3560 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 (0x00000D50)\r | |
3561 | @param EAX Lower 32-bits of MSR value.\r | |
3562 | @param EDX Upper 32-bits of MSR value.\r | |
3563 | \r | |
3564 | <b>Example usage</b>\r | |
3565 | @code\r | |
3566 | UINT64 Msr;\r | |
3567 | \r | |
3568 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0);\r | |
3569 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0, Msr);\r | |
3570 | @endcode\r | |
367f5c9c | 3571 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 is defined as MSR_C2_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3572 | **/\r |
2f88bd3a | 3573 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL0 0x00000D50\r |
dc5d621c MK |
3574 | \r |
3575 | /**\r | |
3576 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 1.\r | |
3577 | \r | |
3578 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 (0x00000D51)\r | |
3579 | @param EAX Lower 32-bits of MSR value.\r | |
3580 | @param EDX Upper 32-bits of MSR value.\r | |
3581 | \r | |
3582 | <b>Example usage</b>\r | |
3583 | @code\r | |
3584 | UINT64 Msr;\r | |
3585 | \r | |
3586 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1);\r | |
3587 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1, Msr);\r | |
3588 | @endcode\r | |
367f5c9c | 3589 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 is defined as MSR_C2_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3590 | **/\r |
2f88bd3a | 3591 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL1 0x00000D51\r |
dc5d621c MK |
3592 | \r |
3593 | /**\r | |
3594 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 2.\r | |
3595 | \r | |
3596 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 (0x00000D52)\r | |
3597 | @param EAX Lower 32-bits of MSR value.\r | |
3598 | @param EDX Upper 32-bits of MSR value.\r | |
3599 | \r | |
3600 | <b>Example usage</b>\r | |
3601 | @code\r | |
3602 | UINT64 Msr;\r | |
3603 | \r | |
3604 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2);\r | |
3605 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2, Msr);\r | |
3606 | @endcode\r | |
367f5c9c | 3607 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 is defined as MSR_C2_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3608 | **/\r |
2f88bd3a | 3609 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL2 0x00000D52\r |
dc5d621c MK |
3610 | \r |
3611 | /**\r | |
3612 | Package. Uncore C-box 2 perfmon event select for C-box 2 counter 3.\r | |
3613 | \r | |
3614 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 (0x00000D53)\r | |
3615 | @param EAX Lower 32-bits of MSR value.\r | |
3616 | @param EDX Upper 32-bits of MSR value.\r | |
3617 | \r | |
3618 | <b>Example usage</b>\r | |
3619 | @code\r | |
3620 | UINT64 Msr;\r | |
3621 | \r | |
3622 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3);\r | |
3623 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3, Msr);\r | |
3624 | @endcode\r | |
367f5c9c | 3625 | @note MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 is defined as MSR_C2_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3626 | **/\r |
2f88bd3a | 3627 | #define MSR_SANDY_BRIDGE_C2_PMON_EVNTSEL3 0x00000D53\r |
dc5d621c MK |
3628 | \r |
3629 | /**\r | |
3630 | Package. Uncore C-box 2 perfmon box wide filter.\r | |
3631 | \r | |
3632 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER (0x00000D54)\r | |
3633 | @param EAX Lower 32-bits of MSR value.\r | |
3634 | @param EDX Upper 32-bits of MSR value.\r | |
3635 | \r | |
3636 | <b>Example usage</b>\r | |
3637 | @code\r | |
3638 | UINT64 Msr;\r | |
3639 | \r | |
3640 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER);\r | |
3641 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER, Msr);\r | |
3642 | @endcode\r | |
367f5c9c | 3643 | @note MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER is defined as MSR_C2_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 3644 | **/\r |
2f88bd3a | 3645 | #define MSR_SANDY_BRIDGE_C2_PMON_BOX_FILTER 0x00000D54\r |
dc5d621c MK |
3646 | \r |
3647 | /**\r | |
3648 | Package. Uncore C-box 2 perfmon counter 0.\r | |
3649 | \r | |
3650 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR0 (0x00000D56)\r | |
3651 | @param EAX Lower 32-bits of MSR value.\r | |
3652 | @param EDX Upper 32-bits of MSR value.\r | |
3653 | \r | |
3654 | <b>Example usage</b>\r | |
3655 | @code\r | |
3656 | UINT64 Msr;\r | |
3657 | \r | |
3658 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0);\r | |
3659 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR0, Msr);\r | |
3660 | @endcode\r | |
367f5c9c | 3661 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR0 is defined as MSR_C2_PMON_CTR0 in SDM.\r |
dc5d621c | 3662 | **/\r |
2f88bd3a | 3663 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR0 0x00000D56\r |
dc5d621c MK |
3664 | \r |
3665 | /**\r | |
3666 | Package. Uncore C-box 2 perfmon counter 1.\r | |
3667 | \r | |
3668 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR1 (0x00000D57)\r | |
3669 | @param EAX Lower 32-bits of MSR value.\r | |
3670 | @param EDX Upper 32-bits of MSR value.\r | |
3671 | \r | |
3672 | <b>Example usage</b>\r | |
3673 | @code\r | |
3674 | UINT64 Msr;\r | |
3675 | \r | |
3676 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1);\r | |
3677 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR1, Msr);\r | |
3678 | @endcode\r | |
367f5c9c | 3679 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR1 is defined as MSR_C2_PMON_CTR1 in SDM.\r |
dc5d621c | 3680 | **/\r |
2f88bd3a | 3681 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR1 0x00000D57\r |
dc5d621c MK |
3682 | \r |
3683 | /**\r | |
3684 | Package. Uncore C-box 2 perfmon counter 2.\r | |
3685 | \r | |
3686 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR2 (0x00000D58)\r | |
3687 | @param EAX Lower 32-bits of MSR value.\r | |
3688 | @param EDX Upper 32-bits of MSR value.\r | |
3689 | \r | |
3690 | <b>Example usage</b>\r | |
3691 | @code\r | |
3692 | UINT64 Msr;\r | |
3693 | \r | |
3694 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2);\r | |
3695 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR2, Msr);\r | |
3696 | @endcode\r | |
367f5c9c | 3697 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR2 is defined as MSR_C2_PMON_CTR2 in SDM.\r |
dc5d621c | 3698 | **/\r |
2f88bd3a | 3699 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR2 0x00000D58\r |
dc5d621c MK |
3700 | \r |
3701 | /**\r | |
3702 | Package. Uncore C-box 2 perfmon counter 3.\r | |
3703 | \r | |
3704 | @param ECX MSR_SANDY_BRIDGE_C2_PMON_CTR3 (0x00000D59)\r | |
3705 | @param EAX Lower 32-bits of MSR value.\r | |
3706 | @param EDX Upper 32-bits of MSR value.\r | |
3707 | \r | |
3708 | <b>Example usage</b>\r | |
3709 | @code\r | |
3710 | UINT64 Msr;\r | |
3711 | \r | |
3712 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3);\r | |
3713 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C2_PMON_CTR3, Msr);\r | |
3714 | @endcode\r | |
367f5c9c | 3715 | @note MSR_SANDY_BRIDGE_C2_PMON_CTR3 is defined as MSR_C2_PMON_CTR3 in SDM.\r |
dc5d621c | 3716 | **/\r |
2f88bd3a | 3717 | #define MSR_SANDY_BRIDGE_C2_PMON_CTR3 0x00000D59\r |
dc5d621c MK |
3718 | \r |
3719 | /**\r | |
3720 | Package. Uncore C-box 3 perfmon local box wide control.\r | |
3721 | \r | |
3722 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL (0x00000D64)\r | |
3723 | @param EAX Lower 32-bits of MSR value.\r | |
3724 | @param EDX Upper 32-bits of MSR value.\r | |
3725 | \r | |
3726 | <b>Example usage</b>\r | |
3727 | @code\r | |
3728 | UINT64 Msr;\r | |
3729 | \r | |
3730 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL);\r | |
3731 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL, Msr);\r | |
3732 | @endcode\r | |
367f5c9c | 3733 | @note MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL is defined as MSR_C3_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3734 | **/\r |
2f88bd3a | 3735 | #define MSR_SANDY_BRIDGE_C3_PMON_BOX_CTL 0x00000D64\r |
dc5d621c MK |
3736 | \r |
3737 | /**\r | |
3738 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 0.\r | |
3739 | \r | |
3740 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 (0x00000D70)\r | |
3741 | @param EAX Lower 32-bits of MSR value.\r | |
3742 | @param EDX Upper 32-bits of MSR value.\r | |
3743 | \r | |
3744 | <b>Example usage</b>\r | |
3745 | @code\r | |
3746 | UINT64 Msr;\r | |
3747 | \r | |
3748 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0);\r | |
3749 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0, Msr);\r | |
3750 | @endcode\r | |
367f5c9c | 3751 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 is defined as MSR_C3_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3752 | **/\r |
2f88bd3a | 3753 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL0 0x00000D70\r |
dc5d621c MK |
3754 | \r |
3755 | /**\r | |
3756 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 1.\r | |
3757 | \r | |
3758 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 (0x00000D71)\r | |
3759 | @param EAX Lower 32-bits of MSR value.\r | |
3760 | @param EDX Upper 32-bits of MSR value.\r | |
3761 | \r | |
3762 | <b>Example usage</b>\r | |
3763 | @code\r | |
3764 | UINT64 Msr;\r | |
3765 | \r | |
3766 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1);\r | |
3767 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1, Msr);\r | |
3768 | @endcode\r | |
367f5c9c | 3769 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 is defined as MSR_C3_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3770 | **/\r |
2f88bd3a | 3771 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL1 0x00000D71\r |
dc5d621c MK |
3772 | \r |
3773 | /**\r | |
3774 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 2.\r | |
3775 | \r | |
3776 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 (0x00000D72)\r | |
3777 | @param EAX Lower 32-bits of MSR value.\r | |
3778 | @param EDX Upper 32-bits of MSR value.\r | |
3779 | \r | |
3780 | <b>Example usage</b>\r | |
3781 | @code\r | |
3782 | UINT64 Msr;\r | |
3783 | \r | |
3784 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2);\r | |
3785 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2, Msr);\r | |
3786 | @endcode\r | |
367f5c9c | 3787 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 is defined as MSR_C3_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3788 | **/\r |
2f88bd3a | 3789 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL2 0x00000D72\r |
dc5d621c MK |
3790 | \r |
3791 | /**\r | |
3792 | Package. Uncore C-box 3 perfmon event select for C-box 3 counter 3.\r | |
3793 | \r | |
3794 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 (0x00000D73)\r | |
3795 | @param EAX Lower 32-bits of MSR value.\r | |
3796 | @param EDX Upper 32-bits of MSR value.\r | |
3797 | \r | |
3798 | <b>Example usage</b>\r | |
3799 | @code\r | |
3800 | UINT64 Msr;\r | |
3801 | \r | |
3802 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3);\r | |
3803 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3, Msr);\r | |
3804 | @endcode\r | |
367f5c9c | 3805 | @note MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 is defined as MSR_C3_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3806 | **/\r |
2f88bd3a | 3807 | #define MSR_SANDY_BRIDGE_C3_PMON_EVNTSEL3 0x00000D73\r |
dc5d621c MK |
3808 | \r |
3809 | /**\r | |
3810 | Package. Uncore C-box 3 perfmon box wide filter.\r | |
3811 | \r | |
3812 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER (0x00000D74)\r | |
3813 | @param EAX Lower 32-bits of MSR value.\r | |
3814 | @param EDX Upper 32-bits of MSR value.\r | |
3815 | \r | |
3816 | <b>Example usage</b>\r | |
3817 | @code\r | |
3818 | UINT64 Msr;\r | |
3819 | \r | |
3820 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER);\r | |
3821 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER, Msr);\r | |
3822 | @endcode\r | |
367f5c9c | 3823 | @note MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER is defined as MSR_C3_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 3824 | **/\r |
2f88bd3a | 3825 | #define MSR_SANDY_BRIDGE_C3_PMON_BOX_FILTER 0x00000D74\r |
dc5d621c MK |
3826 | \r |
3827 | /**\r | |
3828 | Package. Uncore C-box 3 perfmon counter 0.\r | |
3829 | \r | |
3830 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR0 (0x00000D76)\r | |
3831 | @param EAX Lower 32-bits of MSR value.\r | |
3832 | @param EDX Upper 32-bits of MSR value.\r | |
3833 | \r | |
3834 | <b>Example usage</b>\r | |
3835 | @code\r | |
3836 | UINT64 Msr;\r | |
3837 | \r | |
3838 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0);\r | |
3839 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR0, Msr);\r | |
3840 | @endcode\r | |
367f5c9c | 3841 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR0 is defined as MSR_C3_PMON_CTR0 in SDM.\r |
dc5d621c | 3842 | **/\r |
2f88bd3a | 3843 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR0 0x00000D76\r |
dc5d621c MK |
3844 | \r |
3845 | /**\r | |
3846 | Package. Uncore C-box 3 perfmon counter 1.\r | |
3847 | \r | |
3848 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR1 (0x00000D77)\r | |
3849 | @param EAX Lower 32-bits of MSR value.\r | |
3850 | @param EDX Upper 32-bits of MSR value.\r | |
3851 | \r | |
3852 | <b>Example usage</b>\r | |
3853 | @code\r | |
3854 | UINT64 Msr;\r | |
3855 | \r | |
3856 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1);\r | |
3857 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR1, Msr);\r | |
3858 | @endcode\r | |
367f5c9c | 3859 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR1 is defined as MSR_C3_PMON_CTR1 in SDM.\r |
dc5d621c | 3860 | **/\r |
2f88bd3a | 3861 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR1 0x00000D77\r |
dc5d621c MK |
3862 | \r |
3863 | /**\r | |
3864 | Package. Uncore C-box 3 perfmon counter 2.\r | |
3865 | \r | |
3866 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR2 (0x00000D78)\r | |
3867 | @param EAX Lower 32-bits of MSR value.\r | |
3868 | @param EDX Upper 32-bits of MSR value.\r | |
3869 | \r | |
3870 | <b>Example usage</b>\r | |
3871 | @code\r | |
3872 | UINT64 Msr;\r | |
3873 | \r | |
3874 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2);\r | |
3875 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR2, Msr);\r | |
3876 | @endcode\r | |
367f5c9c | 3877 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR2 is defined as MSR_C3_PMON_CTR2 in SDM.\r |
dc5d621c | 3878 | **/\r |
2f88bd3a | 3879 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR2 0x00000D78\r |
dc5d621c MK |
3880 | \r |
3881 | /**\r | |
3882 | Package. Uncore C-box 3 perfmon counter 3.\r | |
3883 | \r | |
3884 | @param ECX MSR_SANDY_BRIDGE_C3_PMON_CTR3 (0x00000D79)\r | |
3885 | @param EAX Lower 32-bits of MSR value.\r | |
3886 | @param EDX Upper 32-bits of MSR value.\r | |
3887 | \r | |
3888 | <b>Example usage</b>\r | |
3889 | @code\r | |
3890 | UINT64 Msr;\r | |
3891 | \r | |
3892 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3);\r | |
3893 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C3_PMON_CTR3, Msr);\r | |
3894 | @endcode\r | |
367f5c9c | 3895 | @note MSR_SANDY_BRIDGE_C3_PMON_CTR3 is defined as MSR_C3_PMON_CTR3 in SDM.\r |
dc5d621c | 3896 | **/\r |
2f88bd3a | 3897 | #define MSR_SANDY_BRIDGE_C3_PMON_CTR3 0x00000D79\r |
dc5d621c MK |
3898 | \r |
3899 | /**\r | |
3900 | Package. Uncore C-box 4 perfmon local box wide control.\r | |
3901 | \r | |
3902 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL (0x00000D84)\r | |
3903 | @param EAX Lower 32-bits of MSR value.\r | |
3904 | @param EDX Upper 32-bits of MSR value.\r | |
3905 | \r | |
3906 | <b>Example usage</b>\r | |
3907 | @code\r | |
3908 | UINT64 Msr;\r | |
3909 | \r | |
3910 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL);\r | |
3911 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL, Msr);\r | |
3912 | @endcode\r | |
367f5c9c | 3913 | @note MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL is defined as MSR_C4_PMON_BOX_CTL in SDM.\r |
dc5d621c | 3914 | **/\r |
2f88bd3a | 3915 | #define MSR_SANDY_BRIDGE_C4_PMON_BOX_CTL 0x00000D84\r |
dc5d621c MK |
3916 | \r |
3917 | /**\r | |
3918 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 0.\r | |
3919 | \r | |
3920 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 (0x00000D90)\r | |
3921 | @param EAX Lower 32-bits of MSR value.\r | |
3922 | @param EDX Upper 32-bits of MSR value.\r | |
3923 | \r | |
3924 | <b>Example usage</b>\r | |
3925 | @code\r | |
3926 | UINT64 Msr;\r | |
3927 | \r | |
3928 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0);\r | |
3929 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0, Msr);\r | |
3930 | @endcode\r | |
367f5c9c | 3931 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 is defined as MSR_C4_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 3932 | **/\r |
2f88bd3a | 3933 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL0 0x00000D90\r |
dc5d621c MK |
3934 | \r |
3935 | /**\r | |
3936 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 1.\r | |
3937 | \r | |
3938 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 (0x00000D91)\r | |
3939 | @param EAX Lower 32-bits of MSR value.\r | |
3940 | @param EDX Upper 32-bits of MSR value.\r | |
3941 | \r | |
3942 | <b>Example usage</b>\r | |
3943 | @code\r | |
3944 | UINT64 Msr;\r | |
3945 | \r | |
3946 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1);\r | |
3947 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1, Msr);\r | |
3948 | @endcode\r | |
367f5c9c | 3949 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 is defined as MSR_C4_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 3950 | **/\r |
2f88bd3a | 3951 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL1 0x00000D91\r |
dc5d621c MK |
3952 | \r |
3953 | /**\r | |
3954 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 2.\r | |
3955 | \r | |
3956 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 (0x00000D92)\r | |
3957 | @param EAX Lower 32-bits of MSR value.\r | |
3958 | @param EDX Upper 32-bits of MSR value.\r | |
3959 | \r | |
3960 | <b>Example usage</b>\r | |
3961 | @code\r | |
3962 | UINT64 Msr;\r | |
3963 | \r | |
3964 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2);\r | |
3965 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2, Msr);\r | |
3966 | @endcode\r | |
367f5c9c | 3967 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 is defined as MSR_C4_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 3968 | **/\r |
2f88bd3a | 3969 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL2 0x00000D92\r |
dc5d621c MK |
3970 | \r |
3971 | /**\r | |
3972 | Package. Uncore C-box 4 perfmon event select for C-box 4 counter 3.\r | |
3973 | \r | |
3974 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 (0x00000D93)\r | |
3975 | @param EAX Lower 32-bits of MSR value.\r | |
3976 | @param EDX Upper 32-bits of MSR value.\r | |
3977 | \r | |
3978 | <b>Example usage</b>\r | |
3979 | @code\r | |
3980 | UINT64 Msr;\r | |
3981 | \r | |
3982 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3);\r | |
3983 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3, Msr);\r | |
3984 | @endcode\r | |
367f5c9c | 3985 | @note MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 is defined as MSR_C4_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 3986 | **/\r |
2f88bd3a | 3987 | #define MSR_SANDY_BRIDGE_C4_PMON_EVNTSEL3 0x00000D93\r |
dc5d621c MK |
3988 | \r |
3989 | /**\r | |
3990 | Package. Uncore C-box 4 perfmon box wide filter.\r | |
3991 | \r | |
3992 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER (0x00000D94)\r | |
3993 | @param EAX Lower 32-bits of MSR value.\r | |
3994 | @param EDX Upper 32-bits of MSR value.\r | |
3995 | \r | |
3996 | <b>Example usage</b>\r | |
3997 | @code\r | |
3998 | UINT64 Msr;\r | |
3999 | \r | |
4000 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER);\r | |
4001 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER, Msr);\r | |
4002 | @endcode\r | |
367f5c9c | 4003 | @note MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER is defined as MSR_C4_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 4004 | **/\r |
2f88bd3a | 4005 | #define MSR_SANDY_BRIDGE_C4_PMON_BOX_FILTER 0x00000D94\r |
dc5d621c MK |
4006 | \r |
4007 | /**\r | |
4008 | Package. Uncore C-box 4 perfmon counter 0.\r | |
4009 | \r | |
4010 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR0 (0x00000D96)\r | |
4011 | @param EAX Lower 32-bits of MSR value.\r | |
4012 | @param EDX Upper 32-bits of MSR value.\r | |
4013 | \r | |
4014 | <b>Example usage</b>\r | |
4015 | @code\r | |
4016 | UINT64 Msr;\r | |
4017 | \r | |
4018 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0);\r | |
4019 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR0, Msr);\r | |
4020 | @endcode\r | |
367f5c9c | 4021 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR0 is defined as MSR_C4_PMON_CTR0 in SDM.\r |
dc5d621c | 4022 | **/\r |
2f88bd3a | 4023 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR0 0x00000D96\r |
dc5d621c MK |
4024 | \r |
4025 | /**\r | |
4026 | Package. Uncore C-box 4 perfmon counter 1.\r | |
4027 | \r | |
4028 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR1 (0x00000D97)\r | |
4029 | @param EAX Lower 32-bits of MSR value.\r | |
4030 | @param EDX Upper 32-bits of MSR value.\r | |
4031 | \r | |
4032 | <b>Example usage</b>\r | |
4033 | @code\r | |
4034 | UINT64 Msr;\r | |
4035 | \r | |
4036 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1);\r | |
4037 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR1, Msr);\r | |
4038 | @endcode\r | |
367f5c9c | 4039 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR1 is defined as MSR_C4_PMON_CTR1 in SDM.\r |
dc5d621c | 4040 | **/\r |
2f88bd3a | 4041 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR1 0x00000D97\r |
dc5d621c MK |
4042 | \r |
4043 | /**\r | |
4044 | Package. Uncore C-box 4 perfmon counter 2.\r | |
4045 | \r | |
4046 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR2 (0x00000D98)\r | |
4047 | @param EAX Lower 32-bits of MSR value.\r | |
4048 | @param EDX Upper 32-bits of MSR value.\r | |
4049 | \r | |
4050 | <b>Example usage</b>\r | |
4051 | @code\r | |
4052 | UINT64 Msr;\r | |
4053 | \r | |
4054 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2);\r | |
4055 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR2, Msr);\r | |
4056 | @endcode\r | |
367f5c9c | 4057 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR2 is defined as MSR_C4_PMON_CTR2 in SDM.\r |
dc5d621c | 4058 | **/\r |
2f88bd3a | 4059 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR2 0x00000D98\r |
dc5d621c MK |
4060 | \r |
4061 | /**\r | |
4062 | Package. Uncore C-box 4 perfmon counter 3.\r | |
4063 | \r | |
4064 | @param ECX MSR_SANDY_BRIDGE_C4_PMON_CTR3 (0x00000D99)\r | |
4065 | @param EAX Lower 32-bits of MSR value.\r | |
4066 | @param EDX Upper 32-bits of MSR value.\r | |
4067 | \r | |
4068 | <b>Example usage</b>\r | |
4069 | @code\r | |
4070 | UINT64 Msr;\r | |
4071 | \r | |
4072 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3);\r | |
4073 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C4_PMON_CTR3, Msr);\r | |
4074 | @endcode\r | |
367f5c9c | 4075 | @note MSR_SANDY_BRIDGE_C4_PMON_CTR3 is defined as MSR_C4_PMON_CTR3 in SDM.\r |
dc5d621c | 4076 | **/\r |
2f88bd3a | 4077 | #define MSR_SANDY_BRIDGE_C4_PMON_CTR3 0x00000D99\r |
dc5d621c MK |
4078 | \r |
4079 | /**\r | |
4080 | Package. Uncore C-box 5 perfmon local box wide control.\r | |
4081 | \r | |
4082 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL (0x00000DA4)\r | |
4083 | @param EAX Lower 32-bits of MSR value.\r | |
4084 | @param EDX Upper 32-bits of MSR value.\r | |
4085 | \r | |
4086 | <b>Example usage</b>\r | |
4087 | @code\r | |
4088 | UINT64 Msr;\r | |
4089 | \r | |
4090 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL);\r | |
4091 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL, Msr);\r | |
4092 | @endcode\r | |
367f5c9c | 4093 | @note MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL is defined as MSR_C5_PMON_BOX_CTL in SDM.\r |
dc5d621c | 4094 | **/\r |
2f88bd3a | 4095 | #define MSR_SANDY_BRIDGE_C5_PMON_BOX_CTL 0x00000DA4\r |
dc5d621c MK |
4096 | \r |
4097 | /**\r | |
4098 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 0.\r | |
4099 | \r | |
4100 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 (0x00000DB0)\r | |
4101 | @param EAX Lower 32-bits of MSR value.\r | |
4102 | @param EDX Upper 32-bits of MSR value.\r | |
4103 | \r | |
4104 | <b>Example usage</b>\r | |
4105 | @code\r | |
4106 | UINT64 Msr;\r | |
4107 | \r | |
4108 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0);\r | |
4109 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0, Msr);\r | |
4110 | @endcode\r | |
367f5c9c | 4111 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 is defined as MSR_C5_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 4112 | **/\r |
2f88bd3a | 4113 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL0 0x00000DB0\r |
dc5d621c MK |
4114 | \r |
4115 | /**\r | |
4116 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 1.\r | |
4117 | \r | |
4118 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 (0x00000DB1)\r | |
4119 | @param EAX Lower 32-bits of MSR value.\r | |
4120 | @param EDX Upper 32-bits of MSR value.\r | |
4121 | \r | |
4122 | <b>Example usage</b>\r | |
4123 | @code\r | |
4124 | UINT64 Msr;\r | |
4125 | \r | |
4126 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1);\r | |
4127 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1, Msr);\r | |
4128 | @endcode\r | |
367f5c9c | 4129 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 is defined as MSR_C5_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 4130 | **/\r |
2f88bd3a | 4131 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL1 0x00000DB1\r |
dc5d621c MK |
4132 | \r |
4133 | /**\r | |
4134 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 2.\r | |
4135 | \r | |
4136 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 (0x00000DB2)\r | |
4137 | @param EAX Lower 32-bits of MSR value.\r | |
4138 | @param EDX Upper 32-bits of MSR value.\r | |
4139 | \r | |
4140 | <b>Example usage</b>\r | |
4141 | @code\r | |
4142 | UINT64 Msr;\r | |
4143 | \r | |
4144 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2);\r | |
4145 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2, Msr);\r | |
4146 | @endcode\r | |
367f5c9c | 4147 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 is defined as MSR_C5_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 4148 | **/\r |
2f88bd3a | 4149 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL2 0x00000DB2\r |
dc5d621c MK |
4150 | \r |
4151 | /**\r | |
4152 | Package. Uncore C-box 5 perfmon event select for C-box 5 counter 3.\r | |
4153 | \r | |
4154 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 (0x00000DB3)\r | |
4155 | @param EAX Lower 32-bits of MSR value.\r | |
4156 | @param EDX Upper 32-bits of MSR value.\r | |
4157 | \r | |
4158 | <b>Example usage</b>\r | |
4159 | @code\r | |
4160 | UINT64 Msr;\r | |
4161 | \r | |
4162 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3);\r | |
4163 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3, Msr);\r | |
4164 | @endcode\r | |
367f5c9c | 4165 | @note MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 is defined as MSR_C5_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 4166 | **/\r |
2f88bd3a | 4167 | #define MSR_SANDY_BRIDGE_C5_PMON_EVNTSEL3 0x00000DB3\r |
dc5d621c MK |
4168 | \r |
4169 | /**\r | |
4170 | Package. Uncore C-box 5 perfmon box wide filter.\r | |
4171 | \r | |
4172 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER (0x00000DB4)\r | |
4173 | @param EAX Lower 32-bits of MSR value.\r | |
4174 | @param EDX Upper 32-bits of MSR value.\r | |
4175 | \r | |
4176 | <b>Example usage</b>\r | |
4177 | @code\r | |
4178 | UINT64 Msr;\r | |
4179 | \r | |
4180 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER);\r | |
4181 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER, Msr);\r | |
4182 | @endcode\r | |
367f5c9c | 4183 | @note MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER is defined as MSR_C5_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 4184 | **/\r |
2f88bd3a | 4185 | #define MSR_SANDY_BRIDGE_C5_PMON_BOX_FILTER 0x00000DB4\r |
dc5d621c MK |
4186 | \r |
4187 | /**\r | |
4188 | Package. Uncore C-box 5 perfmon counter 0.\r | |
4189 | \r | |
4190 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR0 (0x00000DB6)\r | |
4191 | @param EAX Lower 32-bits of MSR value.\r | |
4192 | @param EDX Upper 32-bits of MSR value.\r | |
4193 | \r | |
4194 | <b>Example usage</b>\r | |
4195 | @code\r | |
4196 | UINT64 Msr;\r | |
4197 | \r | |
4198 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0);\r | |
4199 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR0, Msr);\r | |
4200 | @endcode\r | |
367f5c9c | 4201 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR0 is defined as MSR_C5_PMON_CTR0 in SDM.\r |
dc5d621c | 4202 | **/\r |
2f88bd3a | 4203 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR0 0x00000DB6\r |
dc5d621c MK |
4204 | \r |
4205 | /**\r | |
4206 | Package. Uncore C-box 5 perfmon counter 1.\r | |
4207 | \r | |
4208 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR1 (0x00000DB7)\r | |
4209 | @param EAX Lower 32-bits of MSR value.\r | |
4210 | @param EDX Upper 32-bits of MSR value.\r | |
4211 | \r | |
4212 | <b>Example usage</b>\r | |
4213 | @code\r | |
4214 | UINT64 Msr;\r | |
4215 | \r | |
4216 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1);\r | |
4217 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR1, Msr);\r | |
4218 | @endcode\r | |
367f5c9c | 4219 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR1 is defined as MSR_C5_PMON_CTR1 in SDM.\r |
dc5d621c | 4220 | **/\r |
2f88bd3a | 4221 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR1 0x00000DB7\r |
dc5d621c MK |
4222 | \r |
4223 | /**\r | |
4224 | Package. Uncore C-box 5 perfmon counter 2.\r | |
4225 | \r | |
4226 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR2 (0x00000DB8)\r | |
4227 | @param EAX Lower 32-bits of MSR value.\r | |
4228 | @param EDX Upper 32-bits of MSR value.\r | |
4229 | \r | |
4230 | <b>Example usage</b>\r | |
4231 | @code\r | |
4232 | UINT64 Msr;\r | |
4233 | \r | |
4234 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2);\r | |
4235 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR2, Msr);\r | |
4236 | @endcode\r | |
367f5c9c | 4237 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR2 is defined as MSR_C5_PMON_CTR2 in SDM.\r |
dc5d621c | 4238 | **/\r |
2f88bd3a | 4239 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR2 0x00000DB8\r |
dc5d621c MK |
4240 | \r |
4241 | /**\r | |
4242 | Package. Uncore C-box 5 perfmon counter 3.\r | |
4243 | \r | |
4244 | @param ECX MSR_SANDY_BRIDGE_C5_PMON_CTR3 (0x00000DB9)\r | |
4245 | @param EAX Lower 32-bits of MSR value.\r | |
4246 | @param EDX Upper 32-bits of MSR value.\r | |
4247 | \r | |
4248 | <b>Example usage</b>\r | |
4249 | @code\r | |
4250 | UINT64 Msr;\r | |
4251 | \r | |
4252 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3);\r | |
4253 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C5_PMON_CTR3, Msr);\r | |
4254 | @endcode\r | |
367f5c9c | 4255 | @note MSR_SANDY_BRIDGE_C5_PMON_CTR3 is defined as MSR_C5_PMON_CTR3 in SDM.\r |
dc5d621c | 4256 | **/\r |
2f88bd3a | 4257 | #define MSR_SANDY_BRIDGE_C5_PMON_CTR3 0x00000DB9\r |
dc5d621c MK |
4258 | \r |
4259 | /**\r | |
4260 | Package. Uncore C-box 6 perfmon local box wide control.\r | |
4261 | \r | |
4262 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL (0x00000DC4)\r | |
4263 | @param EAX Lower 32-bits of MSR value.\r | |
4264 | @param EDX Upper 32-bits of MSR value.\r | |
4265 | \r | |
4266 | <b>Example usage</b>\r | |
4267 | @code\r | |
4268 | UINT64 Msr;\r | |
4269 | \r | |
4270 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL);\r | |
4271 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL, Msr);\r | |
4272 | @endcode\r | |
367f5c9c | 4273 | @note MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL is defined as MSR_C6_PMON_BOX_CTL in SDM.\r |
dc5d621c | 4274 | **/\r |
2f88bd3a | 4275 | #define MSR_SANDY_BRIDGE_C6_PMON_BOX_CTL 0x00000DC4\r |
dc5d621c MK |
4276 | \r |
4277 | /**\r | |
4278 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 0.\r | |
4279 | \r | |
4280 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 (0x00000DD0)\r | |
4281 | @param EAX Lower 32-bits of MSR value.\r | |
4282 | @param EDX Upper 32-bits of MSR value.\r | |
4283 | \r | |
4284 | <b>Example usage</b>\r | |
4285 | @code\r | |
4286 | UINT64 Msr;\r | |
4287 | \r | |
4288 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0);\r | |
4289 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0, Msr);\r | |
4290 | @endcode\r | |
367f5c9c | 4291 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 is defined as MSR_C6_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 4292 | **/\r |
2f88bd3a | 4293 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL0 0x00000DD0\r |
dc5d621c MK |
4294 | \r |
4295 | /**\r | |
4296 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 1.\r | |
4297 | \r | |
4298 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 (0x00000DD1)\r | |
4299 | @param EAX Lower 32-bits of MSR value.\r | |
4300 | @param EDX Upper 32-bits of MSR value.\r | |
4301 | \r | |
4302 | <b>Example usage</b>\r | |
4303 | @code\r | |
4304 | UINT64 Msr;\r | |
4305 | \r | |
4306 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1);\r | |
4307 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1, Msr);\r | |
4308 | @endcode\r | |
367f5c9c | 4309 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 is defined as MSR_C6_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 4310 | **/\r |
2f88bd3a | 4311 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL1 0x00000DD1\r |
dc5d621c MK |
4312 | \r |
4313 | /**\r | |
4314 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 2.\r | |
4315 | \r | |
4316 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 (0x00000DD2)\r | |
4317 | @param EAX Lower 32-bits of MSR value.\r | |
4318 | @param EDX Upper 32-bits of MSR value.\r | |
4319 | \r | |
4320 | <b>Example usage</b>\r | |
4321 | @code\r | |
4322 | UINT64 Msr;\r | |
4323 | \r | |
4324 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2);\r | |
4325 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2, Msr);\r | |
4326 | @endcode\r | |
367f5c9c | 4327 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 is defined as MSR_C6_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 4328 | **/\r |
2f88bd3a | 4329 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL2 0x00000DD2\r |
dc5d621c MK |
4330 | \r |
4331 | /**\r | |
4332 | Package. Uncore C-box 6 perfmon event select for C-box 6 counter 3.\r | |
4333 | \r | |
4334 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 (0x00000DD3)\r | |
4335 | @param EAX Lower 32-bits of MSR value.\r | |
4336 | @param EDX Upper 32-bits of MSR value.\r | |
4337 | \r | |
4338 | <b>Example usage</b>\r | |
4339 | @code\r | |
4340 | UINT64 Msr;\r | |
4341 | \r | |
4342 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3);\r | |
4343 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3, Msr);\r | |
4344 | @endcode\r | |
367f5c9c | 4345 | @note MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 is defined as MSR_C6_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 4346 | **/\r |
2f88bd3a | 4347 | #define MSR_SANDY_BRIDGE_C6_PMON_EVNTSEL3 0x00000DD3\r |
dc5d621c MK |
4348 | \r |
4349 | /**\r | |
4350 | Package. Uncore C-box 6 perfmon box wide filter.\r | |
4351 | \r | |
4352 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER (0x00000DD4)\r | |
4353 | @param EAX Lower 32-bits of MSR value.\r | |
4354 | @param EDX Upper 32-bits of MSR value.\r | |
4355 | \r | |
4356 | <b>Example usage</b>\r | |
4357 | @code\r | |
4358 | UINT64 Msr;\r | |
4359 | \r | |
4360 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER);\r | |
4361 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER, Msr);\r | |
4362 | @endcode\r | |
367f5c9c | 4363 | @note MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER is defined as MSR_C6_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 4364 | **/\r |
2f88bd3a | 4365 | #define MSR_SANDY_BRIDGE_C6_PMON_BOX_FILTER 0x00000DD4\r |
dc5d621c MK |
4366 | \r |
4367 | /**\r | |
4368 | Package. Uncore C-box 6 perfmon counter 0.\r | |
4369 | \r | |
4370 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR0 (0x00000DD6)\r | |
4371 | @param EAX Lower 32-bits of MSR value.\r | |
4372 | @param EDX Upper 32-bits of MSR value.\r | |
4373 | \r | |
4374 | <b>Example usage</b>\r | |
4375 | @code\r | |
4376 | UINT64 Msr;\r | |
4377 | \r | |
4378 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0);\r | |
4379 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR0, Msr);\r | |
4380 | @endcode\r | |
367f5c9c | 4381 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR0 is defined as MSR_C6_PMON_CTR0 in SDM.\r |
dc5d621c | 4382 | **/\r |
2f88bd3a | 4383 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR0 0x00000DD6\r |
dc5d621c MK |
4384 | \r |
4385 | /**\r | |
4386 | Package. Uncore C-box 6 perfmon counter 1.\r | |
4387 | \r | |
4388 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR1 (0x00000DD7)\r | |
4389 | @param EAX Lower 32-bits of MSR value.\r | |
4390 | @param EDX Upper 32-bits of MSR value.\r | |
4391 | \r | |
4392 | <b>Example usage</b>\r | |
4393 | @code\r | |
4394 | UINT64 Msr;\r | |
4395 | \r | |
4396 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1);\r | |
4397 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR1, Msr);\r | |
4398 | @endcode\r | |
367f5c9c | 4399 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR1 is defined as MSR_C6_PMON_CTR1 in SDM.\r |
dc5d621c | 4400 | **/\r |
2f88bd3a | 4401 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR1 0x00000DD7\r |
dc5d621c MK |
4402 | \r |
4403 | /**\r | |
4404 | Package. Uncore C-box 6 perfmon counter 2.\r | |
4405 | \r | |
4406 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR2 (0x00000DD8)\r | |
4407 | @param EAX Lower 32-bits of MSR value.\r | |
4408 | @param EDX Upper 32-bits of MSR value.\r | |
4409 | \r | |
4410 | <b>Example usage</b>\r | |
4411 | @code\r | |
4412 | UINT64 Msr;\r | |
4413 | \r | |
4414 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2);\r | |
4415 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR2, Msr);\r | |
4416 | @endcode\r | |
367f5c9c | 4417 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR2 is defined as MSR_C6_PMON_CTR2 in SDM.\r |
dc5d621c | 4418 | **/\r |
2f88bd3a | 4419 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR2 0x00000DD8\r |
dc5d621c MK |
4420 | \r |
4421 | /**\r | |
4422 | Package. Uncore C-box 6 perfmon counter 3.\r | |
4423 | \r | |
4424 | @param ECX MSR_SANDY_BRIDGE_C6_PMON_CTR3 (0x00000DD9)\r | |
4425 | @param EAX Lower 32-bits of MSR value.\r | |
4426 | @param EDX Upper 32-bits of MSR value.\r | |
4427 | \r | |
4428 | <b>Example usage</b>\r | |
4429 | @code\r | |
4430 | UINT64 Msr;\r | |
4431 | \r | |
4432 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3);\r | |
4433 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C6_PMON_CTR3, Msr);\r | |
4434 | @endcode\r | |
367f5c9c | 4435 | @note MSR_SANDY_BRIDGE_C6_PMON_CTR3 is defined as MSR_C6_PMON_CTR3 in SDM.\r |
dc5d621c | 4436 | **/\r |
2f88bd3a | 4437 | #define MSR_SANDY_BRIDGE_C6_PMON_CTR3 0x00000DD9\r |
dc5d621c MK |
4438 | \r |
4439 | /**\r | |
4440 | Package. Uncore C-box 7 perfmon local box wide control.\r | |
4441 | \r | |
4442 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL (0x00000DE4)\r | |
4443 | @param EAX Lower 32-bits of MSR value.\r | |
4444 | @param EDX Upper 32-bits of MSR value.\r | |
4445 | \r | |
4446 | <b>Example usage</b>\r | |
4447 | @code\r | |
4448 | UINT64 Msr;\r | |
4449 | \r | |
4450 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL);\r | |
4451 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL, Msr);\r | |
4452 | @endcode\r | |
367f5c9c | 4453 | @note MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL is defined as MSR_C7_PMON_BOX_CTL in SDM.\r |
dc5d621c | 4454 | **/\r |
2f88bd3a | 4455 | #define MSR_SANDY_BRIDGE_C7_PMON_BOX_CTL 0x00000DE4\r |
dc5d621c MK |
4456 | \r |
4457 | /**\r | |
4458 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 0.\r | |
4459 | \r | |
4460 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 (0x00000DF0)\r | |
4461 | @param EAX Lower 32-bits of MSR value.\r | |
4462 | @param EDX Upper 32-bits of MSR value.\r | |
4463 | \r | |
4464 | <b>Example usage</b>\r | |
4465 | @code\r | |
4466 | UINT64 Msr;\r | |
4467 | \r | |
4468 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0);\r | |
4469 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0, Msr);\r | |
4470 | @endcode\r | |
367f5c9c | 4471 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 is defined as MSR_C7_PMON_EVNTSEL0 in SDM.\r |
dc5d621c | 4472 | **/\r |
2f88bd3a | 4473 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL0 0x00000DF0\r |
dc5d621c MK |
4474 | \r |
4475 | /**\r | |
4476 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 1.\r | |
4477 | \r | |
4478 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 (0x00000DF1)\r | |
4479 | @param EAX Lower 32-bits of MSR value.\r | |
4480 | @param EDX Upper 32-bits of MSR value.\r | |
4481 | \r | |
4482 | <b>Example usage</b>\r | |
4483 | @code\r | |
4484 | UINT64 Msr;\r | |
4485 | \r | |
4486 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1);\r | |
4487 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1, Msr);\r | |
4488 | @endcode\r | |
367f5c9c | 4489 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 is defined as MSR_C7_PMON_EVNTSEL1 in SDM.\r |
dc5d621c | 4490 | **/\r |
2f88bd3a | 4491 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL1 0x00000DF1\r |
dc5d621c MK |
4492 | \r |
4493 | /**\r | |
4494 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 2.\r | |
4495 | \r | |
4496 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 (0x00000DF2)\r | |
4497 | @param EAX Lower 32-bits of MSR value.\r | |
4498 | @param EDX Upper 32-bits of MSR value.\r | |
4499 | \r | |
4500 | <b>Example usage</b>\r | |
4501 | @code\r | |
4502 | UINT64 Msr;\r | |
4503 | \r | |
4504 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2);\r | |
4505 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2, Msr);\r | |
4506 | @endcode\r | |
367f5c9c | 4507 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 is defined as MSR_C7_PMON_EVNTSEL2 in SDM.\r |
dc5d621c | 4508 | **/\r |
2f88bd3a | 4509 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL2 0x00000DF2\r |
dc5d621c MK |
4510 | \r |
4511 | /**\r | |
4512 | Package. Uncore C-box 7 perfmon event select for C-box 7 counter 3.\r | |
4513 | \r | |
4514 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 (0x00000DF3)\r | |
4515 | @param EAX Lower 32-bits of MSR value.\r | |
4516 | @param EDX Upper 32-bits of MSR value.\r | |
4517 | \r | |
4518 | <b>Example usage</b>\r | |
4519 | @code\r | |
4520 | UINT64 Msr;\r | |
4521 | \r | |
4522 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3);\r | |
4523 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3, Msr);\r | |
4524 | @endcode\r | |
367f5c9c | 4525 | @note MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 is defined as MSR_C7_PMON_EVNTSEL3 in SDM.\r |
dc5d621c | 4526 | **/\r |
2f88bd3a | 4527 | #define MSR_SANDY_BRIDGE_C7_PMON_EVNTSEL3 0x00000DF3\r |
dc5d621c MK |
4528 | \r |
4529 | /**\r | |
4530 | Package. Uncore C-box 7 perfmon box wide filter.\r | |
4531 | \r | |
4532 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER (0x00000DF4)\r | |
4533 | @param EAX Lower 32-bits of MSR value.\r | |
4534 | @param EDX Upper 32-bits of MSR value.\r | |
4535 | \r | |
4536 | <b>Example usage</b>\r | |
4537 | @code\r | |
4538 | UINT64 Msr;\r | |
4539 | \r | |
4540 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER);\r | |
4541 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER, Msr);\r | |
4542 | @endcode\r | |
367f5c9c | 4543 | @note MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER is defined as MSR_C7_PMON_BOX_FILTER in SDM.\r |
dc5d621c | 4544 | **/\r |
2f88bd3a | 4545 | #define MSR_SANDY_BRIDGE_C7_PMON_BOX_FILTER 0x00000DF4\r |
dc5d621c MK |
4546 | \r |
4547 | /**\r | |
4548 | Package. Uncore C-box 7 perfmon counter 0.\r | |
4549 | \r | |
4550 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR0 (0x00000DF6)\r | |
4551 | @param EAX Lower 32-bits of MSR value.\r | |
4552 | @param EDX Upper 32-bits of MSR value.\r | |
4553 | \r | |
4554 | <b>Example usage</b>\r | |
4555 | @code\r | |
4556 | UINT64 Msr;\r | |
4557 | \r | |
4558 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0);\r | |
4559 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR0, Msr);\r | |
4560 | @endcode\r | |
367f5c9c | 4561 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR0 is defined as MSR_C7_PMON_CTR0 in SDM.\r |
dc5d621c | 4562 | **/\r |
2f88bd3a | 4563 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR0 0x00000DF6\r |
dc5d621c MK |
4564 | \r |
4565 | /**\r | |
4566 | Package. Uncore C-box 7 perfmon counter 1.\r | |
4567 | \r | |
4568 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR1 (0x00000DF7)\r | |
4569 | @param EAX Lower 32-bits of MSR value.\r | |
4570 | @param EDX Upper 32-bits of MSR value.\r | |
4571 | \r | |
4572 | <b>Example usage</b>\r | |
4573 | @code\r | |
4574 | UINT64 Msr;\r | |
4575 | \r | |
4576 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1);\r | |
4577 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR1, Msr);\r | |
4578 | @endcode\r | |
367f5c9c | 4579 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR1 is defined as MSR_C7_PMON_CTR1 in SDM.\r |
dc5d621c | 4580 | **/\r |
2f88bd3a | 4581 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR1 0x00000DF7\r |
dc5d621c MK |
4582 | \r |
4583 | /**\r | |
4584 | Package. Uncore C-box 7 perfmon counter 2.\r | |
4585 | \r | |
4586 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR2 (0x00000DF8)\r | |
4587 | @param EAX Lower 32-bits of MSR value.\r | |
4588 | @param EDX Upper 32-bits of MSR value.\r | |
4589 | \r | |
4590 | <b>Example usage</b>\r | |
4591 | @code\r | |
4592 | UINT64 Msr;\r | |
4593 | \r | |
4594 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2);\r | |
4595 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR2, Msr);\r | |
4596 | @endcode\r | |
367f5c9c | 4597 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR2 is defined as MSR_C7_PMON_CTR2 in SDM.\r |
dc5d621c | 4598 | **/\r |
2f88bd3a | 4599 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR2 0x00000DF8\r |
dc5d621c MK |
4600 | \r |
4601 | /**\r | |
4602 | Package. Uncore C-box 7 perfmon counter 3.\r | |
4603 | \r | |
4604 | @param ECX MSR_SANDY_BRIDGE_C7_PMON_CTR3 (0x00000DF9)\r | |
4605 | @param EAX Lower 32-bits of MSR value.\r | |
4606 | @param EDX Upper 32-bits of MSR value.\r | |
4607 | \r | |
4608 | <b>Example usage</b>\r | |
4609 | @code\r | |
4610 | UINT64 Msr;\r | |
4611 | \r | |
4612 | Msr = AsmReadMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3);\r | |
4613 | AsmWriteMsr64 (MSR_SANDY_BRIDGE_C7_PMON_CTR3, Msr);\r | |
4614 | @endcode\r | |
367f5c9c | 4615 | @note MSR_SANDY_BRIDGE_C7_PMON_CTR3 is defined as MSR_C7_PMON_CTR3 in SDM.\r |
dc5d621c | 4616 | **/\r |
2f88bd3a | 4617 | #define MSR_SANDY_BRIDGE_C7_PMON_CTR3 0x00000DF9\r |
dc5d621c MK |
4618 | \r |
4619 | #endif\r |