[mirror_edk2.git] / MdePkg / Include / Register / Intel / Msr / Xeon5600Msr.h

/** @file\r
  MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
\r
  Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
  are provided for MSRs that contain one or more bit fields.  If the MSR value\r
  returned is a single 32-bit or 64-bit value, then a data structure is not\r
  provided for that MSR.\r
\r
  Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
  @par Specification Reference:\r
  Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
  May 2018, Volume 4: Model-Specific-Registers (MSR)\r
\r
**/\r
\r
#ifndef __XEON_5600_MSR_H__\r
#define __XEON_5600_MSR_H__\r
\r
#include <Register/Intel/ArchitecturalMsr.h>\r
\r
/**\r
  Is Intel(R) Xeon(R) Processor Series 5600?\r
\r
  @param   DisplayFamily  Display Family ID\r
  @param   DisplayModel   Display Model ID\r
\r
  @retval  TRUE   Yes, it is.\r
  @retval  FALSE  No, it isn't.\r
**/\r
#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
  (DisplayFamily == 0x06 && \\r
   (                        \\r
    DisplayModel == 0x25 || \\r
    DisplayModel == 0x2C    \\r
    )                       \\r
   )\r
\r
/**\r
  Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
  handler to handle unsuccessful read of this MSR.\r
\r
  @param  ECX  MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_5600_FEATURE_CONFIG_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
  AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
  @endcode\r
  @note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
**/\r
#define MSR_XEON_5600_FEATURE_CONFIG  0x0000013C\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 1:0] AES Configuration (RW-L)  Upon a successful read of this\r
    /// MSR, the configuration of AES instruction set availability is as\r
    /// follows: 11b: AES instructions are not available until next RESET.\r
    /// otherwise, AES instructions are available. Note, AES instruction set\r
    /// is not available if read is unsuccessful. If the configuration is not\r
    /// 01b, AES instruction can be mis-configured if a privileged agent\r
    /// unintentionally writes 11b.\r
    ///\r
    UINT32    AESConfiguration : 2;\r
    UINT32    Reserved1        : 30;\r
    UINT32    Reserved2        : 32;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 32-bit value\r
  ///\r
  UINT32    Uint32;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
\r
/**\r
  Thread. Offcore Response Event Select Register (R/W).\r
\r
  @param  ECX  MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
  AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
  @endcode\r
  @note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
**/\r
#define MSR_XEON_5600_OFFCORE_RSP_1  0x000001A7\r
\r
/**\r
  Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
  RW if MSR_PLATFORM_INFO.[28] = 1.\r
\r
  @param  ECX  MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
  @param  EAX  Lower 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
  @param  EDX  Upper 32-bits of MSR value.\r
               Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
\r
  <b>Example usage</b>\r
  @code\r
  MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER  Msr;\r
\r
  Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
  @endcode\r
  @note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
**/\r
#define MSR_XEON_5600_TURBO_RATIO_LIMIT  0x000001AD\r
\r
/**\r
  MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
**/\r
typedef union {\r
  ///\r
  /// Individual bit fields\r
  ///\r
  struct {\r
    ///\r
    /// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
    /// limit of 1 core active.\r
    ///\r
    UINT32    Maximum1C : 8;\r
    ///\r
    /// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
    /// limit of 2 core active.\r
    ///\r
    UINT32    Maximum2C : 8;\r
    ///\r
    /// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
    /// limit of 3 core active.\r
    ///\r
    UINT32    Maximum3C : 8;\r
    ///\r
    /// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
    /// limit of 4 core active.\r
    ///\r
    UINT32    Maximum4C : 8;\r
    ///\r
    /// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
    /// limit of 5 core active.\r
    ///\r
    UINT32    Maximum5C : 8;\r
    ///\r
    /// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
    /// limit of 6 core active.\r
    ///\r
    UINT32    Maximum6C : 8;\r
    UINT32    Reserved  : 16;\r
  } Bits;\r
  ///\r
  /// All bit fields as a 64-bit value\r
  ///\r
  UINT64    Uint64;\r
} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
\r
/**\r
  Package. See Table 2-2.\r
\r
  @param  ECX  MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
  @param  EAX  Lower 32-bits of MSR value.\r
  @param  EDX  Upper 32-bits of MSR value.\r
\r
  <b>Example usage</b>\r
  @code\r
  UINT64  Msr;\r
\r
  Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
  AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
  @endcode\r
  @note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
**/\r
#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS  0x000001B0\r
\r
#endif\r
Commit	Line	Data
c5d7b07a MK	1	/** @file\r
	2	MSR Definitions for Intel(R) Xeon(R) Processor Series 5600.\r
	3	\r
	4	Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
	5	are provided for MSRs that contain one or more bit fields. If the MSR value\r
	6	returned is a single 32-bit or 64-bit value, then a data structure is not\r
	7	provided for that MSR.\r
	8	\r
e057908f	9	Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697	10	SPDX-License-Identifier: BSD-2-Clause-Patent\r
c5d7b07a MK	11	\r
c5d7b07a MK	12	@par Specification Reference:\r
ba1a2d11 ED	13	Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
ba1a2d11 ED	14	May 2018, Volume 4: Model-Specific-Registers (MSR)\r
c5d7b07a MK	15	\r
	16	**/\r
	17	\r
	18	#ifndef __XEON_5600_MSR_H__\r
	19	#define __XEON_5600_MSR_H__\r
	20	\r
e057908f	21	#include <Register/Intel/ArchitecturalMsr.h>\r
c5d7b07a	22	\r
f4c982bf JF	23	/**\r
	24	Is Intel(R) Xeon(R) Processor Series 5600?\r
	25	\r
	26	@param DisplayFamily Display Family ID\r
	27	@param DisplayModel Display Model ID\r
	28	\r
	29	@retval TRUE Yes, it is.\r
	30	@retval FALSE No, it isn't.\r
	31	**/\r
	32	#define IS_XEON_5600_PROCESSOR(DisplayFamily, DisplayModel) \\r
	33	(DisplayFamily == 0x06 && \\r
	34	( \\r
	35	DisplayModel == 0x25 \|\| \\r
	36	DisplayModel == 0x2C \\r
	37	) \\r
	38	)\r
	39	\r
c5d7b07a MK	40	/**\r
	41	Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r
	42	handler to handle unsuccessful read of this MSR.\r
	43	\r
	44	@param ECX MSR_XEON_5600_FEATURE_CONFIG (0x0000013C)\r
	45	@param EAX Lower 32-bits of MSR value.\r
	46	Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
	47	@param EDX Upper 32-bits of MSR value.\r
	48	Described by the type MSR_XEON_5600_FEATURE_CONFIG_REGISTER.\r
	49	\r
	50	<b>Example usage</b>\r
	51	@code\r
	52	MSR_XEON_5600_FEATURE_CONFIG_REGISTER Msr;\r
	53	\r
	54	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_FEATURE_CONFIG);\r
	55	AsmWriteMsr64 (MSR_XEON_5600_FEATURE_CONFIG, Msr.Uint64);\r
	56	@endcode\r
eed57645	57	@note MSR_XEON_5600_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r
c5d7b07a	58	**/\r
2f88bd3a	59	#define MSR_XEON_5600_FEATURE_CONFIG 0x0000013C\r
c5d7b07a MK	60	\r
	61	/**\r
	62	MSR information returned for MSR index #MSR_XEON_5600_FEATURE_CONFIG\r
	63	**/\r
	64	typedef union {\r
	65	///\r
	66	/// Individual bit fields\r
	67	///\r
	68	struct {\r
	69	///\r
	70	/// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r
	71	/// MSR, the configuration of AES instruction set availability is as\r
	72	/// follows: 11b: AES instructions are not available until next RESET.\r
	73	/// otherwise, AES instructions are available. Note, AES instruction set\r
	74	/// is not available if read is unsuccessful. If the configuration is not\r
	75	/// 01b, AES instruction can be mis-configured if a privileged agent\r
	76	/// unintentionally writes 11b.\r
	77	///\r
2f88bd3a MK	78	UINT32 AESConfiguration : 2;\r
	79	UINT32 Reserved1 : 30;\r
	80	UINT32 Reserved2 : 32;\r
c5d7b07a MK	81	} Bits;\r
	82	///\r
	83	/// All bit fields as a 32-bit value\r
	84	///\r
2f88bd3a	85	UINT32 Uint32;\r
c5d7b07a MK	86	///\r
	87	/// All bit fields as a 64-bit value\r
	88	///\r
2f88bd3a	89	UINT64 Uint64;\r
c5d7b07a MK	90	} MSR_XEON_5600_FEATURE_CONFIG_REGISTER;\r
c5d7b07a MK	91	\r
c5d7b07a MK	92	/**\r
	93	Thread. Offcore Response Event Select Register (R/W).\r
	94	\r
	95	@param ECX MSR_XEON_5600_OFFCORE_RSP_1 (0x000001A7)\r
	96	@param EAX Lower 32-bits of MSR value.\r
	97	@param EDX Upper 32-bits of MSR value.\r
	98	\r
	99	<b>Example usage</b>\r
	100	@code\r
	101	UINT64 Msr;\r
	102	\r
	103	Msr = AsmReadMsr64 (MSR_XEON_5600_OFFCORE_RSP_1);\r
	104	AsmWriteMsr64 (MSR_XEON_5600_OFFCORE_RSP_1, Msr);\r
	105	@endcode\r
eed57645	106	@note MSR_XEON_5600_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r
c5d7b07a	107	**/\r
2f88bd3a	108	#define MSR_XEON_5600_OFFCORE_RSP_1 0x000001A7\r
c5d7b07a MK	109	\r
	110	/**\r
	111	Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
	112	RW if MSR_PLATFORM_INFO.[28] = 1.\r
	113	\r
	114	@param ECX MSR_XEON_5600_TURBO_RATIO_LIMIT (0x000001AD)\r
	115	@param EAX Lower 32-bits of MSR value.\r
	116	Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
	117	@param EDX Upper 32-bits of MSR value.\r
	118	Described by the type MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER.\r
	119	\r
	120	<b>Example usage</b>\r
	121	@code\r
	122	MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER Msr;\r
	123	\r
	124	Msr.Uint64 = AsmReadMsr64 (MSR_XEON_5600_TURBO_RATIO_LIMIT);\r
	125	@endcode\r
eed57645	126	@note MSR_XEON_5600_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
c5d7b07a	127	**/\r
2f88bd3a	128	#define MSR_XEON_5600_TURBO_RATIO_LIMIT 0x000001AD\r
c5d7b07a MK	129	\r
	130	/**\r
	131	MSR information returned for MSR index #MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER\r
	132	**/\r
	133	typedef union {\r
	134	///\r
	135	/// Individual bit fields\r
	136	///\r
	137	struct {\r
	138	///\r
	139	/// [Bits 7:0] Package. Maximum Ratio Limit for 1C Maximum turbo ratio\r
	140	/// limit of 1 core active.\r
	141	///\r
2f88bd3a	142	UINT32 Maximum1C : 8;\r
c5d7b07a MK	143	///\r
	144	/// [Bits 15:8] Package. Maximum Ratio Limit for 2C Maximum turbo ratio\r
	145	/// limit of 2 core active.\r
	146	///\r
2f88bd3a	147	UINT32 Maximum2C : 8;\r
c5d7b07a MK	148	///\r
	149	/// [Bits 23:16] Package. Maximum Ratio Limit for 3C Maximum turbo ratio\r
	150	/// limit of 3 core active.\r
	151	///\r
2f88bd3a	152	UINT32 Maximum3C : 8;\r
c5d7b07a MK	153	///\r
	154	/// [Bits 31:24] Package. Maximum Ratio Limit for 4C Maximum turbo ratio\r
	155	/// limit of 4 core active.\r
	156	///\r
2f88bd3a	157	UINT32 Maximum4C : 8;\r
c5d7b07a MK	158	///\r
	159	/// [Bits 39:32] Package. Maximum Ratio Limit for 5C Maximum turbo ratio\r
	160	/// limit of 5 core active.\r
	161	///\r
2f88bd3a	162	UINT32 Maximum5C : 8;\r
c5d7b07a MK	163	///\r
	164	/// [Bits 47:40] Package. Maximum Ratio Limit for 6C Maximum turbo ratio\r
	165	/// limit of 6 core active.\r
	166	///\r
2f88bd3a MK	167	UINT32 Maximum6C : 8;\r
2f88bd3a MK	168	UINT32 Reserved : 16;\r
c5d7b07a MK	169	} Bits;\r
	170	///\r
	171	/// All bit fields as a 64-bit value\r
	172	///\r
2f88bd3a	173	UINT64 Uint64;\r
c5d7b07a MK	174	} MSR_XEON_5600_TURBO_RATIO_LIMIT_REGISTER;\r
c5d7b07a MK	175	\r
c5d7b07a	176	/**\r
ba1a2d11	177	Package. See Table 2-2.\r
c5d7b07a MK	178	\r
	179	@param ECX MSR_XEON_5600_IA32_ENERGY_PERF_BIAS (0x000001B0)\r
	180	@param EAX Lower 32-bits of MSR value.\r
	181	@param EDX Upper 32-bits of MSR value.\r
	182	\r
	183	<b>Example usage</b>\r
	184	@code\r
	185	UINT64 Msr;\r
	186	\r
	187	Msr = AsmReadMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS);\r
	188	AsmWriteMsr64 (MSR_XEON_5600_IA32_ENERGY_PERF_BIAS, Msr);\r
	189	@endcode\r
eed57645	190	@note MSR_XEON_5600_IA32_ENERGY_PERF_BIAS is defined as IA32_ENERGY_PERF_BIAS in SDM.\r
c5d7b07a	191	**/\r
2f88bd3a	192	#define MSR_XEON_5600_IA32_ENERGY_PERF_BIAS 0x000001B0\r
c5d7b07a MK	193	\r
c5d7b07a MK	194	#endif\r