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54307cea
MK		 1/** @file\r
2 MSR Definitions for Intel(R) Xeon(R) Processor D product Family.\r
3\r
4 Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r
5 are provided for MSRs that contain one or more bit fields. If the MSR value\r
6 returned is a single 32-bit or 64-bit value, then a data structure is not\r
7 provided for that MSR.\r
8\r
e057908f 9 Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r
0acd8697 10 SPDX-License-Identifier: BSD-2-Clause-Patent\r
54307cea
MK		 11\r
12 @par Specification Reference:\r
ba1a2d11
ED		 13 Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r
14 May 2018, Volume 4: Model-Specific-Registers (MSR)\r
54307cea
MK		 15\r
16**/\r
17\r
18#ifndef __XEON_D_MSR_H__\r
19#define __XEON_D_MSR_H__\r
20\r
e057908f 21#include <Register/Intel/ArchitecturalMsr.h>\r
54307cea 22\r
f4c982bf
JF		 23/**\r
24 Is Intel(R) Xeon(R) Processor D product Family?\r
25\r
26 @param DisplayFamily Display Family ID\r
27 @param DisplayModel Display Model ID\r
28\r
29 @retval TRUE Yes, it is.\r
30 @retval FALSE No, it isn't.\r
31**/\r
32#define IS_XEON_D_PROCESSOR(DisplayFamily, DisplayModel) \\r
33 (DisplayFamily == 0x06 && \\r
34 ( \\r
35 DisplayModel == 0x4F || \\r
36 DisplayModel == 0x56 \\r
37 ) \\r
38 )\r
39\r
54307cea
MK		 40/**\r
41 Package. Protected Processor Inventory Number Enable Control (R/W).\r
42\r
43 @param ECX MSR_XEON_D_PPIN_CTL (0x0000004E)\r
44 @param EAX Lower 32-bits of MSR value.\r
45 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
46 @param EDX Upper 32-bits of MSR value.\r
47 Described by the type MSR_XEON_D_PPIN_CTL_REGISTER.\r
48\r
49 <b>Example usage</b>\r
50 @code\r
51 MSR_XEON_D_PPIN_CTL_REGISTER Msr;\r
52\r
53 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PPIN_CTL);\r
54 AsmWriteMsr64 (MSR_XEON_D_PPIN_CTL, Msr.Uint64);\r
55 @endcode\r
b6ae7578 56 @note MSR_XEON_D_PPIN_CTL is defined as MSR_PPIN_CTL in SDM.\r
54307cea 57**/\r
2f88bd3a 58#define MSR_XEON_D_PPIN_CTL 0x0000004E\r
54307cea
MK		 59\r
60/**\r
61 MSR information returned for MSR index #MSR_XEON_D_PPIN_CTL\r
62**/\r
63typedef union {\r
64 ///\r
65 /// Individual bit fields\r
66 ///\r
67 struct {\r
68 ///\r
ba1a2d11 69 /// [Bit 0] LockOut (R/WO) See Table 2-25.\r
54307cea 70 ///\r
2f88bd3a 71 UINT32 LockOut : 1;\r
54307cea 72 ///\r
ba1a2d11 73 /// [Bit 1] Enable_PPIN (R/W) See Table 2-25.\r
54307cea 74 ///\r
2f88bd3a
MK		 75 UINT32 Enable_PPIN : 1;\r
76 UINT32 Reserved1 : 30;\r
77 UINT32 Reserved2 : 32;\r
54307cea
MK		 78 } Bits;\r
79 ///\r
80 /// All bit fields as a 32-bit value\r
81 ///\r
2f88bd3a 82 UINT32 Uint32;\r
54307cea
MK		 83 ///\r
84 /// All bit fields as a 64-bit value\r
85 ///\r
2f88bd3a 86 UINT64 Uint64;\r
54307cea
MK		 87} MSR_XEON_D_PPIN_CTL_REGISTER;\r
88\r
54307cea
MK		 89/**\r
90 Package. Protected Processor Inventory Number (R/O). Protected Processor\r
ba1a2d11 91 Inventory Number (R/O) See Table 2-25.\r
54307cea
MK		 92\r
93 @param ECX MSR_XEON_D_PPIN (0x0000004F)\r
94 @param EAX Lower 32-bits of MSR value.\r
95 @param EDX Upper 32-bits of MSR value.\r
96\r
97 <b>Example usage</b>\r
98 @code\r
99 UINT64 Msr;\r
100\r
101 Msr = AsmReadMsr64 (MSR_XEON_D_PPIN);\r
102 @endcode\r
b6ae7578 103 @note MSR_XEON_D_PPIN is defined as MSR_PPIN in SDM.\r
54307cea 104**/\r
2f88bd3a 105#define MSR_XEON_D_PPIN 0x0000004F\r
54307cea
MK		 106\r
107/**\r
108 Package. See http://biosbits.org.\r
109\r
110 @param ECX MSR_XEON_D_PLATFORM_INFO (0x000000CE)\r
111 @param EAX Lower 32-bits of MSR value.\r
112 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
113 @param EDX Upper 32-bits of MSR value.\r
114 Described by the type MSR_XEON_D_PLATFORM_INFO_REGISTER.\r
115\r
116 <b>Example usage</b>\r
117 @code\r
118 MSR_XEON_D_PLATFORM_INFO_REGISTER Msr;\r
119\r
120 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PLATFORM_INFO);\r
121 AsmWriteMsr64 (MSR_XEON_D_PLATFORM_INFO, Msr.Uint64);\r
122 @endcode\r
b6ae7578 123 @note MSR_XEON_D_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r
54307cea 124**/\r
2f88bd3a 125#define MSR_XEON_D_PLATFORM_INFO 0x000000CE\r
54307cea
MK		 126\r
127/**\r
128 MSR information returned for MSR index #MSR_XEON_D_PLATFORM_INFO\r
129**/\r
130typedef union {\r
131 ///\r
132 /// Individual bit fields\r
133 ///\r
134 struct {\r
2f88bd3a 135 UINT32 Reserved1 : 8;\r
54307cea 136 ///\r
ba1a2d11 137 /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) See Table 2-25.\r
54307cea 138 ///\r
2f88bd3a
MK		 139 UINT32 MaximumNonTurboRatio : 8;\r
140 UINT32 Reserved2 : 7;\r
54307cea 141 ///\r
ba1a2d11 142 /// [Bit 23] Package. PPIN_CAP (R/O) See Table 2-25.\r
54307cea 143 ///\r
2f88bd3a
MK		 144 UINT32 PPIN_CAP : 1;\r
145 UINT32 Reserved3 : 4;\r
54307cea
MK		 146 ///\r
147 /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) See\r
ba1a2d11 148 /// Table 2-25.\r
54307cea 149 ///\r
2f88bd3a 150 UINT32 RatioLimit : 1;\r
54307cea
MK		 151 ///\r
152 /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) See\r
ba1a2d11 153 /// Table 2-25.\r
54307cea 154 ///\r
2f88bd3a 155 UINT32 TDPLimit : 1;\r
54307cea 156 ///\r
ba1a2d11 157 /// [Bit 30] Package. Programmable TJ OFFSET (R/O) See Table 2-25.\r
54307cea 158 ///\r
2f88bd3a
MK		 159 UINT32 TJOFFSET : 1;\r
160 UINT32 Reserved4 : 1;\r
161 UINT32 Reserved5 : 8;\r
54307cea 162 ///\r
ba1a2d11 163 /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) See Table 2-25.\r
54307cea 164 ///\r
2f88bd3a
MK		 165 UINT32 MaximumEfficiencyRatio : 8;\r
166 UINT32 Reserved6 : 16;\r
54307cea
MK		 167 } Bits;\r
168 ///\r
169 /// All bit fields as a 64-bit value\r
170 ///\r
2f88bd3a 171 UINT64 Uint64;\r
54307cea
MK		 172} MSR_XEON_D_PLATFORM_INFO_REGISTER;\r
173\r
54307cea
MK		 174/**\r
175 Core. C-State Configuration Control (R/W) Note: C-state values are processor\r
176 specific C-state code names, unrelated to MWAIT extension C-state parameters\r
177 or ACPI C-states. `See http://biosbits.org. <http://biosbits.org>`__.\r
178\r
179 @param ECX MSR_XEON_D_PKG_CST_CONFIG_CONTROL (0x000000E2)\r
180 @param EAX Lower 32-bits of MSR value.\r
181 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
182 @param EDX Upper 32-bits of MSR value.\r
183 Described by the type MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER.\r
184\r
185 <b>Example usage</b>\r
186 @code\r
187 MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r
188\r
189 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL);\r
190 AsmWriteMsr64 (MSR_XEON_D_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r
191 @endcode\r
b6ae7578 192 @note MSR_XEON_D_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r
54307cea 193**/\r
2f88bd3a 194#define MSR_XEON_D_PKG_CST_CONFIG_CONTROL 0x000000E2\r
54307cea
MK		 195\r
196/**\r
197 MSR information returned for MSR index #MSR_XEON_D_PKG_CST_CONFIG_CONTROL\r
198**/\r
199typedef union {\r
200 ///\r
201 /// Individual bit fields\r
202 ///\r
203 struct {\r
204 ///\r
205 /// [Bits 2:0] Package C-State Limit (R/W) Specifies the lowest\r
206 /// processor-specific C-state code name (consuming the least power) for\r
207 /// the package. The default is set as factory-configured package C-state\r
208 /// limit. The following C-state code name encodings are supported: 000b:\r
209 /// C0/C1 (no package C-state support) 001b: C2 010b: C6 (non-retention)\r
210 /// 011b: C6 (retention) 111b: No Package C state limits. All C states\r
211 /// supported by the processor are available.\r
212 ///\r
2f88bd3a
MK		 213 UINT32 Limit : 3;\r
214 UINT32 Reserved1 : 7;\r
54307cea
MK		 215 ///\r
216 /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r
217 ///\r
2f88bd3a
MK		 218 UINT32 IO_MWAIT : 1;\r
219 UINT32 Reserved2 : 4;\r
54307cea
MK		 220 ///\r
221 /// [Bit 15] CFG Lock (R/WO).\r
222 ///\r
2f88bd3a 223 UINT32 CFGLock : 1;\r
54307cea
MK		 224 ///\r
225 /// [Bit 16] Automatic C-State Conversion Enable (R/W) If 1, the processor\r
226 /// will convert HALT or MWAT(C1) to MWAIT(C6).\r
227 ///\r
2f88bd3a
MK		 228 UINT32 CStateConversion : 1;\r
229 UINT32 Reserved3 : 8;\r
54307cea
MK		 230 ///\r
231 /// [Bit 25] C3 State Auto Demotion Enable (R/W).\r
232 ///\r
2f88bd3a 233 UINT32 C3AutoDemotion : 1;\r
54307cea
MK		 234 ///\r
235 /// [Bit 26] C1 State Auto Demotion Enable (R/W).\r
236 ///\r
2f88bd3a 237 UINT32 C1AutoDemotion : 1;\r
54307cea
MK		 238 ///\r
239 /// [Bit 27] Enable C3 Undemotion (R/W).\r
240 ///\r
2f88bd3a 241 UINT32 C3Undemotion : 1;\r
54307cea
MK		 242 ///\r
243 /// [Bit 28] Enable C1 Undemotion (R/W).\r
244 ///\r
2f88bd3a 245 UINT32 C1Undemotion : 1;\r
54307cea
MK		 246 ///\r
247 /// [Bit 29] Package C State Demotion Enable (R/W).\r
248 ///\r
2f88bd3a 249 UINT32 CStateDemotion : 1;\r
54307cea
MK		 250 ///\r
251 /// [Bit 30] Package C State UnDemotion Enable (R/W).\r
252 ///\r
2f88bd3a
MK		 253 UINT32 CStateUndemotion : 1;\r
254 UINT32 Reserved4 : 1;\r
255 UINT32 Reserved5 : 32;\r
54307cea
MK		 256 } Bits;\r
257 ///\r
258 /// All bit fields as a 32-bit value\r
259 ///\r
2f88bd3a 260 UINT32 Uint32;\r
54307cea
MK		 261 ///\r
262 /// All bit fields as a 64-bit value\r
263 ///\r
2f88bd3a 264 UINT64 Uint64;\r
54307cea
MK		 265} MSR_XEON_D_PKG_CST_CONFIG_CONTROL_REGISTER;\r
266\r
54307cea
MK		 267/**\r
268 Thread. Global Machine Check Capability (R/O).\r
269\r
270 @param ECX MSR_XEON_D_IA32_MCG_CAP (0x00000179)\r
271 @param EAX Lower 32-bits of MSR value.\r
272 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
273 @param EDX Upper 32-bits of MSR value.\r
274 Described by the type MSR_XEON_D_IA32_MCG_CAP_REGISTER.\r
275\r
276 <b>Example usage</b>\r
277 @code\r
278 MSR_XEON_D_IA32_MCG_CAP_REGISTER Msr;\r
279\r
280 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_MCG_CAP);\r
281 @endcode\r
b6ae7578 282 @note MSR_XEON_D_IA32_MCG_CAP is defined as IA32_MCG_CAP in SDM.\r
54307cea 283**/\r
2f88bd3a 284#define MSR_XEON_D_IA32_MCG_CAP 0x00000179\r
54307cea
MK		 285\r
286/**\r
287 MSR information returned for MSR index #MSR_XEON_D_IA32_MCG_CAP\r
288**/\r
289typedef union {\r
290 ///\r
291 /// Individual bit fields\r
292 ///\r
293 struct {\r
294 ///\r
295 /// [Bits 7:0] Count.\r
296 ///\r
2f88bd3a 297 UINT32 Count : 8;\r
54307cea
MK		 298 ///\r
299 /// [Bit 8] MCG_CTL_P.\r
300 ///\r
2f88bd3a 301 UINT32 MCG_CTL_P : 1;\r
54307cea
MK		 302 ///\r
303 /// [Bit 9] MCG_EXT_P.\r
304 ///\r
2f88bd3a 305 UINT32 MCG_EXT_P : 1;\r
54307cea
MK		 306 ///\r
307 /// [Bit 10] MCP_CMCI_P.\r
308 ///\r
2f88bd3a 309 UINT32 MCP_CMCI_P : 1;\r
54307cea
MK		 310 ///\r
311 /// [Bit 11] MCG_TES_P.\r
312 ///\r
2f88bd3a
MK		 313 UINT32 MCG_TES_P : 1;\r
314 UINT32 Reserved1 : 4;\r
54307cea
MK		 315 ///\r
316 /// [Bits 23:16] MCG_EXT_CNT.\r
317 ///\r
2f88bd3a 318 UINT32 MCG_EXT_CNT : 8;\r
54307cea
MK		 319 ///\r
320 /// [Bit 24] MCG_SER_P.\r
321 ///\r
2f88bd3a 322 UINT32 MCG_SER_P : 1;\r
54307cea
MK		 323 ///\r
324 /// [Bit 25] MCG_EM_P.\r
325 ///\r
2f88bd3a 326 UINT32 MCG_EM_P : 1;\r
54307cea
MK		 327 ///\r
328 /// [Bit 26] MCG_ELOG_P.\r
329 ///\r
2f88bd3a
MK		 330 UINT32 MCG_ELOG_P : 1;\r
331 UINT32 Reserved2 : 5;\r
332 UINT32 Reserved3 : 32;\r
54307cea
MK		 333 } Bits;\r
334 ///\r
335 /// All bit fields as a 32-bit value\r
336 ///\r
2f88bd3a 337 UINT32 Uint32;\r
54307cea
MK		 338 ///\r
339 /// All bit fields as a 64-bit value\r
340 ///\r
2f88bd3a 341 UINT64 Uint64;\r
54307cea
MK		 342} MSR_XEON_D_IA32_MCG_CAP_REGISTER;\r
343\r
54307cea
MK		 344/**\r
345 THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r
346 Enhancement. Accessible only while in SMM.\r
347\r
348 @param ECX MSR_XEON_D_SMM_MCA_CAP (0x0000017D)\r
349 @param EAX Lower 32-bits of MSR value.\r
350 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
351 @param EDX Upper 32-bits of MSR value.\r
352 Described by the type MSR_XEON_D_SMM_MCA_CAP_REGISTER.\r
353\r
354 <b>Example usage</b>\r
355 @code\r
356 MSR_XEON_D_SMM_MCA_CAP_REGISTER Msr;\r
357\r
358 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_SMM_MCA_CAP);\r
359 AsmWriteMsr64 (MSR_XEON_D_SMM_MCA_CAP, Msr.Uint64);\r
360 @endcode\r
b6ae7578 361 @note MSR_XEON_D_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r
54307cea 362**/\r
2f88bd3a 363#define MSR_XEON_D_SMM_MCA_CAP 0x0000017D\r
54307cea
MK		 364\r
365/**\r
366 MSR information returned for MSR index #MSR_XEON_D_SMM_MCA_CAP\r
367**/\r
368typedef union {\r
369 ///\r
370 /// Individual bit fields\r
371 ///\r
372 struct {\r
2f88bd3a
MK		 373 UINT32 Reserved1 : 32;\r
374 UINT32 Reserved2 : 26;\r
54307cea
MK		 375 ///\r
376 /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r
377 /// SMM code access restriction is supported and a host-space interface\r
378 /// available to SMM handler.\r
379 ///\r
2f88bd3a 380 UINT32 SMM_Code_Access_Chk : 1;\r
54307cea
MK		 381 ///\r
382 /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r
383 /// SMM long flow indicator is supported and a host-space interface\r
384 /// available to SMM handler.\r
385 ///\r
2f88bd3a
MK		 386 UINT32 Long_Flow_Indication : 1;\r
387 UINT32 Reserved3 : 4;\r
54307cea
MK		 388 } Bits;\r
389 ///\r
390 /// All bit fields as a 64-bit value\r
391 ///\r
2f88bd3a 392 UINT64 Uint64;\r
54307cea
MK		 393} MSR_XEON_D_SMM_MCA_CAP_REGISTER;\r
394\r
54307cea
MK		 395/**\r
396 Package.\r
397\r
398 @param ECX MSR_XEON_D_TEMPERATURE_TARGET (0x000001A2)\r
399 @param EAX Lower 32-bits of MSR value.\r
400 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
401 @param EDX Upper 32-bits of MSR value.\r
402 Described by the type MSR_XEON_D_TEMPERATURE_TARGET_REGISTER.\r
403\r
404 <b>Example usage</b>\r
405 @code\r
406 MSR_XEON_D_TEMPERATURE_TARGET_REGISTER Msr;\r
407\r
408 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TEMPERATURE_TARGET);\r
409 AsmWriteMsr64 (MSR_XEON_D_TEMPERATURE_TARGET, Msr.Uint64);\r
410 @endcode\r
b6ae7578 411 @note MSR_XEON_D_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r
54307cea 412**/\r
2f88bd3a 413#define MSR_XEON_D_TEMPERATURE_TARGET 0x000001A2\r
54307cea
MK		 414\r
415/**\r
416 MSR information returned for MSR index #MSR_XEON_D_TEMPERATURE_TARGET\r
417**/\r
418typedef union {\r
419 ///\r
420 /// Individual bit fields\r
421 ///\r
422 struct {\r
2f88bd3a 423 UINT32 Reserved1 : 16;\r
54307cea 424 ///\r
ba1a2d11 425 /// [Bits 23:16] Temperature Target (RO) See Table 2-25.\r
54307cea 426 ///\r
2f88bd3a 427 UINT32 TemperatureTarget : 8;\r
54307cea 428 ///\r
ba1a2d11 429 /// [Bits 27:24] TCC Activation Offset (R/W) See Table 2-25.\r
54307cea 430 ///\r
2f88bd3a
MK		 431 UINT32 TCCActivationOffset : 4;\r
432 UINT32 Reserved2 : 4;\r
433 UINT32 Reserved3 : 32;\r
54307cea
MK		 434 } Bits;\r
435 ///\r
436 /// All bit fields as a 32-bit value\r
437 ///\r
2f88bd3a 438 UINT32 Uint32;\r
54307cea
MK		 439 ///\r
440 /// All bit fields as a 64-bit value\r
441 ///\r
2f88bd3a 442 UINT64 Uint64;\r
54307cea
MK		 443} MSR_XEON_D_TEMPERATURE_TARGET_REGISTER;\r
444\r
54307cea
MK		 445/**\r
446 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
447 RW if MSR_PLATFORM_INFO.[28] = 1.\r
448\r
449 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT (0x000001AD)\r
450 @param EAX Lower 32-bits of MSR value.\r
451 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
452 @param EDX Upper 32-bits of MSR value.\r
453 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER.\r
454\r
455 <b>Example usage</b>\r
456 @code\r
457 MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER Msr;\r
458\r
459 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT);\r
460 @endcode\r
b6ae7578 461 @note MSR_XEON_D_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r
54307cea 462**/\r
2f88bd3a 463#define MSR_XEON_D_TURBO_RATIO_LIMIT 0x000001AD\r
54307cea
MK		 464\r
465/**\r
466 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT\r
467**/\r
468typedef union {\r
469 ///\r
470 /// Individual bit fields\r
471 ///\r
472 struct {\r
473 ///\r
474 /// [Bits 7:0] Package. Maximum Ratio Limit for 1C.\r
475 ///\r
2f88bd3a 476 UINT32 Maximum1C : 8;\r
54307cea
MK		 477 ///\r
478 /// [Bits 15:8] Package. Maximum Ratio Limit for 2C.\r
479 ///\r
2f88bd3a 480 UINT32 Maximum2C : 8;\r
54307cea
MK		 481 ///\r
482 /// [Bits 23:16] Package. Maximum Ratio Limit for 3C.\r
483 ///\r
2f88bd3a 484 UINT32 Maximum3C : 8;\r
54307cea
MK		 485 ///\r
486 /// [Bits 31:24] Package. Maximum Ratio Limit for 4C.\r
487 ///\r
2f88bd3a 488 UINT32 Maximum4C : 8;\r
54307cea
MK		 489 ///\r
490 /// [Bits 39:32] Package. Maximum Ratio Limit for 5C.\r
491 ///\r
2f88bd3a 492 UINT32 Maximum5C : 8;\r
54307cea
MK		 493 ///\r
494 /// [Bits 47:40] Package. Maximum Ratio Limit for 6C.\r
495 ///\r
2f88bd3a 496 UINT32 Maximum6C : 8;\r
54307cea
MK		 497 ///\r
498 /// [Bits 55:48] Package. Maximum Ratio Limit for 7C.\r
499 ///\r
2f88bd3a 500 UINT32 Maximum7C : 8;\r
54307cea
MK		 501 ///\r
502 /// [Bits 63:56] Package. Maximum Ratio Limit for 8C.\r
503 ///\r
2f88bd3a 504 UINT32 Maximum8C : 8;\r
54307cea
MK		 505 } Bits;\r
506 ///\r
507 /// All bit fields as a 64-bit value\r
508 ///\r
2f88bd3a 509 UINT64 Uint64;\r
54307cea
MK		 510} MSR_XEON_D_TURBO_RATIO_LIMIT_REGISTER;\r
511\r
54307cea
MK		 512/**\r
513 Package. Maximum Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
514 RW if MSR_PLATFORM_INFO.[28] = 1.\r
515\r
516 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT1 (0x000001AE)\r
517 @param EAX Lower 32-bits of MSR value.\r
518 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
519 @param EDX Upper 32-bits of MSR value.\r
520 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER.\r
521\r
522 <b>Example usage</b>\r
523 @code\r
524 MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER Msr;\r
525\r
526 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT1);\r
527 @endcode\r
b6ae7578 528 @note MSR_XEON_D_TURBO_RATIO_LIMIT1 is defined as MSR_TURBO_RATIO_LIMIT1 in SDM.\r
54307cea 529**/\r
2f88bd3a 530#define MSR_XEON_D_TURBO_RATIO_LIMIT1 0x000001AE\r
54307cea
MK		 531\r
532/**\r
533 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT1\r
534**/\r
535typedef union {\r
536 ///\r
537 /// Individual bit fields\r
538 ///\r
539 struct {\r
540 ///\r
541 /// [Bits 7:0] Package. Maximum Ratio Limit for 9C.\r
542 ///\r
2f88bd3a 543 UINT32 Maximum9C : 8;\r
54307cea
MK		 544 ///\r
545 /// [Bits 15:8] Package. Maximum Ratio Limit for 10C.\r
546 ///\r
2f88bd3a 547 UINT32 Maximum10C : 8;\r
54307cea
MK		 548 ///\r
549 /// [Bits 23:16] Package. Maximum Ratio Limit for 11C.\r
550 ///\r
2f88bd3a 551 UINT32 Maximum11C : 8;\r
54307cea
MK		 552 ///\r
553 /// [Bits 31:24] Package. Maximum Ratio Limit for 12C.\r
554 ///\r
2f88bd3a 555 UINT32 Maximum12C : 8;\r
54307cea
MK		 556 ///\r
557 /// [Bits 39:32] Package. Maximum Ratio Limit for 13C.\r
558 ///\r
2f88bd3a 559 UINT32 Maximum13C : 8;\r
54307cea
MK		 560 ///\r
561 /// [Bits 47:40] Package. Maximum Ratio Limit for 14C.\r
562 ///\r
2f88bd3a 563 UINT32 Maximum14C : 8;\r
54307cea
MK		 564 ///\r
565 /// [Bits 55:48] Package. Maximum Ratio Limit for 15C.\r
566 ///\r
2f88bd3a 567 UINT32 Maximum15C : 8;\r
54307cea
MK		 568 ///\r
569 /// [Bits 63:56] Package. Maximum Ratio Limit for 16C.\r
570 ///\r
2f88bd3a 571 UINT32 Maximum16C : 8;\r
54307cea
MK		 572 } Bits;\r
573 ///\r
574 /// All bit fields as a 64-bit value\r
575 ///\r
2f88bd3a 576 UINT64 Uint64;\r
54307cea
MK		 577} MSR_XEON_D_TURBO_RATIO_LIMIT1_REGISTER;\r
578\r
54307cea
MK		 579/**\r
580 Package. Unit Multipliers used in RAPL Interfaces (R/O).\r
581\r
582 @param ECX MSR_XEON_D_RAPL_POWER_UNIT (0x00000606)\r
583 @param EAX Lower 32-bits of MSR value.\r
584 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
585 @param EDX Upper 32-bits of MSR value.\r
586 Described by the type MSR_XEON_D_RAPL_POWER_UNIT_REGISTER.\r
587\r
588 <b>Example usage</b>\r
589 @code\r
590 MSR_XEON_D_RAPL_POWER_UNIT_REGISTER Msr;\r
591\r
592 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_RAPL_POWER_UNIT);\r
593 @endcode\r
b6ae7578 594 @note MSR_XEON_D_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r
54307cea 595**/\r
2f88bd3a 596#define MSR_XEON_D_RAPL_POWER_UNIT 0x00000606\r
54307cea
MK		 597\r
598/**\r
599 MSR information returned for MSR index #MSR_XEON_D_RAPL_POWER_UNIT\r
600**/\r
601typedef union {\r
602 ///\r
603 /// Individual bit fields\r
604 ///\r
605 struct {\r
606 ///\r
607 /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r
608 ///\r
2f88bd3a
MK		 609 UINT32 PowerUnits : 4;\r
610 UINT32 Reserved1 : 4;\r
54307cea
MK		 611 ///\r
612 /// [Bits 12:8] Package. Energy Status Units Energy related information\r
613 /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r
614 /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r
615 /// micro-joules).\r
616 ///\r
2f88bd3a
MK		 617 UINT32 EnergyStatusUnits : 5;\r
618 UINT32 Reserved2 : 3;\r
54307cea
MK		 619 ///\r
620 /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r
621 /// Interfaces.".\r
622 ///\r
2f88bd3a
MK		 623 UINT32 TimeUnits : 4;\r
624 UINT32 Reserved3 : 12;\r
625 UINT32 Reserved4 : 32;\r
54307cea
MK		 626 } Bits;\r
627 ///\r
628 /// All bit fields as a 32-bit value\r
629 ///\r
2f88bd3a 630 UINT32 Uint32;\r
54307cea
MK		 631 ///\r
632 /// All bit fields as a 64-bit value\r
633 ///\r
2f88bd3a 634 UINT64 Uint64;\r
54307cea
MK		 635} MSR_XEON_D_RAPL_POWER_UNIT_REGISTER;\r
636\r
54307cea
MK		 637/**\r
638 Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r
639 Domain.".\r
640\r
641 @param ECX MSR_XEON_D_DRAM_POWER_LIMIT (0x00000618)\r
642 @param EAX Lower 32-bits of MSR value.\r
643 @param EDX Upper 32-bits of MSR value.\r
644\r
645 <b>Example usage</b>\r
646 @code\r
647 UINT64 Msr;\r
648\r
649 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT);\r
650 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_LIMIT, Msr);\r
651 @endcode\r
b6ae7578 652 @note MSR_XEON_D_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r
54307cea 653**/\r
2f88bd3a 654#define MSR_XEON_D_DRAM_POWER_LIMIT 0x00000618\r
54307cea
MK		 655\r
656/**\r
0f16be6d 657 Package. DRAM Energy Status (R/O) Energy consumed by DRAM devices.\r
54307cea
MK		 658\r
659 @param ECX MSR_XEON_D_DRAM_ENERGY_STATUS (0x00000619)\r
660 @param EAX Lower 32-bits of MSR value.\r
0f16be6d 661 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea 662 @param EDX Upper 32-bits of MSR value.\r
0f16be6d 663 Described by the type MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER.\r
54307cea
MK		 664\r
665 <b>Example usage</b>\r
666 @code\r
0f16be6d 667 MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER Msr;\r
54307cea 668\r
0f16be6d 669 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_DRAM_ENERGY_STATUS);\r
54307cea 670 @endcode\r
b6ae7578 671 @note MSR_XEON_D_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r
54307cea 672**/\r
2f88bd3a 673#define MSR_XEON_D_DRAM_ENERGY_STATUS 0x00000619\r
54307cea 674\r
0f16be6d
HW		 675/**\r
676 MSR information returned for MSR index #MSR_XEON_D_DRAM_ENERGY_STATUS\r
677**/\r
678typedef union {\r
679 ///\r
680 /// Individual bit fields\r
681 ///\r
682 struct {\r
683 ///\r
684 /// [Bits 31:0] Energy in 15.3 micro-joules. Requires BIOS configuration\r
685 /// to enable DRAM RAPL mode 0 (Direct VR).\r
686 ///\r
2f88bd3a
MK		 687 UINT32 Energy : 32;\r
688 UINT32 Reserved : 32;\r
0f16be6d
HW		 689 } Bits;\r
690 ///\r
691 /// All bit fields as a 32-bit value\r
692 ///\r
2f88bd3a 693 UINT32 Uint32;\r
0f16be6d
HW		 694 ///\r
695 /// All bit fields as a 64-bit value\r
696 ///\r
2f88bd3a 697 UINT64 Uint64;\r
0f16be6d
HW		 698} MSR_XEON_D_DRAM_ENERGY_STATUS_REGISTER;\r
699\r
54307cea
MK		 700/**\r
701 Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r
702 RAPL Domain.".\r
703\r
704 @param ECX MSR_XEON_D_DRAM_PERF_STATUS (0x0000061B)\r
705 @param EAX Lower 32-bits of MSR value.\r
706 @param EDX Upper 32-bits of MSR value.\r
707\r
708 <b>Example usage</b>\r
709 @code\r
710 UINT64 Msr;\r
711\r
712 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_PERF_STATUS);\r
713 @endcode\r
b6ae7578 714 @note MSR_XEON_D_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r
54307cea 715**/\r
2f88bd3a 716#define MSR_XEON_D_DRAM_PERF_STATUS 0x0000061B\r
54307cea
MK		 717\r
718/**\r
719 Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r
720\r
721 @param ECX MSR_XEON_D_DRAM_POWER_INFO (0x0000061C)\r
722 @param EAX Lower 32-bits of MSR value.\r
723 @param EDX Upper 32-bits of MSR value.\r
724\r
725 <b>Example usage</b>\r
726 @code\r
727 UINT64 Msr;\r
728\r
729 Msr = AsmReadMsr64 (MSR_XEON_D_DRAM_POWER_INFO);\r
730 AsmWriteMsr64 (MSR_XEON_D_DRAM_POWER_INFO, Msr);\r
731 @endcode\r
b6ae7578 732 @note MSR_XEON_D_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r
54307cea 733**/\r
2f88bd3a 734#define MSR_XEON_D_DRAM_POWER_INFO 0x0000061C\r
54307cea 735\r
0f16be6d 736/**\r
c4b07363
ED		 737 Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r
738 fields represent the widest possible range of uncore frequencies. Writing to\r
739 these fields allows software to control the minimum and the maximum\r
740 frequency that hardware will select.\r
741\r
742 @param ECX MSR_XEON_D_MSRUNCORE_RATIO_LIMIT (0x00000620)\r
743 @param EAX Lower 32-bits of MSR value.\r
744 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
745 @param EDX Upper 32-bits of MSR value.\r
746 Described by the type MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER.\r
747\r
748 <b>Example usage</b>\r
749 @code\r
750 MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r
751\r
752 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT);\r
753 AsmWriteMsr64 (MSR_XEON_D_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r
754 @endcode\r
755**/\r
2f88bd3a 756#define MSR_XEON_D_MSRUNCORE_RATIO_LIMIT 0x00000620\r
c4b07363
ED		 757\r
758/**\r
759 MSR information returned for MSR index #MSR_XEON_D_MSRUNCORE_RATIO_LIMIT\r
760**/\r
761typedef union {\r
762 ///\r
763 /// Individual bit fields\r
764 ///\r
765 struct {\r
766 ///\r
767 /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r
768 /// LLC/Ring.\r
769 ///\r
2f88bd3a
MK		 770 UINT32 MAX_RATIO : 7;\r
771 UINT32 Reserved1 : 1;\r
c4b07363
ED		 772 ///\r
773 /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r
774 /// possible ratio of the LLC/Ring.\r
775 ///\r
2f88bd3a
MK		 776 UINT32 MIN_RATIO : 7;\r
777 UINT32 Reserved2 : 17;\r
778 UINT32 Reserved3 : 32;\r
c4b07363
ED		 779 } Bits;\r
780 ///\r
781 /// All bit fields as a 32-bit value\r
782 ///\r
2f88bd3a 783 UINT32 Uint32;\r
c4b07363
ED		 784 ///\r
785 /// All bit fields as a 64-bit value\r
786 ///\r
2f88bd3a 787 UINT64 Uint64;\r
c4b07363
ED		 788} MSR_XEON_D_MSRUNCORE_RATIO_LIMIT_REGISTER;\r
789\r
790/**\r
791 Package. Reserved (R/O) Reads return 0.\r
0f16be6d
HW		 792\r
793 @param ECX MSR_XEON_D_PP0_ENERGY_STATUS (0x00000639)\r
794 @param EAX Lower 32-bits of MSR value.\r
795 @param EDX Upper 32-bits of MSR value.\r
796\r
797 <b>Example usage</b>\r
798 @code\r
799 UINT64 Msr;\r
800\r
801 Msr = AsmReadMsr64 (MSR_XEON_D_PP0_ENERGY_STATUS);\r
802 @endcode\r
803 @note MSR_XEON_D_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r
804**/\r
2f88bd3a 805#define MSR_XEON_D_PP0_ENERGY_STATUS 0x00000639\r
0f16be6d 806\r
54307cea
MK		 807/**\r
808 Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r
809 refers to processor core frequency).\r
810\r
811 @param ECX MSR_XEON_D_CORE_PERF_LIMIT_REASONS (0x00000690)\r
812 @param EAX Lower 32-bits of MSR value.\r
813 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
814 @param EDX Upper 32-bits of MSR value.\r
815 Described by the type MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER.\r
816\r
817 <b>Example usage</b>\r
818 @code\r
819 MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r
820\r
821 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS);\r
822 AsmWriteMsr64 (MSR_XEON_D_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r
823 @endcode\r
b6ae7578 824 @note MSR_XEON_D_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r
54307cea 825**/\r
2f88bd3a 826#define MSR_XEON_D_CORE_PERF_LIMIT_REASONS 0x00000690\r
54307cea
MK		 827\r
828/**\r
829 MSR information returned for MSR index #MSR_XEON_D_CORE_PERF_LIMIT_REASONS\r
830**/\r
831typedef union {\r
832 ///\r
833 /// Individual bit fields\r
834 ///\r
835 struct {\r
836 ///\r
837 /// [Bit 0] PROCHOT Status (R0) When set, processor core frequency is\r
838 /// reduced below the operating system request due to assertion of\r
839 /// external PROCHOT.\r
840 ///\r
2f88bd3a 841 UINT32 PROCHOT_Status : 1;\r
54307cea
MK		 842 ///\r
843 /// [Bit 1] Thermal Status (R0) When set, frequency is reduced below the\r
844 /// operating system request due to a thermal event.\r
845 ///\r
2f88bd3a 846 UINT32 ThermalStatus : 1;\r
54307cea
MK		 847 ///\r
848 /// [Bit 2] Power Budget Management Status (R0) When set, frequency is\r
849 /// reduced below the operating system request due to PBM limit.\r
850 ///\r
2f88bd3a 851 UINT32 PowerBudgetManagementStatus : 1;\r
54307cea
MK		 852 ///\r
853 /// [Bit 3] Platform Configuration Services Status (R0) When set,\r
854 /// frequency is reduced below the operating system request due to PCS\r
855 /// limit.\r
856 ///\r
2f88bd3a
MK		 857 UINT32 PlatformConfigurationServicesStatus : 1;\r
858 UINT32 Reserved1 : 1;\r
54307cea
MK		 859 ///\r
860 /// [Bit 5] Autonomous Utilization-Based Frequency Control Status (R0)\r
861 /// When set, frequency is reduced below the operating system request\r
862 /// because the processor has detected that utilization is low.\r
863 ///\r
2f88bd3a 864 UINT32 AutonomousUtilizationBasedFrequencyControlStatus : 1;\r
54307cea
MK		 865 ///\r
866 /// [Bit 6] VR Therm Alert Status (R0) When set, frequency is reduced\r
867 /// below the operating system request due to a thermal alert from the\r
868 /// Voltage Regulator.\r
869 ///\r
2f88bd3a
MK		 870 UINT32 VRThermAlertStatus : 1;\r
871 UINT32 Reserved2 : 1;\r
54307cea
MK		 872 ///\r
873 /// [Bit 8] Electrical Design Point Status (R0) When set, frequency is\r
874 /// reduced below the operating system request due to electrical design\r
875 /// point constraints (e.g. maximum electrical current consumption).\r
876 ///\r
2f88bd3a
MK		 877 UINT32 ElectricalDesignPointStatus : 1;\r
878 UINT32 Reserved3 : 1;\r
54307cea
MK		 879 ///\r
880 /// [Bit 10] Multi-Core Turbo Status (R0) When set, frequency is reduced\r
881 /// below the operating system request due to Multi-Core Turbo limits.\r
882 ///\r
2f88bd3a
MK		 883 UINT32 MultiCoreTurboStatus : 1;\r
884 UINT32 Reserved4 : 2;\r
54307cea
MK		 885 ///\r
886 /// [Bit 13] Core Frequency P1 Status (R0) When set, frequency is reduced\r
887 /// below max non-turbo P1.\r
888 ///\r
2f88bd3a 889 UINT32 FrequencyP1Status : 1;\r
54307cea
MK		 890 ///\r
891 /// [Bit 14] Core Max n-core Turbo Frequency Limiting Status (R0) When\r
892 /// set, frequency is reduced below max n-core turbo frequency.\r
893 ///\r
2f88bd3a 894 UINT32 TurboFrequencyLimitingStatus : 1;\r
54307cea
MK		 895 ///\r
896 /// [Bit 15] Core Frequency Limiting Status (R0) When set, frequency is\r
897 /// reduced below the operating system request.\r
898 ///\r
2f88bd3a 899 UINT32 FrequencyLimitingStatus : 1;\r
54307cea
MK		 900 ///\r
901 /// [Bit 16] PROCHOT Log When set, indicates that the PROCHOT Status bit\r
902 /// has asserted since the log bit was last cleared. This log bit will\r
903 /// remain set until cleared by software writing 0.\r
904 ///\r
2f88bd3a 905 UINT32 PROCHOT_Log : 1;\r
54307cea
MK		 906 ///\r
907 /// [Bit 17] Thermal Log When set, indicates that the Thermal Status bit\r
908 /// has asserted since the log bit was last cleared. This log bit will\r
909 /// remain set until cleared by software writing 0.\r
910 ///\r
2f88bd3a 911 UINT32 ThermalLog : 1;\r
54307cea
MK		 912 ///\r
913 /// [Bit 18] Power Budget Management Log When set, indicates that the PBM\r
914 /// Status bit has asserted since the log bit was last cleared. This log\r
915 /// bit will remain set until cleared by software writing 0.\r
916 ///\r
2f88bd3a 917 UINT32 PowerBudgetManagementLog : 1;\r
54307cea
MK		 918 ///\r
919 /// [Bit 19] Platform Configuration Services Log When set, indicates that\r
920 /// the PCS Status bit has asserted since the log bit was last cleared.\r
921 /// This log bit will remain set until cleared by software writing 0.\r
922 ///\r
2f88bd3a
MK		 923 UINT32 PlatformConfigurationServicesLog : 1;\r
924 UINT32 Reserved5 : 1;\r
54307cea
MK		 925 ///\r
926 /// [Bit 21] Autonomous Utilization-Based Frequency Control Log When set,\r
927 /// indicates that the AUBFC Status bit has asserted since the log bit was\r
928 /// last cleared. This log bit will remain set until cleared by software\r
929 /// writing 0.\r
930 ///\r
2f88bd3a 931 UINT32 AutonomousUtilizationBasedFrequencyControlLog : 1;\r
54307cea
MK		 932 ///\r
933 /// [Bit 22] VR Therm Alert Log When set, indicates that the VR Therm\r
934 /// Alert Status bit has asserted since the log bit was last cleared. This\r
935 /// log bit will remain set until cleared by software writing 0.\r
936 ///\r
2f88bd3a
MK		 937 UINT32 VRThermAlertLog : 1;\r
938 UINT32 Reserved6 : 1;\r
54307cea
MK		 939 ///\r
940 /// [Bit 24] Electrical Design Point Log When set, indicates that the EDP\r
941 /// Status bit has asserted since the log bit was last cleared. This log\r
942 /// bit will remain set until cleared by software writing 0.\r
943 ///\r
2f88bd3a
MK		 944 UINT32 ElectricalDesignPointLog : 1;\r
945 UINT32 Reserved7 : 1;\r
54307cea
MK		 946 ///\r
947 /// [Bit 26] Multi-Core Turbo Log When set, indicates that the Multi-Core\r
948 /// Turbo Status bit has asserted since the log bit was last cleared. This\r
949 /// log bit will remain set until cleared by software writing 0.\r
950 ///\r
2f88bd3a
MK		 951 UINT32 MultiCoreTurboLog : 1;\r
952 UINT32 Reserved8 : 2;\r
54307cea
MK		 953 ///\r
954 /// [Bit 29] Core Frequency P1 Log When set, indicates that the Core\r
955 /// Frequency P1 Status bit has asserted since the log bit was last\r
956 /// cleared. This log bit will remain set until cleared by software\r
957 /// writing 0.\r
958 ///\r
2f88bd3a 959 UINT32 CoreFrequencyP1Log : 1;\r
54307cea
MK		 960 ///\r
961 /// [Bit 30] Core Max n-core Turbo Frequency Limiting Log When set,\r
962 /// indicates that the Core Max n-core Turbo Frequency Limiting Status bit\r
963 /// has asserted since the log bit was last cleared. This log bit will\r
964 /// remain set until cleared by software writing 0.\r
965 ///\r
2f88bd3a 966 UINT32 TurboFrequencyLimitingLog : 1;\r
54307cea
MK		 967 ///\r
968 /// [Bit 31] Core Frequency Limiting Log When set, indicates that the Core\r
969 /// Frequency Limiting Status bit has asserted since the log bit was last\r
970 /// cleared. This log bit will remain set until cleared by software\r
971 /// writing 0.\r
972 ///\r
2f88bd3a
MK		 973 UINT32 CoreFrequencyLimitingLog : 1;\r
974 UINT32 Reserved9 : 32;\r
54307cea
MK		 975 } Bits;\r
976 ///\r
977 /// All bit fields as a 32-bit value\r
978 ///\r
2f88bd3a 979 UINT32 Uint32;\r
54307cea
MK		 980 ///\r
981 /// All bit fields as a 64-bit value\r
982 ///\r
2f88bd3a 983 UINT64 Uint64;\r
54307cea
MK		 984} MSR_XEON_D_CORE_PERF_LIMIT_REASONS_REGISTER;\r
985\r
54307cea
MK		 986/**\r
987 THREAD. Monitoring Event Select Register (R/W) if CPUID.(EAX=07H,\r
0f16be6d 988 ECX=0):EBX.RDT-M[bit 12] = 1.\r
54307cea
MK		 989\r
990 @param ECX MSR_XEON_D_IA32_QM_EVTSEL (0x00000C8D)\r
991 @param EAX Lower 32-bits of MSR value.\r
992 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
993 @param EDX Upper 32-bits of MSR value.\r
994 Described by the type MSR_XEON_D_IA32_QM_EVTSEL_REGISTER.\r
995\r
996 <b>Example usage</b>\r
997 @code\r
998 MSR_XEON_D_IA32_QM_EVTSEL_REGISTER Msr;\r
999\r
1000 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_QM_EVTSEL);\r
1001 AsmWriteMsr64 (MSR_XEON_D_IA32_QM_EVTSEL, Msr.Uint64);\r
1002 @endcode\r
b6ae7578 1003 @note MSR_XEON_D_IA32_QM_EVTSEL is defined as IA32_QM_EVTSEL in SDM.\r
54307cea 1004**/\r
2f88bd3a 1005#define MSR_XEON_D_IA32_QM_EVTSEL 0x00000C8D\r
54307cea
MK		 1006\r
1007/**\r
1008 MSR information returned for MSR index #MSR_XEON_D_IA32_QM_EVTSEL\r
1009**/\r
1010typedef union {\r
1011 ///\r
1012 /// Individual bit fields\r
1013 ///\r
1014 struct {\r
1015 ///\r
1016 /// [Bits 7:0] EventID (RW) Event encoding: 0x00: no monitoring 0x01: L3\r
1017 /// occupancy monitoring 0x02: Total memory bandwidth monitoring 0x03:\r
1018 /// Local memory bandwidth monitoring All other encoding reserved.\r
1019 ///\r
2f88bd3a
MK		 1020 UINT32 EventID : 8;\r
1021 UINT32 Reserved1 : 24;\r
54307cea
MK		 1022 ///\r
1023 /// [Bits 41:32] RMID (RW).\r
1024 ///\r
2f88bd3a
MK		 1025 UINT32 RMID : 10;\r
1026 UINT32 Reserved2 : 22;\r
54307cea
MK		 1027 } Bits;\r
1028 ///\r
1029 /// All bit fields as a 64-bit value\r
1030 ///\r
2f88bd3a 1031 UINT64 Uint64;\r
54307cea
MK		 1032} MSR_XEON_D_IA32_QM_EVTSEL_REGISTER;\r
1033\r
54307cea
MK		 1034/**\r
1035 THREAD. Resource Association Register (R/W).\r
1036\r
1037 @param ECX MSR_XEON_D_IA32_PQR_ASSOC (0x00000C8F)\r
1038 @param EAX Lower 32-bits of MSR value.\r
1039 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1040 @param EDX Upper 32-bits of MSR value.\r
1041 Described by the type MSR_XEON_D_IA32_PQR_ASSOC_REGISTER.\r
1042\r
1043 <b>Example usage</b>\r
1044 @code\r
1045 MSR_XEON_D_IA32_PQR_ASSOC_REGISTER Msr;\r
1046\r
1047 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_PQR_ASSOC);\r
1048 AsmWriteMsr64 (MSR_XEON_D_IA32_PQR_ASSOC, Msr.Uint64);\r
1049 @endcode\r
b6ae7578 1050 @note MSR_XEON_D_IA32_PQR_ASSOC is defined as IA32_PQR_ASSOC in SDM.\r
54307cea 1051**/\r
2f88bd3a 1052#define MSR_XEON_D_IA32_PQR_ASSOC 0x00000C8F\r
54307cea
MK		 1053\r
1054/**\r
1055 MSR information returned for MSR index #MSR_XEON_D_IA32_PQR_ASSOC\r
1056**/\r
1057typedef union {\r
1058 ///\r
1059 /// Individual bit fields\r
1060 ///\r
1061 struct {\r
1062 ///\r
1063 /// [Bits 9:0] RMID.\r
1064 ///\r
2f88bd3a
MK		 1065 UINT32 RMID : 10;\r
1066 UINT32 Reserved1 : 22;\r
54307cea
MK		 1067 ///\r
1068 /// [Bits 51:32] COS (R/W).\r
1069 ///\r
2f88bd3a
MK		 1070 UINT32 COS : 20;\r
1071 UINT32 Reserved2 : 12;\r
54307cea
MK		 1072 } Bits;\r
1073 ///\r
1074 /// All bit fields as a 64-bit value\r
1075 ///\r
2f88bd3a 1076 UINT64 Uint64;\r
54307cea
MK		 1077} MSR_XEON_D_IA32_PQR_ASSOC_REGISTER;\r
1078\r
54307cea
MK		 1079/**\r
1080 Package. L3 Class Of Service Mask - COS n (R/W) if CPUID.(EAX=10H,\r
1081 ECX=1):EDX.COS_MAX[15:0] >= n.\r
1082\r
1083 @param ECX MSR_XEON_D_IA32_L3_QOS_MASK_n\r
1084 @param EAX Lower 32-bits of MSR value.\r
1085 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1086 @param EDX Upper 32-bits of MSR value.\r
1087 Described by the type MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER.\r
1088\r
1089 <b>Example usage</b>\r
1090 @code\r
1091 MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER Msr;\r
1092\r
1093 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0);\r
1094 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_MASK_0, Msr.Uint64);\r
1095 @endcode\r
b6ae7578
JF		 1096 @note MSR_XEON_D_IA32_L3_QOS_MASK_0 is defined as IA32_L3_QOS_MASK_0 in SDM.\r
1097 MSR_XEON_D_IA32_L3_QOS_MASK_1 is defined as IA32_L3_QOS_MASK_1 in SDM.\r
1098 MSR_XEON_D_IA32_L3_QOS_MASK_2 is defined as IA32_L3_QOS_MASK_2 in SDM.\r
1099 MSR_XEON_D_IA32_L3_QOS_MASK_3 is defined as IA32_L3_QOS_MASK_3 in SDM.\r
1100 MSR_XEON_D_IA32_L3_QOS_MASK_4 is defined as IA32_L3_QOS_MASK_4 in SDM.\r
1101 MSR_XEON_D_IA32_L3_QOS_MASK_5 is defined as IA32_L3_QOS_MASK_5 in SDM.\r
1102 MSR_XEON_D_IA32_L3_QOS_MASK_6 is defined as IA32_L3_QOS_MASK_6 in SDM.\r
1103 MSR_XEON_D_IA32_L3_QOS_MASK_7 is defined as IA32_L3_QOS_MASK_7 in SDM.\r
1104 MSR_XEON_D_IA32_L3_QOS_MASK_8 is defined as IA32_L3_QOS_MASK_8 in SDM.\r
1105 MSR_XEON_D_IA32_L3_QOS_MASK_9 is defined as IA32_L3_QOS_MASK_9 in SDM.\r
1106 MSR_XEON_D_IA32_L3_QOS_MASK_10 is defined as IA32_L3_QOS_MASK_10 in SDM.\r
1107 MSR_XEON_D_IA32_L3_QOS_MASK_11 is defined as IA32_L3_QOS_MASK_11 in SDM.\r
1108 MSR_XEON_D_IA32_L3_QOS_MASK_12 is defined as IA32_L3_QOS_MASK_12 in SDM.\r
1109 MSR_XEON_D_IA32_L3_QOS_MASK_13 is defined as IA32_L3_QOS_MASK_13 in SDM.\r
1110 MSR_XEON_D_IA32_L3_QOS_MASK_14 is defined as IA32_L3_QOS_MASK_14 in SDM.\r
1111 MSR_XEON_D_IA32_L3_QOS_MASK_15 is defined as IA32_L3_QOS_MASK_15 in SDM.\r
54307cea
MK		 1112 @{\r
1113**/\r
2f88bd3a
MK		 1114#define MSR_XEON_D_IA32_L3_QOS_MASK_0 0x00000C90\r
1115#define MSR_XEON_D_IA32_L3_QOS_MASK_1 0x00000C91\r
1116#define MSR_XEON_D_IA32_L3_QOS_MASK_2 0x00000C92\r
1117#define MSR_XEON_D_IA32_L3_QOS_MASK_3 0x00000C93\r
1118#define MSR_XEON_D_IA32_L3_QOS_MASK_4 0x00000C94\r
1119#define MSR_XEON_D_IA32_L3_QOS_MASK_5 0x00000C95\r
1120#define MSR_XEON_D_IA32_L3_QOS_MASK_6 0x00000C96\r
1121#define MSR_XEON_D_IA32_L3_QOS_MASK_7 0x00000C97\r
1122#define MSR_XEON_D_IA32_L3_QOS_MASK_8 0x00000C98\r
1123#define MSR_XEON_D_IA32_L3_QOS_MASK_9 0x00000C99\r
1124#define MSR_XEON_D_IA32_L3_QOS_MASK_10 0x00000C9A\r
1125#define MSR_XEON_D_IA32_L3_QOS_MASK_11 0x00000C9B\r
1126#define MSR_XEON_D_IA32_L3_QOS_MASK_12 0x00000C9C\r
1127#define MSR_XEON_D_IA32_L3_QOS_MASK_13 0x00000C9D\r
1128#define MSR_XEON_D_IA32_L3_QOS_MASK_14 0x00000C9E\r
1129#define MSR_XEON_D_IA32_L3_QOS_MASK_15 0x00000C9F\r
54307cea
MK		 1130/// @}\r
1131\r
1132/**\r
1133 MSR information returned for MSR indexes #MSR_XEON_D_IA32_L3_QOS_MASK_0\r
1134 to #MSR_XEON_D_IA32_L3_QOS_MASK_15.\r
1135**/\r
1136typedef union {\r
1137 ///\r
1138 /// Individual bit fields\r
1139 ///\r
1140 struct {\r
1141 ///\r
1142 /// [Bits 19:0] CBM: Bit vector of available L3 ways for COS 0 enforcement.\r
1143 ///\r
2f88bd3a
MK		 1144 UINT32 CBM : 20;\r
1145 UINT32 Reserved2 : 12;\r
1146 UINT32 Reserved3 : 32;\r
54307cea
MK		 1147 } Bits;\r
1148 ///\r
1149 /// All bit fields as a 32-bit value\r
1150 ///\r
2f88bd3a 1151 UINT32 Uint32;\r
54307cea
MK		 1152 ///\r
1153 /// All bit fields as a 64-bit value\r
1154 ///\r
2f88bd3a 1155 UINT64 Uint64;\r
54307cea
MK		 1156} MSR_XEON_D_IA32_L3_QOS_MASK_REGISTER;\r
1157\r
54307cea
MK		 1158/**\r
1159 Package. Config Ratio Limit of Turbo Mode RO if MSR_PLATFORM_INFO.[28] = 0,\r
1160 RW if MSR_PLATFORM_INFO.[28] = 1.\r
1161\r
1162 @param ECX MSR_XEON_D_TURBO_RATIO_LIMIT3 (0x000001AC)\r
1163 @param EAX Lower 32-bits of MSR value.\r
1164 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1165 @param EDX Upper 32-bits of MSR value.\r
1166 Described by the type MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER.\r
1167\r
1168 <b>Example usage</b>\r
1169 @code\r
1170 MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER Msr;\r
1171\r
1172 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_TURBO_RATIO_LIMIT3);\r
1173 @endcode\r
b6ae7578 1174 @note MSR_XEON_D_TURBO_RATIO_LIMIT3 is defined as MSR_TURBO_RATIO_LIMIT3 in SDM.\r
54307cea 1175**/\r
2f88bd3a 1176#define MSR_XEON_D_TURBO_RATIO_LIMIT3 0x000001AC\r
54307cea
MK		 1177\r
1178/**\r
1179 MSR information returned for MSR index #MSR_XEON_D_TURBO_RATIO_LIMIT3\r
1180**/\r
1181typedef union {\r
1182 ///\r
1183 /// Individual bit fields\r
1184 ///\r
1185 struct {\r
2f88bd3a
MK		 1186 UINT32 Reserved1 : 32;\r
1187 UINT32 Reserved2 : 31;\r
54307cea
MK		 1188 ///\r
1189 /// [Bit 63] Package. Semaphore for Turbo Ratio Limit Configuration If 1,\r
1190 /// the processor uses override configuration specified in\r
1191 /// MSR_TURBO_RATIO_LIMIT, MSR_TURBO_RATIO_LIMIT1. If 0, the processor\r
1192 /// uses factory-set configuration (Default).\r
1193 ///\r
2f88bd3a 1194 UINT32 TurboRatioLimitConfigurationSemaphore : 1;\r
54307cea
MK		 1195 } Bits;\r
1196 ///\r
1197 /// All bit fields as a 64-bit value\r
1198 ///\r
2f88bd3a 1199 UINT64 Uint64;\r
54307cea
MK		 1200} MSR_XEON_D_TURBO_RATIO_LIMIT3_REGISTER;\r
1201\r
54307cea
MK		 1202/**\r
1203 Package. Cache Allocation Technology Configuration (R/W).\r
1204\r
1205 @param ECX MSR_XEON_D_IA32_L3_QOS_CFG (0x00000C81)\r
1206 @param EAX Lower 32-bits of MSR value.\r
1207 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1208 @param EDX Upper 32-bits of MSR value.\r
1209 Described by the type MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER.\r
1210\r
1211 <b>Example usage</b>\r
1212 @code\r
1213 MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER Msr;\r
1214\r
1215 Msr.Uint64 = AsmReadMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG);\r
1216 AsmWriteMsr64 (MSR_XEON_D_IA32_L3_QOS_CFG, Msr.Uint64);\r
1217 @endcode\r
b6ae7578 1218 @note MSR_XEON_D_IA32_L3_QOS_CFG is defined as IA32_L3_QOS_CFG in SDM.\r
54307cea 1219**/\r
2f88bd3a 1220#define MSR_XEON_D_IA32_L3_QOS_CFG 0x00000C81\r
54307cea
MK		 1221\r
1222/**\r
1223 MSR information returned for MSR index #MSR_XEON_D_IA32_L3_QOS_CFG\r
1224**/\r
1225typedef union {\r
1226 ///\r
1227 /// Individual bit fields\r
1228 ///\r
1229 struct {\r
1230 ///\r
1231 /// [Bit 0] CAT Enable. Set 1 to enable Cache Allocation Technology.\r
1232 ///\r
2f88bd3a
MK		 1233 UINT32 CAT : 1;\r
1234 UINT32 Reserved1 : 31;\r
1235 UINT32 Reserved2 : 32;\r
54307cea
MK		 1236 } Bits;\r
1237 ///\r
1238 /// All bit fields as a 32-bit value\r
1239 ///\r
2f88bd3a 1240 UINT32 Uint32;\r
54307cea
MK		 1241 ///\r
1242 /// All bit fields as a 64-bit value\r
1243 ///\r
2f88bd3a 1244 UINT64 Uint64;\r
54307cea
MK		 1245} MSR_XEON_D_IA32_L3_QOS_CFG_REGISTER;\r
1246\r
1247#endif\r
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