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3adf6316 MK |
1 | /** @file\r |
2 | MSR Definitions for Intel(R) Xeon(R) Phi(TM) processor Family.\r | |
3 | \r | |
4 | Provides defines for Machine Specific Registers(MSR) indexes. Data structures\r | |
5 | are provided for MSRs that contain one or more bit fields. If the MSR value\r | |
6 | returned is a single 32-bit or 64-bit value, then a data structure is not\r | |
7 | provided for that MSR.\r | |
8 | \r | |
e057908f | 9 | Copyright (c) 2016 - 2019, Intel Corporation. All rights reserved.<BR>\r |
0acd8697 | 10 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
3adf6316 MK |
11 | \r |
12 | @par Specification Reference:\r | |
ba1a2d11 ED |
13 | Intel(R) 64 and IA-32 Architectures Software Developer's Manual, Volume 4,\r |
14 | May 2018, Volume 4: Model-Specific-Registers (MSR)\r | |
3adf6316 MK |
15 | \r |
16 | **/\r | |
17 | \r | |
18 | #ifndef __XEON_PHI_MSR_H__\r | |
19 | #define __XEON_PHI_MSR_H__\r | |
20 | \r | |
e057908f | 21 | #include <Register/Intel/ArchitecturalMsr.h>\r |
3adf6316 | 22 | \r |
f4c982bf JF |
23 | /**\r |
24 | Is Intel(R) Xeon(R) Phi(TM) processor Family?\r | |
25 | \r | |
26 | @param DisplayFamily Display Family ID\r | |
27 | @param DisplayModel Display Model ID\r | |
28 | \r | |
29 | @retval TRUE Yes, it is.\r | |
30 | @retval FALSE No, it isn't.\r | |
31 | **/\r | |
32 | #define IS_XEON_PHI_PROCESSOR(DisplayFamily, DisplayModel) \\r | |
33 | (DisplayFamily == 0x06 && \\r | |
34 | ( \\r | |
dfb20851 ED |
35 | DisplayModel == 0x57 || \\r |
36 | DisplayModel == 0x85 \\r | |
f4c982bf JF |
37 | ) \\r |
38 | )\r | |
39 | \r | |
3adf6316 MK |
40 | /**\r |
41 | Thread. SMI Counter (R/O).\r | |
42 | \r | |
43 | @param ECX MSR_XEON_PHI_SMI_COUNT (0x00000034)\r | |
44 | @param EAX Lower 32-bits of MSR value.\r | |
45 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
46 | @param EDX Upper 32-bits of MSR value.\r | |
47 | Described by the type MSR_XEON_PHI_SMI_COUNT_REGISTER.\r | |
48 | \r | |
49 | <b>Example usage</b>\r | |
50 | @code\r | |
51 | MSR_XEON_PHI_SMI_COUNT_REGISTER Msr;\r | |
52 | \r | |
53 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMI_COUNT);\r | |
54 | @endcode\r | |
ad8a2f5e | 55 | @note MSR_XEON_PHI_SMI_COUNT is defined as MSR_SMI_COUNT in SDM.\r |
3adf6316 | 56 | **/\r |
2f88bd3a | 57 | #define MSR_XEON_PHI_SMI_COUNT 0x00000034\r |
3adf6316 MK |
58 | \r |
59 | /**\r | |
60 | MSR information returned for MSR index #MSR_XEON_PHI_SMI_COUNT\r | |
61 | **/\r | |
62 | typedef union {\r | |
63 | ///\r | |
64 | /// Individual bit fields\r | |
65 | ///\r | |
66 | struct {\r | |
67 | ///\r | |
68 | /// [Bits 31:0] SMI Count (R/O).\r | |
69 | ///\r | |
2f88bd3a MK |
70 | UINT32 SMICount : 32;\r |
71 | UINT32 Reserved : 32;\r | |
3adf6316 MK |
72 | } Bits;\r |
73 | ///\r | |
74 | /// All bit fields as a 32-bit value\r | |
75 | ///\r | |
2f88bd3a | 76 | UINT32 Uint32;\r |
3adf6316 MK |
77 | ///\r |
78 | /// All bit fields as a 64-bit value\r | |
79 | ///\r | |
2f88bd3a | 80 | UINT64 Uint64;\r |
3adf6316 MK |
81 | } MSR_XEON_PHI_SMI_COUNT_REGISTER;\r |
82 | \r | |
dfb20851 ED |
83 | /**\r |
84 | Package. Protected Processor Inventory Number Enable Control (R/W).\r | |
85 | \r | |
86 | @param ECX MSR_XEON_PHI_PPIN_CTL (0x0000004E)\r | |
87 | @param EAX Lower 32-bits of MSR value.\r | |
88 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
89 | @param EDX Upper 32-bits of MSR value.\r | |
90 | Described by the type MSR_XEON_PHI_PPIN_CTL_REGISTER.\r | |
91 | \r | |
92 | <b>Example usage</b>\r | |
93 | @code\r | |
94 | MSR_XEON_PHI_PPIN_CTL_REGISTER Msr;\r | |
95 | \r | |
96 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PPIN_CTL);\r | |
97 | AsmWriteMsr64 (MSR_XEON_PHI_PPIN_CTL, Msr.Uint64);\r | |
98 | @endcode\r | |
99 | **/\r | |
2f88bd3a | 100 | #define MSR_XEON_PHI_PPIN_CTL 0x0000004E\r |
3adf6316 MK |
101 | \r |
102 | /**\r | |
dfb20851 ED |
103 | MSR information returned for MSR index #MSR_XEON_PHI_PPIN_CTL\r |
104 | **/\r | |
105 | typedef union {\r | |
106 | ///\r | |
107 | /// Individual bit fields\r | |
108 | ///\r | |
109 | struct {\r | |
110 | ///\r | |
111 | /// [Bit 0] LockOut (R/WO) Set 1 to prevent further writes to\r | |
112 | /// MSR_PPIN_CTL. Writing 1 to MSR_PPINCTL[bit 0] is permitted only if\r | |
113 | /// MSR_PPIN_CTL[bit 1] is clear. Default is 0. BIOS should provide an\r | |
114 | /// opt-in menu to enable the user to turn on MSR_PPIN_CTL[bit 1] for a\r | |
115 | /// privileged inventory initialization agent to access MSR_PPIN. After\r | |
116 | /// reading MSR_PPIN, the privileged inventory initialization agent should\r | |
117 | /// write '01b' to MSR_PPIN_CTL to disable further access to MSR_PPIN and\r | |
118 | /// prevent unauthorized modification to MSR_PPIN_CTL.\r | |
119 | ///\r | |
2f88bd3a | 120 | UINT32 LockOut : 1;\r |
dfb20851 ED |
121 | ///\r |
122 | /// [Bit 1] Enable_PPIN (R/W) If 1, enables MSR_PPIN to be accessible\r | |
123 | /// using RDMSR. Once set, an attempt to write 1 to MSR_PPIN_CTL[bit 0]\r | |
124 | /// will cause #GP. If 0, an attempt to read MSR_PPIN will cause #GP.\r | |
125 | /// Default is 0.\r | |
126 | ///\r | |
2f88bd3a MK |
127 | UINT32 Enable_PPIN : 1;\r |
128 | UINT32 Reserved1 : 30;\r | |
129 | UINT32 Reserved2 : 32;\r | |
dfb20851 ED |
130 | } Bits;\r |
131 | ///\r | |
132 | /// All bit fields as a 32-bit value\r | |
133 | ///\r | |
2f88bd3a | 134 | UINT32 Uint32;\r |
dfb20851 ED |
135 | ///\r |
136 | /// All bit fields as a 64-bit value\r | |
137 | ///\r | |
2f88bd3a | 138 | UINT64 Uint64;\r |
dfb20851 ED |
139 | } MSR_XEON_PHI_PPIN_CTL_REGISTER;\r |
140 | \r | |
dfb20851 ED |
141 | /**\r |
142 | Package. Protected Processor Inventory Number (R/O). Protected Processor\r | |
143 | Inventory Number (R/O) A unique value within a given CPUID\r | |
144 | family/model/stepping signature that a privileged inventory initialization\r | |
145 | agent can access to identify each physical processor, when access to\r | |
146 | MSR_PPIN is enabled. Access to MSR_PPIN is permitted only if\r | |
147 | MSR_PPIN_CTL[bits 1:0] = '10b'.\r | |
148 | \r | |
149 | @param ECX MSR_XEON_PHI_PPIN (0x0000004F)\r | |
150 | @param EAX Lower 32-bits of MSR value.\r | |
151 | @param EDX Upper 32-bits of MSR value.\r | |
152 | \r | |
153 | <b>Example usage</b>\r | |
154 | @code\r | |
155 | UINT64 Msr;\r | |
156 | \r | |
157 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PPIN);\r | |
158 | @endcode\r | |
159 | **/\r | |
2f88bd3a | 160 | #define MSR_XEON_PHI_PPIN 0x0000004F\r |
dfb20851 ED |
161 | \r |
162 | /**\r | |
163 | Package. Platform Information Contains power management and other model\r | |
164 | specific features enumeration. See http://biosbits.org.\r | |
3adf6316 MK |
165 | \r |
166 | @param ECX MSR_XEON_PHI_PLATFORM_INFO (0x000000CE)\r | |
167 | @param EAX Lower 32-bits of MSR value.\r | |
168 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
169 | @param EDX Upper 32-bits of MSR value.\r | |
170 | Described by the type MSR_XEON_PHI_PLATFORM_INFO_REGISTER.\r | |
171 | \r | |
172 | <b>Example usage</b>\r | |
173 | @code\r | |
174 | MSR_XEON_PHI_PLATFORM_INFO_REGISTER Msr;\r | |
175 | \r | |
176 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PLATFORM_INFO);\r | |
177 | AsmWriteMsr64 (MSR_XEON_PHI_PLATFORM_INFO, Msr.Uint64);\r | |
178 | @endcode\r | |
ad8a2f5e | 179 | @note MSR_XEON_PHI_PLATFORM_INFO is defined as MSR_PLATFORM_INFO in SDM.\r |
3adf6316 | 180 | **/\r |
2f88bd3a | 181 | #define MSR_XEON_PHI_PLATFORM_INFO 0x000000CE\r |
3adf6316 MK |
182 | \r |
183 | /**\r | |
184 | MSR information returned for MSR index #MSR_XEON_PHI_PLATFORM_INFO\r | |
185 | **/\r | |
186 | typedef union {\r | |
187 | ///\r | |
188 | /// Individual bit fields\r | |
189 | ///\r | |
190 | struct {\r | |
2f88bd3a | 191 | UINT32 Reserved1 : 8;\r |
3adf6316 MK |
192 | ///\r |
193 | /// [Bits 15:8] Package. Maximum Non-Turbo Ratio (R/O) The is the ratio\r | |
194 | /// of the frequency that invariant TSC runs at. Frequency = ratio * 100\r | |
195 | /// MHz.\r | |
196 | ///\r | |
2f88bd3a MK |
197 | UINT32 MaximumNonTurboRatio : 8;\r |
198 | UINT32 Reserved2 : 12;\r | |
3adf6316 MK |
199 | ///\r |
200 | /// [Bit 28] Package. Programmable Ratio Limit for Turbo Mode (R/O) When\r | |
201 | /// set to 1, indicates that Programmable Ratio Limits for Turbo mode is\r | |
202 | /// enabled, and when set to 0, indicates Programmable Ratio Limits for\r | |
203 | /// Turbo mode is disabled.\r | |
204 | ///\r | |
2f88bd3a | 205 | UINT32 RatioLimit : 1;\r |
3adf6316 MK |
206 | ///\r |
207 | /// [Bit 29] Package. Programmable TDP Limit for Turbo Mode (R/O) When\r | |
208 | /// set to 1, indicates that TDP Limits for Turbo mode are programmable,\r | |
209 | /// and when set to 0, indicates TDP Limit for Turbo mode is not\r | |
210 | /// programmable.\r | |
211 | ///\r | |
2f88bd3a MK |
212 | UINT32 TDPLimit : 1;\r |
213 | UINT32 Reserved3 : 2;\r | |
214 | UINT32 Reserved4 : 8;\r | |
3adf6316 MK |
215 | ///\r |
216 | /// [Bits 47:40] Package. Maximum Efficiency Ratio (R/O) The is the\r | |
217 | /// minimum ratio (maximum efficiency) that the processor can operates, in\r | |
218 | /// units of 100MHz.\r | |
219 | ///\r | |
2f88bd3a MK |
220 | UINT32 MaximumEfficiencyRatio : 8;\r |
221 | UINT32 Reserved5 : 16;\r | |
3adf6316 MK |
222 | } Bits;\r |
223 | ///\r | |
224 | /// All bit fields as a 64-bit value\r | |
225 | ///\r | |
2f88bd3a | 226 | UINT64 Uint64;\r |
3adf6316 MK |
227 | } MSR_XEON_PHI_PLATFORM_INFO_REGISTER;\r |
228 | \r | |
3adf6316 MK |
229 | /**\r |
230 | Module. C-State Configuration Control (R/W).\r | |
231 | \r | |
232 | @param ECX MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL (0x000000E2)\r | |
233 | @param EAX Lower 32-bits of MSR value.\r | |
234 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
235 | @param EDX Upper 32-bits of MSR value.\r | |
236 | Described by the type MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER.\r | |
237 | \r | |
238 | <b>Example usage</b>\r | |
239 | @code\r | |
240 | MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER Msr;\r | |
241 | \r | |
242 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL);\r | |
243 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL, Msr.Uint64);\r | |
244 | @endcode\r | |
ad8a2f5e | 245 | @note MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL is defined as MSR_PKG_CST_CONFIG_CONTROL in SDM.\r |
3adf6316 | 246 | **/\r |
2f88bd3a | 247 | #define MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL 0x000000E2\r |
3adf6316 MK |
248 | \r |
249 | /**\r | |
250 | MSR information returned for MSR index #MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL\r | |
251 | **/\r | |
252 | typedef union {\r | |
253 | ///\r | |
254 | /// Individual bit fields\r | |
255 | ///\r | |
256 | struct {\r | |
257 | ///\r | |
258 | /// [Bits 2:0] Package C-State Limit (R/W) The following C-state code\r | |
259 | /// name encodings are supported: 000b: C0/C1 001b: C2 010b: C6 No\r | |
260 | /// Retention 011b: C6 Retention 111b: No limit.\r | |
261 | ///\r | |
2f88bd3a MK |
262 | UINT32 Limit : 3;\r |
263 | UINT32 Reserved1 : 7;\r | |
3adf6316 MK |
264 | ///\r |
265 | /// [Bit 10] I/O MWAIT Redirection Enable (R/W).\r | |
266 | ///\r | |
2f88bd3a MK |
267 | UINT32 IO_MWAIT : 1;\r |
268 | UINT32 Reserved2 : 4;\r | |
3adf6316 MK |
269 | ///\r |
270 | /// [Bit 15] CFG Lock (R/WO).\r | |
271 | ///\r | |
2f88bd3a MK |
272 | UINT32 CFGLock : 1;\r |
273 | UINT32 Reserved5 : 10;\r | |
53002b7e ED |
274 | ///\r |
275 | /// [Bit 26] C1 State Auto Demotion Enable (R/W) When set, the processor\r | |
276 | /// will conditionally demote C3/C6/C7 requests to C1 based on uncore\r | |
277 | /// auto-demote information.\r | |
278 | ///\r | |
2f88bd3a MK |
279 | UINT32 C1StateAutoDemotionEnable : 1;\r |
280 | UINT32 Reserved6 : 1;\r | |
53002b7e ED |
281 | ///\r |
282 | /// [Bit 28] C1 State Auto Undemotion Enable (R/W) When set, enables\r | |
283 | /// Undemotion from Demoted C1.\r | |
284 | ///\r | |
2f88bd3a | 285 | UINT32 C1StateAutoUndemotionEnable : 1;\r |
53002b7e ED |
286 | ///\r |
287 | /// [Bit 29] PKG C-State Auto Demotion Enable (R/W) When set, enables\r | |
288 | /// Package C state demotion.\r | |
289 | ///\r | |
2f88bd3a MK |
290 | UINT32 PKGC_StateAutoDemotionEnable : 1;\r |
291 | UINT32 Reserved7 : 2;\r | |
292 | UINT32 Reserved4 : 32;\r | |
3adf6316 MK |
293 | } Bits;\r |
294 | ///\r | |
295 | /// All bit fields as a 32-bit value\r | |
296 | ///\r | |
2f88bd3a | 297 | UINT32 Uint32;\r |
3adf6316 MK |
298 | ///\r |
299 | /// All bit fields as a 64-bit value\r | |
300 | ///\r | |
2f88bd3a | 301 | UINT64 Uint64;\r |
3adf6316 MK |
302 | } MSR_XEON_PHI_PKG_CST_CONFIG_CONTROL_REGISTER;\r |
303 | \r | |
3adf6316 MK |
304 | /**\r |
305 | Module. Power Management IO Redirection in C-state (R/W).\r | |
306 | \r | |
307 | @param ECX MSR_XEON_PHI_PMG_IO_CAPTURE_BASE (0x000000E4)\r | |
308 | @param EAX Lower 32-bits of MSR value.\r | |
309 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
310 | @param EDX Upper 32-bits of MSR value.\r | |
311 | Described by the type MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER.\r | |
312 | \r | |
313 | <b>Example usage</b>\r | |
314 | @code\r | |
315 | MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER Msr;\r | |
316 | \r | |
317 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE);\r | |
318 | AsmWriteMsr64 (MSR_XEON_PHI_PMG_IO_CAPTURE_BASE, Msr.Uint64);\r | |
319 | @endcode\r | |
ad8a2f5e | 320 | @note MSR_XEON_PHI_PMG_IO_CAPTURE_BASE is defined as MSR_PMG_IO_CAPTURE_BASE in SDM.\r |
3adf6316 | 321 | **/\r |
2f88bd3a | 322 | #define MSR_XEON_PHI_PMG_IO_CAPTURE_BASE 0x000000E4\r |
3adf6316 MK |
323 | \r |
324 | /**\r | |
325 | MSR information returned for MSR index #MSR_XEON_PHI_PMG_IO_CAPTURE_BASE\r | |
326 | **/\r | |
327 | typedef union {\r | |
328 | ///\r | |
329 | /// Individual bit fields\r | |
330 | ///\r | |
331 | struct {\r | |
332 | ///\r | |
333 | /// [Bits 15:0] LVL_2 Base Address (R/W).\r | |
334 | ///\r | |
2f88bd3a | 335 | UINT32 Lvl2Base : 16;\r |
3adf6316 | 336 | ///\r |
53002b7e ED |
337 | /// [Bits 22:16] C-State Range (R/W) The IO-port block size in which\r |
338 | /// IO-redirection will be executed (0-127). Should be programmed based on\r | |
339 | /// the number of LVLx registers existing in the chipset.\r | |
3adf6316 | 340 | ///\r |
2f88bd3a MK |
341 | UINT32 CStateRange : 7;\r |
342 | UINT32 Reserved3 : 9;\r | |
343 | UINT32 Reserved2 : 32;\r | |
3adf6316 MK |
344 | } Bits;\r |
345 | ///\r | |
346 | /// All bit fields as a 32-bit value\r | |
347 | ///\r | |
2f88bd3a | 348 | UINT32 Uint32;\r |
3adf6316 MK |
349 | ///\r |
350 | /// All bit fields as a 64-bit value\r | |
351 | ///\r | |
2f88bd3a | 352 | UINT64 Uint64;\r |
3adf6316 MK |
353 | } MSR_XEON_PHI_PMG_IO_CAPTURE_BASE_REGISTER;\r |
354 | \r | |
3adf6316 MK |
355 | /**\r |
356 | Core. AES Configuration (RW-L) Privileged post-BIOS agent must provide a #GP\r | |
357 | handler to handle unsuccessful read of this MSR.\r | |
358 | \r | |
359 | @param ECX MSR_XEON_PHI_FEATURE_CONFIG (0x0000013C)\r | |
360 | @param EAX Lower 32-bits of MSR value.\r | |
361 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
362 | @param EDX Upper 32-bits of MSR value.\r | |
363 | Described by the type MSR_XEON_PHI_FEATURE_CONFIG_REGISTER.\r | |
364 | \r | |
365 | <b>Example usage</b>\r | |
366 | @code\r | |
367 | MSR_XEON_PHI_FEATURE_CONFIG_REGISTER Msr;\r | |
368 | \r | |
369 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_FEATURE_CONFIG);\r | |
370 | AsmWriteMsr64 (MSR_XEON_PHI_FEATURE_CONFIG, Msr.Uint64);\r | |
371 | @endcode\r | |
ad8a2f5e | 372 | @note MSR_XEON_PHI_FEATURE_CONFIG is defined as MSR_FEATURE_CONFIG in SDM.\r |
3adf6316 | 373 | **/\r |
2f88bd3a | 374 | #define MSR_XEON_PHI_FEATURE_CONFIG 0x0000013C\r |
3adf6316 MK |
375 | \r |
376 | /**\r | |
377 | MSR information returned for MSR index #MSR_XEON_PHI_FEATURE_CONFIG\r | |
378 | **/\r | |
379 | typedef union {\r | |
380 | ///\r | |
381 | /// Individual bit fields\r | |
382 | ///\r | |
383 | struct {\r | |
384 | ///\r | |
385 | /// [Bits 1:0] AES Configuration (RW-L) Upon a successful read of this\r | |
386 | /// MSR, the configuration of AES instruction set availability is as\r | |
387 | /// follows: 11b: AES instructions are not available until next RESET.\r | |
388 | /// otherwise, AES instructions are available. Note, AES instruction set\r | |
389 | /// is not available if read is unsuccessful. If the configuration is not\r | |
390 | /// 01b, AES instruction can be mis-configured if a privileged agent\r | |
391 | /// unintentionally writes 11b.\r | |
392 | ///\r | |
2f88bd3a MK |
393 | UINT32 AESConfiguration : 2;\r |
394 | UINT32 Reserved1 : 30;\r | |
395 | UINT32 Reserved2 : 32;\r | |
3adf6316 MK |
396 | } Bits;\r |
397 | ///\r | |
398 | /// All bit fields as a 32-bit value\r | |
399 | ///\r | |
2f88bd3a | 400 | UINT32 Uint32;\r |
3adf6316 MK |
401 | ///\r |
402 | /// All bit fields as a 64-bit value\r | |
403 | ///\r | |
2f88bd3a | 404 | UINT64 Uint64;\r |
3adf6316 MK |
405 | } MSR_XEON_PHI_FEATURE_CONFIG_REGISTER;\r |
406 | \r | |
dfb20851 ED |
407 | /**\r |
408 | Thread. MISC_FEATURE_ENABLES.\r | |
409 | \r | |
410 | @param ECX MSR_XEON_PHI_MISC_FEATURE_ENABLES (0x00000140)\r | |
411 | @param EAX Lower 32-bits of MSR value.\r | |
412 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
413 | @param EDX Upper 32-bits of MSR value.\r | |
414 | Described by the type MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER.\r | |
415 | \r | |
416 | <b>Example usage</b>\r | |
417 | @code\r | |
418 | MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER Msr;\r | |
419 | \r | |
420 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES);\r | |
421 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_ENABLES, Msr.Uint64);\r | |
422 | @endcode\r | |
423 | **/\r | |
2f88bd3a | 424 | #define MSR_XEON_PHI_MISC_FEATURE_ENABLES 0x00000140\r |
dfb20851 ED |
425 | \r |
426 | /**\r | |
427 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_ENABLES\r | |
428 | **/\r | |
429 | typedef union {\r | |
430 | ///\r | |
431 | /// Individual bit fields\r | |
432 | ///\r | |
433 | struct {\r | |
2f88bd3a | 434 | UINT32 Reserved1 : 1;\r |
dfb20851 ED |
435 | ///\r |
436 | /// [Bit 1] User Mode MONITOR and MWAIT (R/W) If set to 1, the MONITOR and\r | |
437 | /// MWAIT instructions do not cause invalid-opcode exceptions when\r | |
438 | /// executed with CPL > 0 or in virtual-8086 mode. If MWAIT is executed\r | |
439 | /// when CPL > 0 or in virtual-8086 mode, and if EAX indicates a C-state\r | |
440 | /// other than C0 or C1, the instruction operates as if EAX indicated the\r | |
441 | /// C-state C1.\r | |
442 | ///\r | |
2f88bd3a MK |
443 | UINT32 UserModeMonitorAndMwait : 1;\r |
444 | UINT32 Reserved2 : 30;\r | |
445 | UINT32 Reserved3 : 32;\r | |
dfb20851 ED |
446 | } Bits;\r |
447 | ///\r | |
448 | /// All bit fields as a 32-bit value\r | |
449 | ///\r | |
2f88bd3a | 450 | UINT32 Uint32;\r |
dfb20851 ED |
451 | ///\r |
452 | /// All bit fields as a 64-bit value\r | |
453 | ///\r | |
2f88bd3a | 454 | UINT64 Uint64;\r |
dfb20851 ED |
455 | } MSR_XEON_PHI_MISC_FEATURE_ENABLES_REGISTER;\r |
456 | \r | |
0f16be6d HW |
457 | /**\r |
458 | THREAD. Enhanced SMM Capabilities (SMM-RO) Reports SMM capability\r | |
459 | Enhancement. Accessible only while in SMM.\r | |
460 | \r | |
461 | @param ECX MSR_XEON_PHI_SMM_MCA_CAP (0x0000017D)\r | |
462 | @param EAX Lower 32-bits of MSR value.\r | |
463 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
464 | @param EDX Upper 32-bits of MSR value.\r | |
465 | Described by the type MSR_XEON_PHI_SMM_MCA_CAP_REGISTER.\r | |
466 | \r | |
467 | <b>Example usage</b>\r | |
468 | @code\r | |
469 | MSR_XEON_PHI_SMM_MCA_CAP_REGISTER Msr;\r | |
470 | \r | |
471 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_SMM_MCA_CAP);\r | |
472 | AsmWriteMsr64 (MSR_XEON_PHI_SMM_MCA_CAP, Msr.Uint64);\r | |
473 | @endcode\r | |
474 | @note MSR_XEON_PHI_SMM_MCA_CAP is defined as MSR_SMM_MCA_CAP in SDM.\r | |
475 | **/\r | |
2f88bd3a | 476 | #define MSR_XEON_PHI_SMM_MCA_CAP 0x0000017D\r |
0f16be6d HW |
477 | \r |
478 | /**\r | |
479 | MSR information returned for MSR index #MSR_XEON_PHI_SMM_MCA_CAP\r | |
480 | **/\r | |
481 | typedef union {\r | |
482 | ///\r | |
483 | /// Individual bit fields\r | |
484 | ///\r | |
485 | struct {\r | |
53002b7e ED |
486 | ///\r |
487 | /// [Bits 31:0] Bank Support (SMM-RO) One bit per MCA bank. If the bit is\r | |
488 | /// set, that bank supports Enhanced MCA (Default all 0; does not support\r | |
489 | /// EMCA).\r | |
490 | ///\r | |
2f88bd3a MK |
491 | UINT32 BankSupport : 32;\r |
492 | UINT32 Reserved4 : 24;\r | |
53002b7e ED |
493 | ///\r |
494 | /// [Bit 56] Targeted SMI (SMM-RO) Set if targeted SMI is supported.\r | |
495 | ///\r | |
2f88bd3a | 496 | UINT32 TargetedSMI : 1;\r |
53002b7e ED |
497 | ///\r |
498 | /// [Bit 57] SMM_CPU_SVRSTR (SMM-RO) Set if SMM SRAM save/restore feature\r | |
499 | /// is supported.\r | |
500 | ///\r | |
2f88bd3a | 501 | UINT32 SMM_CPU_SVRSTR : 1;\r |
0f16be6d HW |
502 | ///\r |
503 | /// [Bit 58] SMM_Code_Access_Chk (SMM-RO) If set to 1 indicates that the\r | |
504 | /// SMM code access restriction is supported and a host-space interface\r | |
505 | /// available to SMM handler.\r | |
506 | ///\r | |
2f88bd3a | 507 | UINT32 SMM_Code_Access_Chk : 1;\r |
0f16be6d HW |
508 | ///\r |
509 | /// [Bit 59] Long_Flow_Indication (SMM-RO) If set to 1 indicates that the\r | |
510 | /// SMM long flow indicator is supported and a host-space interface\r | |
511 | /// available to SMM handler.\r | |
512 | ///\r | |
2f88bd3a MK |
513 | UINT32 Long_Flow_Indication : 1;\r |
514 | UINT32 Reserved3 : 4;\r | |
0f16be6d HW |
515 | } Bits;\r |
516 | ///\r | |
517 | /// All bit fields as a 64-bit value\r | |
518 | ///\r | |
2f88bd3a | 519 | UINT64 Uint64;\r |
0f16be6d HW |
520 | } MSR_XEON_PHI_SMM_MCA_CAP_REGISTER;\r |
521 | \r | |
3adf6316 MK |
522 | /**\r |
523 | Thread. Enable Misc. Processor Features (R/W) Allows a variety of processor\r | |
524 | functions to be enabled and disabled.\r | |
525 | \r | |
526 | @param ECX MSR_XEON_PHI_IA32_MISC_ENABLE (0x000001A0)\r | |
527 | @param EAX Lower 32-bits of MSR value.\r | |
528 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
529 | @param EDX Upper 32-bits of MSR value.\r | |
530 | Described by the type MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER.\r | |
531 | \r | |
532 | <b>Example usage</b>\r | |
533 | @code\r | |
534 | MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER Msr;\r | |
535 | \r | |
536 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE);\r | |
537 | AsmWriteMsr64 (MSR_XEON_PHI_IA32_MISC_ENABLE, Msr.Uint64);\r | |
538 | @endcode\r | |
ad8a2f5e | 539 | @note MSR_XEON_PHI_IA32_MISC_ENABLE is defined as IA32_MISC_ENABLE in SDM.\r |
3adf6316 | 540 | **/\r |
2f88bd3a | 541 | #define MSR_XEON_PHI_IA32_MISC_ENABLE 0x000001A0\r |
3adf6316 MK |
542 | \r |
543 | /**\r | |
544 | MSR information returned for MSR index #MSR_XEON_PHI_IA32_MISC_ENABLE\r | |
545 | **/\r | |
546 | typedef union {\r | |
547 | ///\r | |
548 | /// Individual bit fields\r | |
549 | ///\r | |
550 | struct {\r | |
551 | ///\r | |
552 | /// [Bit 0] Fast-Strings Enable.\r | |
553 | ///\r | |
2f88bd3a MK |
554 | UINT32 FastStrings : 1;\r |
555 | UINT32 Reserved1 : 2;\r | |
3adf6316 | 556 | ///\r |
0f16be6d HW |
557 | /// [Bit 3] Automatic Thermal Control Circuit Enable (R/W) Default value\r |
558 | /// is 1.\r | |
3adf6316 | 559 | ///\r |
2f88bd3a MK |
560 | UINT32 AutomaticThermalControlCircuit : 1;\r |
561 | UINT32 Reserved2 : 3;\r | |
3adf6316 MK |
562 | ///\r |
563 | /// [Bit 7] Performance Monitoring Available (R).\r | |
564 | ///\r | |
2f88bd3a MK |
565 | UINT32 PerformanceMonitoring : 1;\r |
566 | UINT32 Reserved3 : 3;\r | |
3adf6316 MK |
567 | ///\r |
568 | /// [Bit 11] Branch Trace Storage Unavailable (RO).\r | |
569 | ///\r | |
2f88bd3a | 570 | UINT32 BTS : 1;\r |
3adf6316 | 571 | ///\r |
0f16be6d | 572 | /// [Bit 12] Processor Event Based Sampling Unavailable (RO).\r |
3adf6316 | 573 | ///\r |
2f88bd3a MK |
574 | UINT32 PEBS : 1;\r |
575 | UINT32 Reserved4 : 3;\r | |
3adf6316 MK |
576 | ///\r |
577 | /// [Bit 16] Enhanced Intel SpeedStep Technology Enable (R/W).\r | |
578 | ///\r | |
2f88bd3a MK |
579 | UINT32 EIST : 1;\r |
580 | UINT32 Reserved5 : 1;\r | |
3adf6316 MK |
581 | ///\r |
582 | /// [Bit 18] ENABLE MONITOR FSM (R/W).\r | |
583 | ///\r | |
2f88bd3a MK |
584 | UINT32 MONITOR : 1;\r |
585 | UINT32 Reserved6 : 3;\r | |
3adf6316 MK |
586 | ///\r |
587 | /// [Bit 22] Limit CPUID Maxval (R/W).\r | |
588 | ///\r | |
2f88bd3a | 589 | UINT32 LimitCpuidMaxval : 1;\r |
3adf6316 MK |
590 | ///\r |
591 | /// [Bit 23] xTPR Message Disable (R/W).\r | |
592 | ///\r | |
2f88bd3a MK |
593 | UINT32 xTPR_Message_Disable : 1;\r |
594 | UINT32 Reserved7 : 8;\r | |
595 | UINT32 Reserved8 : 2;\r | |
3adf6316 MK |
596 | ///\r |
597 | /// [Bit 34] XD Bit Disable (R/W).\r | |
598 | ///\r | |
2f88bd3a MK |
599 | UINT32 XD : 1;\r |
600 | UINT32 Reserved9 : 3;\r | |
3adf6316 MK |
601 | ///\r |
602 | /// [Bit 38] Turbo Mode Disable (R/W).\r | |
603 | ///\r | |
2f88bd3a MK |
604 | UINT32 TurboModeDisable : 1;\r |
605 | UINT32 Reserved10 : 25;\r | |
3adf6316 MK |
606 | } Bits;\r |
607 | ///\r | |
608 | /// All bit fields as a 64-bit value\r | |
609 | ///\r | |
2f88bd3a | 610 | UINT64 Uint64;\r |
3adf6316 MK |
611 | } MSR_XEON_PHI_IA32_MISC_ENABLE_REGISTER;\r |
612 | \r | |
3adf6316 MK |
613 | /**\r |
614 | Package.\r | |
615 | \r | |
616 | @param ECX MSR_XEON_PHI_TEMPERATURE_TARGET (0x000001A2)\r | |
617 | @param EAX Lower 32-bits of MSR value.\r | |
618 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
619 | @param EDX Upper 32-bits of MSR value.\r | |
620 | Described by the type MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER.\r | |
621 | \r | |
622 | <b>Example usage</b>\r | |
623 | @code\r | |
624 | MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER Msr;\r | |
625 | \r | |
626 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET);\r | |
627 | AsmWriteMsr64 (MSR_XEON_PHI_TEMPERATURE_TARGET, Msr.Uint64);\r | |
628 | @endcode\r | |
ad8a2f5e | 629 | @note MSR_XEON_PHI_TEMPERATURE_TARGET is defined as MSR_TEMPERATURE_TARGET in SDM.\r |
3adf6316 | 630 | **/\r |
2f88bd3a | 631 | #define MSR_XEON_PHI_TEMPERATURE_TARGET 0x000001A2\r |
3adf6316 MK |
632 | \r |
633 | /**\r | |
634 | MSR information returned for MSR index #MSR_XEON_PHI_TEMPERATURE_TARGET\r | |
635 | **/\r | |
636 | typedef union {\r | |
637 | ///\r | |
638 | /// Individual bit fields\r | |
639 | ///\r | |
640 | struct {\r | |
2f88bd3a | 641 | UINT32 Reserved1 : 16;\r |
3adf6316 MK |
642 | ///\r |
643 | /// [Bits 23:16] Temperature Target (R).\r | |
644 | ///\r | |
2f88bd3a | 645 | UINT32 TemperatureTarget : 8;\r |
3adf6316 MK |
646 | ///\r |
647 | /// [Bits 29:24] Target Offset (R/W).\r | |
648 | ///\r | |
2f88bd3a MK |
649 | UINT32 TargetOffset : 6;\r |
650 | UINT32 Reserved2 : 2;\r | |
651 | UINT32 Reserved3 : 32;\r | |
3adf6316 MK |
652 | } Bits;\r |
653 | ///\r | |
654 | /// All bit fields as a 32-bit value\r | |
655 | ///\r | |
2f88bd3a | 656 | UINT32 Uint32;\r |
3adf6316 MK |
657 | ///\r |
658 | /// All bit fields as a 64-bit value\r | |
659 | ///\r | |
2f88bd3a | 660 | UINT64 Uint64;\r |
3adf6316 MK |
661 | } MSR_XEON_PHI_TEMPERATURE_TARGET_REGISTER;\r |
662 | \r | |
0f16be6d HW |
663 | /**\r |
664 | Miscellaneous Feature Control (R/W).\r | |
665 | \r | |
666 | @param ECX MSR_XEON_PHI_MISC_FEATURE_CONTROL (0x000001A4)\r | |
667 | @param EAX Lower 32-bits of MSR value.\r | |
668 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
669 | @param EDX Upper 32-bits of MSR value.\r | |
670 | Described by the type MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER.\r | |
671 | \r | |
672 | <b>Example usage</b>\r | |
673 | @code\r | |
674 | MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER Msr;\r | |
675 | \r | |
676 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL);\r | |
677 | AsmWriteMsr64 (MSR_XEON_PHI_MISC_FEATURE_CONTROL, Msr.Uint64);\r | |
678 | @endcode\r | |
679 | @note MSR_XEON_PHI_MISC_FEATURE_CONTROL is defined as MSR_MISC_FEATURE_CONTROL in SDM.\r | |
680 | **/\r | |
2f88bd3a | 681 | #define MSR_XEON_PHI_MISC_FEATURE_CONTROL 0x000001A4\r |
0f16be6d HW |
682 | \r |
683 | /**\r | |
684 | MSR information returned for MSR index #MSR_XEON_PHI_MISC_FEATURE_CONTROL\r | |
685 | **/\r | |
686 | typedef union {\r | |
687 | ///\r | |
688 | /// Individual bit fields\r | |
689 | ///\r | |
690 | struct {\r | |
691 | ///\r | |
692 | /// [Bit 0] Core. DCU Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
693 | /// L1 data cache prefetcher.\r | |
694 | ///\r | |
2f88bd3a | 695 | UINT32 DCUHardwarePrefetcherDisable : 1;\r |
0f16be6d HW |
696 | ///\r |
697 | /// [Bit 1] Core. L2 Hardware Prefetcher Disable (R/W) If 1, disables the\r | |
698 | /// L2 hardware prefetcher.\r | |
699 | ///\r | |
2f88bd3a MK |
700 | UINT32 L2HardwarePrefetcherDisable : 1;\r |
701 | UINT32 Reserved1 : 30;\r | |
702 | UINT32 Reserved2 : 32;\r | |
0f16be6d HW |
703 | } Bits;\r |
704 | ///\r | |
705 | /// All bit fields as a 32-bit value\r | |
706 | ///\r | |
2f88bd3a | 707 | UINT32 Uint32;\r |
0f16be6d HW |
708 | ///\r |
709 | /// All bit fields as a 64-bit value\r | |
710 | ///\r | |
2f88bd3a | 711 | UINT64 Uint64;\r |
0f16be6d HW |
712 | } MSR_XEON_PHI_MISC_FEATURE_CONTROL_REGISTER;\r |
713 | \r | |
3adf6316 MK |
714 | /**\r |
715 | Shared. Offcore Response Event Select Register (R/W).\r | |
716 | \r | |
717 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_0 (0x000001A6)\r | |
718 | @param EAX Lower 32-bits of MSR value.\r | |
719 | @param EDX Upper 32-bits of MSR value.\r | |
720 | \r | |
721 | <b>Example usage</b>\r | |
722 | @code\r | |
723 | UINT64 Msr;\r | |
724 | \r | |
725 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0);\r | |
726 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_0, Msr);\r | |
727 | @endcode\r | |
ad8a2f5e | 728 | @note MSR_XEON_PHI_OFFCORE_RSP_0 is defined as MSR_OFFCORE_RSP_0 in SDM.\r |
3adf6316 | 729 | **/\r |
2f88bd3a | 730 | #define MSR_XEON_PHI_OFFCORE_RSP_0 0x000001A6\r |
3adf6316 MK |
731 | \r |
732 | /**\r | |
733 | Shared. Offcore Response Event Select Register (R/W).\r | |
734 | \r | |
735 | @param ECX MSR_XEON_PHI_OFFCORE_RSP_1 (0x000001A7)\r | |
736 | @param EAX Lower 32-bits of MSR value.\r | |
737 | @param EDX Upper 32-bits of MSR value.\r | |
738 | \r | |
739 | <b>Example usage</b>\r | |
740 | @code\r | |
741 | UINT64 Msr;\r | |
742 | \r | |
743 | Msr = AsmReadMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1);\r | |
744 | AsmWriteMsr64 (MSR_XEON_PHI_OFFCORE_RSP_1, Msr);\r | |
745 | @endcode\r | |
ad8a2f5e | 746 | @note MSR_XEON_PHI_OFFCORE_RSP_1 is defined as MSR_OFFCORE_RSP_1 in SDM.\r |
3adf6316 | 747 | **/\r |
2f88bd3a | 748 | #define MSR_XEON_PHI_OFFCORE_RSP_1 0x000001A7\r |
3adf6316 MK |
749 | \r |
750 | /**\r | |
751 | Package. Maximum Ratio Limit of Turbo Mode for Groups of Cores (RW).\r | |
752 | \r | |
753 | @param ECX MSR_XEON_PHI_TURBO_RATIO_LIMIT (0x000001AD)\r | |
754 | @param EAX Lower 32-bits of MSR value.\r | |
755 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
756 | @param EDX Upper 32-bits of MSR value.\r | |
757 | Described by the type MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER.\r | |
758 | \r | |
759 | <b>Example usage</b>\r | |
760 | @code\r | |
761 | MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER Msr;\r | |
762 | \r | |
763 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT);\r | |
764 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_RATIO_LIMIT, Msr.Uint64);\r | |
765 | @endcode\r | |
ad8a2f5e | 766 | @note MSR_XEON_PHI_TURBO_RATIO_LIMIT is defined as MSR_TURBO_RATIO_LIMIT in SDM.\r |
3adf6316 | 767 | **/\r |
2f88bd3a | 768 | #define MSR_XEON_PHI_TURBO_RATIO_LIMIT 0x000001AD\r |
3adf6316 MK |
769 | \r |
770 | /**\r | |
771 | MSR information returned for MSR index #MSR_XEON_PHI_TURBO_RATIO_LIMIT\r | |
772 | **/\r | |
773 | typedef union {\r | |
774 | ///\r | |
775 | /// Individual bit fields\r | |
776 | ///\r | |
777 | struct {\r | |
2f88bd3a | 778 | UINT32 Reserved : 1;\r |
3adf6316 MK |
779 | ///\r |
780 | /// [Bits 7:1] Package. Maximum Number of Cores in Group 0 Number active\r | |
781 | /// processor cores which operates under the maximum ratio limit for group\r | |
782 | /// 0.\r | |
783 | ///\r | |
2f88bd3a | 784 | UINT32 MaxCoresGroup0 : 7;\r |
3adf6316 MK |
785 | ///\r |
786 | /// [Bits 15:8] Package. Maximum Ratio Limit for Group 0 Maximum turbo\r | |
787 | /// ratio limit when the number of active cores are not more than the\r | |
788 | /// group 0 maximum core count.\r | |
789 | ///\r | |
2f88bd3a | 790 | UINT32 MaxRatioLimitGroup0 : 8;\r |
3adf6316 MK |
791 | ///\r |
792 | /// [Bits 20:16] Package. Number of Incremental Cores Added to Group 1\r | |
793 | /// Group 1, which includes the specified number of additional cores plus\r | |
794 | /// the cores in group 0, operates under the group 1 turbo max ratio limit\r | |
795 | /// = "group 0 Max ratio limit" - "group ratio delta for group 1".\r | |
796 | ///\r | |
2f88bd3a | 797 | UINT32 MaxIncrementalCoresGroup1 : 5;\r |
3adf6316 MK |
798 | ///\r |
799 | /// [Bits 23:21] Package. Group Ratio Delta for Group 1 An unsigned\r | |
800 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
801 | /// to Group 0.\r | |
802 | ///\r | |
2f88bd3a | 803 | UINT32 DeltaRatioGroup1 : 3;\r |
3adf6316 MK |
804 | ///\r |
805 | /// [Bits 28:24] Package. Number of Incremental Cores Added to Group 2\r | |
806 | /// Group 2, which includes the specified number of additional cores plus\r | |
807 | /// all the cores in group 1, operates under the group 2 turbo max ratio\r | |
808 | /// limit = "group 1 Max ratio limit" - "group ratio delta for group 2".\r | |
809 | ///\r | |
2f88bd3a | 810 | UINT32 MaxIncrementalCoresGroup2 : 5;\r |
3adf6316 MK |
811 | ///\r |
812 | /// [Bits 31:29] Package. Group Ratio Delta for Group 2 An unsigned\r | |
813 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
814 | /// for Group 1.\r | |
815 | ///\r | |
2f88bd3a | 816 | UINT32 DeltaRatioGroup2 : 3;\r |
3adf6316 MK |
817 | ///\r |
818 | /// [Bits 36:32] Package. Number of Incremental Cores Added to Group 3\r | |
819 | /// Group 3, which includes the specified number of additional cores plus\r | |
820 | /// all the cores in group 2, operates under the group 3 turbo max ratio\r | |
821 | /// limit = "group 2 Max ratio limit" - "group ratio delta for group 3".\r | |
822 | ///\r | |
2f88bd3a | 823 | UINT32 MaxIncrementalCoresGroup3 : 5;\r |
3adf6316 MK |
824 | ///\r |
825 | /// [Bits 39:37] Package. Group Ratio Delta for Group 3 An unsigned\r | |
826 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
827 | /// for Group 2.\r | |
828 | ///\r | |
2f88bd3a | 829 | UINT32 DeltaRatioGroup3 : 3;\r |
3adf6316 MK |
830 | ///\r |
831 | /// [Bits 44:40] Package. Number of Incremental Cores Added to Group 4\r | |
832 | /// Group 4, which includes the specified number of additional cores plus\r | |
833 | /// all the cores in group 3, operates under the group 4 turbo max ratio\r | |
834 | /// limit = "group 3 Max ratio limit" - "group ratio delta for group 4".\r | |
835 | ///\r | |
2f88bd3a | 836 | UINT32 MaxIncrementalCoresGroup4 : 5;\r |
3adf6316 MK |
837 | ///\r |
838 | /// [Bits 47:45] Package. Group Ratio Delta for Group 4 An unsigned\r | |
839 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
840 | /// for Group 3.\r | |
841 | ///\r | |
2f88bd3a | 842 | UINT32 DeltaRatioGroup4 : 3;\r |
3adf6316 MK |
843 | ///\r |
844 | /// [Bits 52:48] Package. Number of Incremental Cores Added to Group 5\r | |
845 | /// Group 5, which includes the specified number of additional cores plus\r | |
846 | /// all the cores in group 4, operates under the group 5 turbo max ratio\r | |
847 | /// limit = "group 4 Max ratio limit" - "group ratio delta for group 5".\r | |
848 | ///\r | |
2f88bd3a | 849 | UINT32 MaxIncrementalCoresGroup5 : 5;\r |
3adf6316 MK |
850 | ///\r |
851 | /// [Bits 55:53] Package. Group Ratio Delta for Group 5 An unsigned\r | |
852 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
853 | /// for Group 4.\r | |
854 | ///\r | |
2f88bd3a | 855 | UINT32 DeltaRatioGroup5 : 3;\r |
3adf6316 MK |
856 | ///\r |
857 | /// [Bits 60:56] Package. Number of Incremental Cores Added to Group 6\r | |
858 | /// Group 6, which includes the specified number of additional cores plus\r | |
859 | /// all the cores in group 5, operates under the group 6 turbo max ratio\r | |
860 | /// limit = "group 5 Max ratio limit" - "group ratio delta for group 6".\r | |
861 | ///\r | |
2f88bd3a | 862 | UINT32 MaxIncrementalCoresGroup6 : 5;\r |
3adf6316 MK |
863 | ///\r |
864 | /// [Bits 63:61] Package. Group Ratio Delta for Group 6 An unsigned\r | |
865 | /// integer specifying the ratio decrement relative to the Max ratio limit\r | |
866 | /// for Group 5.\r | |
867 | ///\r | |
2f88bd3a | 868 | UINT32 DeltaRatioGroup6 : 3;\r |
3adf6316 MK |
869 | } Bits;\r |
870 | ///\r | |
871 | /// All bit fields as a 64-bit value\r | |
872 | ///\r | |
2f88bd3a | 873 | UINT64 Uint64;\r |
3adf6316 MK |
874 | } MSR_XEON_PHI_TURBO_RATIO_LIMIT_REGISTER;\r |
875 | \r | |
3adf6316 MK |
876 | /**\r |
877 | Thread. Last Branch Record Filtering Select Register (R/W).\r | |
878 | \r | |
879 | @param ECX MSR_XEON_PHI_LBR_SELECT (0x000001C8)\r | |
880 | @param EAX Lower 32-bits of MSR value.\r | |
881 | @param EDX Upper 32-bits of MSR value.\r | |
882 | \r | |
883 | <b>Example usage</b>\r | |
884 | @code\r | |
885 | UINT64 Msr;\r | |
886 | \r | |
887 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LBR_SELECT);\r | |
888 | AsmWriteMsr64 (MSR_XEON_PHI_LBR_SELECT, Msr);\r | |
889 | @endcode\r | |
ad8a2f5e | 890 | @note MSR_XEON_PHI_LBR_SELECT is defined as MSR_LBR_SELECT in SDM.\r |
3adf6316 | 891 | **/\r |
2f88bd3a | 892 | #define MSR_XEON_PHI_LBR_SELECT 0x000001C8\r |
3adf6316 | 893 | \r |
dfb20851 ED |
894 | /**\r |
895 | MSR information returned for MSR index #MSR_XEON_PHI_LBR_SELECT\r | |
896 | **/\r | |
897 | typedef union {\r | |
898 | ///\r | |
899 | /// Individual bit fields\r | |
900 | ///\r | |
901 | struct {\r | |
902 | ///\r | |
903 | /// [Bit 0] CPL_EQ_0.\r | |
904 | ///\r | |
2f88bd3a | 905 | UINT32 CPL_EQ_0 : 1;\r |
dfb20851 ED |
906 | ///\r |
907 | /// [Bit 1] CPL_NEQ_0.\r | |
908 | ///\r | |
2f88bd3a | 909 | UINT32 CPL_NEQ_0 : 1;\r |
dfb20851 ED |
910 | ///\r |
911 | /// [Bit 2] JCC.\r | |
912 | ///\r | |
2f88bd3a | 913 | UINT32 JCC : 1;\r |
dfb20851 ED |
914 | ///\r |
915 | /// [Bit 3] NEAR_REL_CALL.\r | |
916 | ///\r | |
2f88bd3a | 917 | UINT32 NEAR_REL_CALL : 1;\r |
dfb20851 ED |
918 | ///\r |
919 | /// [Bit 4] NEAR_IND_CALL.\r | |
920 | ///\r | |
2f88bd3a | 921 | UINT32 NEAR_IND_CALL : 1;\r |
dfb20851 ED |
922 | ///\r |
923 | /// [Bit 5] NEAR_RET.\r | |
924 | ///\r | |
2f88bd3a | 925 | UINT32 NEAR_RET : 1;\r |
dfb20851 ED |
926 | ///\r |
927 | /// [Bit 6] NEAR_IND_JMP.\r | |
928 | ///\r | |
2f88bd3a | 929 | UINT32 NEAR_IND_JMP : 1;\r |
dfb20851 ED |
930 | ///\r |
931 | /// [Bit 7] NEAR_REL_JMP.\r | |
932 | ///\r | |
2f88bd3a | 933 | UINT32 NEAR_REL_JMP : 1;\r |
dfb20851 ED |
934 | ///\r |
935 | /// [Bit 8] FAR_BRANCH.\r | |
936 | ///\r | |
2f88bd3a MK |
937 | UINT32 FAR_BRANCH : 1;\r |
938 | UINT32 Reserved1 : 23;\r | |
939 | UINT32 Reserved2 : 32;\r | |
dfb20851 ED |
940 | } Bits;\r |
941 | ///\r | |
942 | /// All bit fields as a 32-bit value\r | |
943 | ///\r | |
2f88bd3a | 944 | UINT32 Uint32;\r |
dfb20851 ED |
945 | ///\r |
946 | /// All bit fields as a 64-bit value\r | |
947 | ///\r | |
2f88bd3a | 948 | UINT64 Uint64;\r |
dfb20851 ED |
949 | } MSR_XEON_PHI_LBR_SELECT_REGISTER;\r |
950 | \r | |
3adf6316 MK |
951 | /**\r |
952 | Thread. Last Branch Record Stack TOS (R/W).\r | |
953 | \r | |
954 | @param ECX MSR_XEON_PHI_LASTBRANCH_TOS (0x000001C9)\r | |
955 | @param EAX Lower 32-bits of MSR value.\r | |
956 | @param EDX Upper 32-bits of MSR value.\r | |
957 | \r | |
958 | <b>Example usage</b>\r | |
959 | @code\r | |
960 | UINT64 Msr;\r | |
961 | \r | |
962 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS);\r | |
963 | AsmWriteMsr64 (MSR_XEON_PHI_LASTBRANCH_TOS, Msr);\r | |
964 | @endcode\r | |
ad8a2f5e | 965 | @note MSR_XEON_PHI_LASTBRANCH_TOS is defined as MSR_LASTBRANCH_TOS in SDM.\r |
3adf6316 | 966 | **/\r |
2f88bd3a | 967 | #define MSR_XEON_PHI_LASTBRANCH_TOS 0x000001C9\r |
3adf6316 MK |
968 | \r |
969 | /**\r | |
970 | Thread. Last Exception Record From Linear IP (R).\r | |
971 | \r | |
972 | @param ECX MSR_XEON_PHI_LER_FROM_LIP (0x000001DD)\r | |
973 | @param EAX Lower 32-bits of MSR value.\r | |
974 | @param EDX Upper 32-bits of MSR value.\r | |
975 | \r | |
976 | <b>Example usage</b>\r | |
977 | @code\r | |
978 | UINT64 Msr;\r | |
979 | \r | |
980 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_FROM_LIP);\r | |
981 | @endcode\r | |
ad8a2f5e | 982 | @note MSR_XEON_PHI_LER_FROM_LIP is defined as MSR_LER_FROM_LIP in SDM.\r |
3adf6316 | 983 | **/\r |
2f88bd3a | 984 | #define MSR_XEON_PHI_LER_FROM_LIP 0x000001DD\r |
3adf6316 MK |
985 | \r |
986 | /**\r | |
987 | Thread. Last Exception Record To Linear IP (R).\r | |
988 | \r | |
989 | @param ECX MSR_XEON_PHI_LER_TO_LIP (0x000001DE)\r | |
990 | @param EAX Lower 32-bits of MSR value.\r | |
991 | @param EDX Upper 32-bits of MSR value.\r | |
992 | \r | |
993 | <b>Example usage</b>\r | |
994 | @code\r | |
995 | UINT64 Msr;\r | |
996 | \r | |
997 | Msr = AsmReadMsr64 (MSR_XEON_PHI_LER_TO_LIP);\r | |
998 | @endcode\r | |
ad8a2f5e | 999 | @note MSR_XEON_PHI_LER_TO_LIP is defined as MSR_LER_TO_LIP in SDM.\r |
3adf6316 | 1000 | **/\r |
2f88bd3a | 1001 | #define MSR_XEON_PHI_LER_TO_LIP 0x000001DE\r |
3adf6316 | 1002 | \r |
3adf6316 | 1003 | /**\r |
ba1a2d11 | 1004 | Thread. See Table 2-2.\r |
3adf6316 MK |
1005 | \r |
1006 | @param ECX MSR_XEON_PHI_PEBS_ENABLE (0x000003F1)\r | |
1007 | @param EAX Lower 32-bits of MSR value.\r | |
1008 | @param EDX Upper 32-bits of MSR value.\r | |
1009 | \r | |
1010 | <b>Example usage</b>\r | |
1011 | @code\r | |
1012 | UINT64 Msr;\r | |
1013 | \r | |
1014 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PEBS_ENABLE);\r | |
1015 | AsmWriteMsr64 (MSR_XEON_PHI_PEBS_ENABLE, Msr);\r | |
1016 | @endcode\r | |
ad8a2f5e | 1017 | @note MSR_XEON_PHI_PEBS_ENABLE is defined as MSR_PEBS_ENABLE in SDM.\r |
3adf6316 | 1018 | **/\r |
2f88bd3a | 1019 | #define MSR_XEON_PHI_PEBS_ENABLE 0x000003F1\r |
3adf6316 MK |
1020 | \r |
1021 | /**\r | |
1022 | Package. Note: C-state values are processor specific C-state code names,\r | |
1023 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C3\r | |
1024 | Residency Counter. (R/O).\r | |
1025 | \r | |
1026 | @param ECX MSR_XEON_PHI_PKG_C3_RESIDENCY (0x000003F8)\r | |
1027 | @param EAX Lower 32-bits of MSR value.\r | |
1028 | @param EDX Upper 32-bits of MSR value.\r | |
1029 | \r | |
1030 | <b>Example usage</b>\r | |
1031 | @code\r | |
1032 | UINT64 Msr;\r | |
1033 | \r | |
1034 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY);\r | |
1035 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C3_RESIDENCY, Msr);\r | |
1036 | @endcode\r | |
ad8a2f5e | 1037 | @note MSR_XEON_PHI_PKG_C3_RESIDENCY is defined as MSR_PKG_C3_RESIDENCY in SDM.\r |
3adf6316 | 1038 | **/\r |
2f88bd3a | 1039 | #define MSR_XEON_PHI_PKG_C3_RESIDENCY 0x000003F8\r |
3adf6316 MK |
1040 | \r |
1041 | /**\r | |
1042 | Package. Package C6 Residency Counter. (R/O).\r | |
1043 | \r | |
1044 | @param ECX MSR_XEON_PHI_PKG_C6_RESIDENCY (0x000003F9)\r | |
1045 | @param EAX Lower 32-bits of MSR value.\r | |
1046 | @param EDX Upper 32-bits of MSR value.\r | |
1047 | \r | |
1048 | <b>Example usage</b>\r | |
1049 | @code\r | |
1050 | UINT64 Msr;\r | |
1051 | \r | |
1052 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY);\r | |
1053 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C6_RESIDENCY, Msr);\r | |
1054 | @endcode\r | |
ad8a2f5e | 1055 | @note MSR_XEON_PHI_PKG_C6_RESIDENCY is defined as MSR_PKG_C6_RESIDENCY in SDM.\r |
3adf6316 | 1056 | **/\r |
2f88bd3a | 1057 | #define MSR_XEON_PHI_PKG_C6_RESIDENCY 0x000003F9\r |
3adf6316 MK |
1058 | \r |
1059 | /**\r | |
1060 | Package. Package C7 Residency Counter. (R/O).\r | |
1061 | \r | |
1062 | @param ECX MSR_XEON_PHI_PKG_C7_RESIDENCY (0x000003FA)\r | |
1063 | @param EAX Lower 32-bits of MSR value.\r | |
1064 | @param EDX Upper 32-bits of MSR value.\r | |
1065 | \r | |
1066 | <b>Example usage</b>\r | |
1067 | @code\r | |
1068 | UINT64 Msr;\r | |
1069 | \r | |
1070 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY);\r | |
1071 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C7_RESIDENCY, Msr);\r | |
1072 | @endcode\r | |
ad8a2f5e | 1073 | @note MSR_XEON_PHI_PKG_C7_RESIDENCY is defined as MSR_PKG_C7_RESIDENCY in SDM.\r |
3adf6316 | 1074 | **/\r |
2f88bd3a | 1075 | #define MSR_XEON_PHI_PKG_C7_RESIDENCY 0x000003FA\r |
3adf6316 MK |
1076 | \r |
1077 | /**\r | |
1078 | Module. Note: C-state values are processor specific C-state code names,\r | |
1079 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Module C0\r | |
1080 | Residency Counter. (R/O).\r | |
1081 | \r | |
1082 | @param ECX MSR_XEON_PHI_MC0_RESIDENCY (0x000003FC)\r | |
1083 | @param EAX Lower 32-bits of MSR value.\r | |
1084 | @param EDX Upper 32-bits of MSR value.\r | |
1085 | \r | |
1086 | <b>Example usage</b>\r | |
1087 | @code\r | |
1088 | UINT64 Msr;\r | |
1089 | \r | |
1090 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC0_RESIDENCY);\r | |
1091 | AsmWriteMsr64 (MSR_XEON_PHI_MC0_RESIDENCY, Msr);\r | |
1092 | @endcode\r | |
ad8a2f5e | 1093 | @note MSR_XEON_PHI_MC0_RESIDENCY is defined as MSR_MC0_RESIDENCY in SDM.\r |
3adf6316 | 1094 | **/\r |
2f88bd3a | 1095 | #define MSR_XEON_PHI_MC0_RESIDENCY 0x000003FC\r |
3adf6316 MK |
1096 | \r |
1097 | /**\r | |
1098 | Module. Module C6 Residency Counter. (R/O).\r | |
1099 | \r | |
1100 | @param ECX MSR_XEON_PHI_MC6_RESIDENCY (0x000003FD)\r | |
1101 | @param EAX Lower 32-bits of MSR value.\r | |
1102 | @param EDX Upper 32-bits of MSR value.\r | |
1103 | \r | |
1104 | <b>Example usage</b>\r | |
1105 | @code\r | |
1106 | UINT64 Msr;\r | |
1107 | \r | |
1108 | Msr = AsmReadMsr64 (MSR_XEON_PHI_MC6_RESIDENCY);\r | |
1109 | AsmWriteMsr64 (MSR_XEON_PHI_MC6_RESIDENCY, Msr);\r | |
1110 | @endcode\r | |
ad8a2f5e | 1111 | @note MSR_XEON_PHI_MC6_RESIDENCY is defined as MSR_MC6_RESIDENCY in SDM.\r |
3adf6316 | 1112 | **/\r |
2f88bd3a | 1113 | #define MSR_XEON_PHI_MC6_RESIDENCY 0x000003FD\r |
3adf6316 MK |
1114 | \r |
1115 | /**\r | |
1116 | Core. Note: C-state values are processor specific C-state code names,\r | |
1117 | unrelated to MWAIT extension C-state parameters or ACPI C-States. CORE C6\r | |
1118 | Residency Counter. (R/O).\r | |
1119 | \r | |
1120 | @param ECX MSR_XEON_PHI_CORE_C6_RESIDENCY (0x000003FF)\r | |
1121 | @param EAX Lower 32-bits of MSR value.\r | |
1122 | @param EDX Upper 32-bits of MSR value.\r | |
1123 | \r | |
1124 | <b>Example usage</b>\r | |
1125 | @code\r | |
1126 | UINT64 Msr;\r | |
1127 | \r | |
1128 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY);\r | |
1129 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_C6_RESIDENCY, Msr);\r | |
1130 | @endcode\r | |
ad8a2f5e | 1131 | @note MSR_XEON_PHI_CORE_C6_RESIDENCY is defined as MSR_CORE_C6_RESIDENCY in SDM.\r |
3adf6316 | 1132 | **/\r |
2f88bd3a | 1133 | #define MSR_XEON_PHI_CORE_C6_RESIDENCY 0x000003FF\r |
3adf6316 | 1134 | \r |
3adf6316 | 1135 | /**\r |
ba1a2d11 | 1136 | Core. Capability Reporting Register of EPT and VPID (R/O) See Table 2-2.\r |
3adf6316 MK |
1137 | \r |
1138 | @param ECX MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM (0x0000048C)\r | |
1139 | @param EAX Lower 32-bits of MSR value.\r | |
1140 | @param EDX Upper 32-bits of MSR value.\r | |
1141 | \r | |
1142 | <b>Example usage</b>\r | |
1143 | @code\r | |
1144 | UINT64 Msr;\r | |
1145 | \r | |
1146 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM);\r | |
1147 | @endcode\r | |
ad8a2f5e | 1148 | @note MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM is defined as IA32_VMX_EPT_VPID_ENUM in SDM.\r |
3adf6316 | 1149 | **/\r |
2f88bd3a | 1150 | #define MSR_XEON_PHI_IA32_VMX_EPT_VPID_ENUM 0x0000048C\r |
3adf6316 MK |
1151 | \r |
1152 | /**\r | |
ba1a2d11 ED |
1153 | Core. Capability Reporting Register of VM-Function Controls (R/O) See Table\r |
1154 | 2-2.\r | |
3adf6316 MK |
1155 | \r |
1156 | @param ECX MSR_XEON_PHI_IA32_VMX_FMFUNC (0x00000491)\r | |
1157 | @param EAX Lower 32-bits of MSR value.\r | |
1158 | @param EDX Upper 32-bits of MSR value.\r | |
1159 | \r | |
1160 | <b>Example usage</b>\r | |
1161 | @code\r | |
1162 | UINT64 Msr;\r | |
1163 | \r | |
1164 | Msr = AsmReadMsr64 (MSR_XEON_PHI_IA32_VMX_FMFUNC);\r | |
1165 | @endcode\r | |
ad8a2f5e | 1166 | @note MSR_XEON_PHI_IA32_VMX_FMFUNC is defined as IA32_VMX_FMFUNC in SDM.\r |
3adf6316 | 1167 | **/\r |
2f88bd3a | 1168 | #define MSR_XEON_PHI_IA32_VMX_FMFUNC 0x00000491\r |
3adf6316 MK |
1169 | \r |
1170 | /**\r | |
1171 | Package. Unit Multipliers used in RAPL Interfaces (R/O).\r | |
1172 | \r | |
1173 | @param ECX MSR_XEON_PHI_RAPL_POWER_UNIT (0x00000606)\r | |
1174 | @param EAX Lower 32-bits of MSR value.\r | |
1175 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
1176 | @param EDX Upper 32-bits of MSR value.\r | |
1177 | Described by the type MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER.\r | |
1178 | \r | |
1179 | <b>Example usage</b>\r | |
1180 | @code\r | |
1181 | MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER Msr;\r | |
1182 | \r | |
1183 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_RAPL_POWER_UNIT);\r | |
1184 | @endcode\r | |
ad8a2f5e | 1185 | @note MSR_XEON_PHI_RAPL_POWER_UNIT is defined as MSR_RAPL_POWER_UNIT in SDM.\r |
3adf6316 | 1186 | **/\r |
2f88bd3a | 1187 | #define MSR_XEON_PHI_RAPL_POWER_UNIT 0x00000606\r |
3adf6316 MK |
1188 | \r |
1189 | /**\r | |
1190 | MSR information returned for MSR index #MSR_XEON_PHI_RAPL_POWER_UNIT\r | |
1191 | **/\r | |
1192 | typedef union {\r | |
1193 | ///\r | |
1194 | /// Individual bit fields\r | |
1195 | ///\r | |
1196 | struct {\r | |
1197 | ///\r | |
1198 | /// [Bits 3:0] Package. Power Units See Section 14.9.1, "RAPL Interfaces.".\r | |
1199 | ///\r | |
2f88bd3a MK |
1200 | UINT32 PowerUnits : 4;\r |
1201 | UINT32 Reserved1 : 4;\r | |
3adf6316 MK |
1202 | ///\r |
1203 | /// [Bits 12:8] Package. Energy Status Units Energy related information\r | |
1204 | /// (in Joules) is based on the multiplier, 1/2^ESU; where ESU is an\r | |
1205 | /// unsigned integer represented by bits 12:8. Default value is 0EH (or 61\r | |
1206 | /// micro-joules).\r | |
1207 | ///\r | |
2f88bd3a MK |
1208 | UINT32 EnergyStatusUnits : 5;\r |
1209 | UINT32 Reserved2 : 3;\r | |
3adf6316 MK |
1210 | ///\r |
1211 | /// [Bits 19:16] Package. Time Units See Section 14.9.1, "RAPL\r | |
1212 | /// Interfaces.".\r | |
1213 | ///\r | |
2f88bd3a MK |
1214 | UINT32 TimeUnits : 4;\r |
1215 | UINT32 Reserved3 : 12;\r | |
1216 | UINT32 Reserved4 : 32;\r | |
3adf6316 MK |
1217 | } Bits;\r |
1218 | ///\r | |
1219 | /// All bit fields as a 32-bit value\r | |
1220 | ///\r | |
2f88bd3a | 1221 | UINT32 Uint32;\r |
3adf6316 MK |
1222 | ///\r |
1223 | /// All bit fields as a 64-bit value\r | |
1224 | ///\r | |
2f88bd3a | 1225 | UINT64 Uint64;\r |
3adf6316 MK |
1226 | } MSR_XEON_PHI_RAPL_POWER_UNIT_REGISTER;\r |
1227 | \r | |
3adf6316 MK |
1228 | /**\r |
1229 | Package. Note: C-state values are processor specific C-state code names,\r | |
1230 | unrelated to MWAIT extension C-state parameters or ACPI C-States. Package C2\r | |
1231 | Residency Counter. (R/O).\r | |
1232 | \r | |
1233 | @param ECX MSR_XEON_PHI_PKG_C2_RESIDENCY (0x0000060D)\r | |
1234 | @param EAX Lower 32-bits of MSR value.\r | |
1235 | @param EDX Upper 32-bits of MSR value.\r | |
1236 | \r | |
1237 | <b>Example usage</b>\r | |
1238 | @code\r | |
1239 | UINT64 Msr;\r | |
1240 | \r | |
1241 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY);\r | |
1242 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_C2_RESIDENCY, Msr);\r | |
1243 | @endcode\r | |
ad8a2f5e | 1244 | @note MSR_XEON_PHI_PKG_C2_RESIDENCY is defined as MSR_PKG_C2_RESIDENCY in SDM.\r |
3adf6316 | 1245 | **/\r |
2f88bd3a | 1246 | #define MSR_XEON_PHI_PKG_C2_RESIDENCY 0x0000060D\r |
3adf6316 MK |
1247 | \r |
1248 | /**\r | |
1249 | Package. PKG RAPL Power Limit Control (R/W) See Section 14.9.3, "Package\r | |
1250 | RAPL Domain.".\r | |
1251 | \r | |
1252 | @param ECX MSR_XEON_PHI_PKG_POWER_LIMIT (0x00000610)\r | |
1253 | @param EAX Lower 32-bits of MSR value.\r | |
1254 | @param EDX Upper 32-bits of MSR value.\r | |
1255 | \r | |
1256 | <b>Example usage</b>\r | |
1257 | @code\r | |
1258 | UINT64 Msr;\r | |
1259 | \r | |
1260 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT);\r | |
1261 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_LIMIT, Msr);\r | |
1262 | @endcode\r | |
ad8a2f5e | 1263 | @note MSR_XEON_PHI_PKG_POWER_LIMIT is defined as MSR_PKG_POWER_LIMIT in SDM.\r |
3adf6316 | 1264 | **/\r |
2f88bd3a | 1265 | #define MSR_XEON_PHI_PKG_POWER_LIMIT 0x00000610\r |
3adf6316 MK |
1266 | \r |
1267 | /**\r | |
1268 | Package. PKG Energy Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1269 | \r | |
1270 | @param ECX MSR_XEON_PHI_PKG_ENERGY_STATUS (0x00000611)\r | |
1271 | @param EAX Lower 32-bits of MSR value.\r | |
1272 | @param EDX Upper 32-bits of MSR value.\r | |
1273 | \r | |
1274 | <b>Example usage</b>\r | |
1275 | @code\r | |
1276 | UINT64 Msr;\r | |
1277 | \r | |
1278 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_ENERGY_STATUS);\r | |
1279 | @endcode\r | |
ad8a2f5e | 1280 | @note MSR_XEON_PHI_PKG_ENERGY_STATUS is defined as MSR_PKG_ENERGY_STATUS in SDM.\r |
3adf6316 | 1281 | **/\r |
2f88bd3a | 1282 | #define MSR_XEON_PHI_PKG_ENERGY_STATUS 0x00000611\r |
3adf6316 MK |
1283 | \r |
1284 | /**\r | |
1285 | Package. PKG Perf Status (R/O) See Section 14.9.3, "Package RAPL Domain.".\r | |
1286 | \r | |
1287 | @param ECX MSR_XEON_PHI_PKG_PERF_STATUS (0x00000613)\r | |
1288 | @param EAX Lower 32-bits of MSR value.\r | |
1289 | @param EDX Upper 32-bits of MSR value.\r | |
1290 | \r | |
1291 | <b>Example usage</b>\r | |
1292 | @code\r | |
1293 | UINT64 Msr;\r | |
1294 | \r | |
1295 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_PERF_STATUS);\r | |
1296 | @endcode\r | |
ad8a2f5e | 1297 | @note MSR_XEON_PHI_PKG_PERF_STATUS is defined as MSR_PKG_PERF_STATUS in SDM.\r |
3adf6316 | 1298 | **/\r |
2f88bd3a | 1299 | #define MSR_XEON_PHI_PKG_PERF_STATUS 0x00000613\r |
3adf6316 MK |
1300 | \r |
1301 | /**\r | |
1302 | Package. PKG RAPL Parameters (R/W) See Section 14.9.3, "Package RAPL\r | |
1303 | Domain.".\r | |
1304 | \r | |
1305 | @param ECX MSR_XEON_PHI_PKG_POWER_INFO (0x00000614)\r | |
1306 | @param EAX Lower 32-bits of MSR value.\r | |
1307 | @param EDX Upper 32-bits of MSR value.\r | |
1308 | \r | |
1309 | <b>Example usage</b>\r | |
1310 | @code\r | |
1311 | UINT64 Msr;\r | |
1312 | \r | |
1313 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PKG_POWER_INFO);\r | |
1314 | AsmWriteMsr64 (MSR_XEON_PHI_PKG_POWER_INFO, Msr);\r | |
1315 | @endcode\r | |
ad8a2f5e | 1316 | @note MSR_XEON_PHI_PKG_POWER_INFO is defined as MSR_PKG_POWER_INFO in SDM.\r |
3adf6316 | 1317 | **/\r |
2f88bd3a | 1318 | #define MSR_XEON_PHI_PKG_POWER_INFO 0x00000614\r |
3adf6316 MK |
1319 | \r |
1320 | /**\r | |
1321 | Package. DRAM RAPL Power Limit Control (R/W) See Section 14.9.5, "DRAM RAPL\r | |
1322 | Domain.".\r | |
1323 | \r | |
1324 | @param ECX MSR_XEON_PHI_DRAM_POWER_LIMIT (0x00000618)\r | |
1325 | @param EAX Lower 32-bits of MSR value.\r | |
1326 | @param EDX Upper 32-bits of MSR value.\r | |
1327 | \r | |
1328 | <b>Example usage</b>\r | |
1329 | @code\r | |
1330 | UINT64 Msr;\r | |
1331 | \r | |
1332 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT);\r | |
1333 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_LIMIT, Msr);\r | |
1334 | @endcode\r | |
ad8a2f5e | 1335 | @note MSR_XEON_PHI_DRAM_POWER_LIMIT is defined as MSR_DRAM_POWER_LIMIT in SDM.\r |
3adf6316 | 1336 | **/\r |
2f88bd3a | 1337 | #define MSR_XEON_PHI_DRAM_POWER_LIMIT 0x00000618\r |
3adf6316 MK |
1338 | \r |
1339 | /**\r | |
1340 | Package. DRAM Energy Status (R/O) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1341 | \r | |
1342 | @param ECX MSR_XEON_PHI_DRAM_ENERGY_STATUS (0x00000619)\r | |
1343 | @param EAX Lower 32-bits of MSR value.\r | |
1344 | @param EDX Upper 32-bits of MSR value.\r | |
1345 | \r | |
1346 | <b>Example usage</b>\r | |
1347 | @code\r | |
1348 | UINT64 Msr;\r | |
1349 | \r | |
1350 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_ENERGY_STATUS);\r | |
1351 | @endcode\r | |
ad8a2f5e | 1352 | @note MSR_XEON_PHI_DRAM_ENERGY_STATUS is defined as MSR_DRAM_ENERGY_STATUS in SDM.\r |
3adf6316 | 1353 | **/\r |
2f88bd3a | 1354 | #define MSR_XEON_PHI_DRAM_ENERGY_STATUS 0x00000619\r |
3adf6316 MK |
1355 | \r |
1356 | /**\r | |
1357 | Package. DRAM Performance Throttling Status (R/O) See Section 14.9.5, "DRAM\r | |
1358 | RAPL Domain.".\r | |
1359 | \r | |
1360 | @param ECX MSR_XEON_PHI_DRAM_PERF_STATUS (0x0000061B)\r | |
1361 | @param EAX Lower 32-bits of MSR value.\r | |
1362 | @param EDX Upper 32-bits of MSR value.\r | |
1363 | \r | |
1364 | <b>Example usage</b>\r | |
1365 | @code\r | |
1366 | UINT64 Msr;\r | |
1367 | \r | |
1368 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_PERF_STATUS);\r | |
1369 | @endcode\r | |
ad8a2f5e | 1370 | @note MSR_XEON_PHI_DRAM_PERF_STATUS is defined as MSR_DRAM_PERF_STATUS in SDM.\r |
3adf6316 | 1371 | **/\r |
2f88bd3a | 1372 | #define MSR_XEON_PHI_DRAM_PERF_STATUS 0x0000061B\r |
3adf6316 MK |
1373 | \r |
1374 | /**\r | |
1375 | Package. DRAM RAPL Parameters (R/W) See Section 14.9.5, "DRAM RAPL Domain.".\r | |
1376 | \r | |
1377 | @param ECX MSR_XEON_PHI_DRAM_POWER_INFO (0x0000061C)\r | |
1378 | @param EAX Lower 32-bits of MSR value.\r | |
1379 | @param EDX Upper 32-bits of MSR value.\r | |
1380 | \r | |
1381 | <b>Example usage</b>\r | |
1382 | @code\r | |
1383 | UINT64 Msr;\r | |
1384 | \r | |
1385 | Msr = AsmReadMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO);\r | |
1386 | AsmWriteMsr64 (MSR_XEON_PHI_DRAM_POWER_INFO, Msr);\r | |
1387 | @endcode\r | |
ad8a2f5e | 1388 | @note MSR_XEON_PHI_DRAM_POWER_INFO is defined as MSR_DRAM_POWER_INFO in SDM.\r |
3adf6316 | 1389 | **/\r |
2f88bd3a | 1390 | #define MSR_XEON_PHI_DRAM_POWER_INFO 0x0000061C\r |
3adf6316 MK |
1391 | \r |
1392 | /**\r | |
dfb20851 ED |
1393 | Package. Uncore Ratio Limit (R/W) Out of reset, the min_ratio and max_ratio\r |
1394 | fields represent the widest possible range of uncore frequencies. Writing to\r | |
1395 | these fields allows software to control the minimum and the maximum\r | |
1396 | frequency that hardware will select.\r | |
1397 | \r | |
1398 | @param ECX MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT (0x00000620)\r | |
1399 | @param EAX Lower 32-bits of MSR value.\r | |
1400 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
1401 | @param EDX Upper 32-bits of MSR value.\r | |
1402 | Described by the type MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER.\r | |
1403 | \r | |
1404 | <b>Example usage</b>\r | |
1405 | @code\r | |
1406 | MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER Msr;\r | |
1407 | \r | |
1408 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT);\r | |
1409 | AsmWriteMsr64 (MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT, Msr.Uint64);\r | |
1410 | @endcode\r | |
1411 | **/\r | |
2f88bd3a | 1412 | #define MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT 0x00000620\r |
dfb20851 ED |
1413 | \r |
1414 | /**\r | |
1415 | MSR information returned for MSR index #MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT\r | |
1416 | **/\r | |
1417 | typedef union {\r | |
1418 | ///\r | |
1419 | /// Individual bit fields\r | |
1420 | ///\r | |
1421 | struct {\r | |
1422 | ///\r | |
1423 | /// [Bits 6:0] MAX_RATIO This field is used to limit the max ratio of the\r | |
1424 | /// LLC/Ring.\r | |
1425 | ///\r | |
2f88bd3a MK |
1426 | UINT32 MAX_RATIO : 7;\r |
1427 | UINT32 Reserved1 : 1;\r | |
dfb20851 ED |
1428 | ///\r |
1429 | /// [Bits 14:8] MIN_RATIO Writing to this field controls the minimum\r | |
1430 | /// possible ratio of the LLC/Ring.\r | |
1431 | ///\r | |
2f88bd3a MK |
1432 | UINT32 MIN_RATIO : 7;\r |
1433 | UINT32 Reserved2 : 17;\r | |
1434 | UINT32 Reserved3 : 32;\r | |
dfb20851 ED |
1435 | } Bits;\r |
1436 | ///\r | |
1437 | /// All bit fields as a 32-bit value\r | |
1438 | ///\r | |
2f88bd3a | 1439 | UINT32 Uint32;\r |
dfb20851 ED |
1440 | ///\r |
1441 | /// All bit fields as a 64-bit value\r | |
1442 | ///\r | |
2f88bd3a | 1443 | UINT64 Uint64;\r |
dfb20851 ED |
1444 | } MSR_XEON_PHI_MSRUNCORE_RATIO_LIMIT_REGISTER;\r |
1445 | \r | |
dfb20851 ED |
1446 | /**\r |
1447 | Package. PP0 RAPL Power Limit Control (R/W) See Section 14.9.4, "PP0/PP1\r | |
3adf6316 MK |
1448 | RAPL Domains.".\r |
1449 | \r | |
1450 | @param ECX MSR_XEON_PHI_PP0_POWER_LIMIT (0x00000638)\r | |
1451 | @param EAX Lower 32-bits of MSR value.\r | |
1452 | @param EDX Upper 32-bits of MSR value.\r | |
1453 | \r | |
1454 | <b>Example usage</b>\r | |
1455 | @code\r | |
1456 | UINT64 Msr;\r | |
1457 | \r | |
1458 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT);\r | |
1459 | AsmWriteMsr64 (MSR_XEON_PHI_PP0_POWER_LIMIT, Msr);\r | |
1460 | @endcode\r | |
ad8a2f5e | 1461 | @note MSR_XEON_PHI_PP0_POWER_LIMIT is defined as MSR_PP0_POWER_LIMIT in SDM.\r |
3adf6316 | 1462 | **/\r |
2f88bd3a | 1463 | #define MSR_XEON_PHI_PP0_POWER_LIMIT 0x00000638\r |
3adf6316 MK |
1464 | \r |
1465 | /**\r | |
1466 | Package. PP0 Energy Status (R/O) See Section 14.9.4, "PP0/PP1 RAPL\r | |
1467 | Domains.".\r | |
1468 | \r | |
1469 | @param ECX MSR_XEON_PHI_PP0_ENERGY_STATUS (0x00000639)\r | |
1470 | @param EAX Lower 32-bits of MSR value.\r | |
1471 | @param EDX Upper 32-bits of MSR value.\r | |
1472 | \r | |
1473 | <b>Example usage</b>\r | |
1474 | @code\r | |
1475 | UINT64 Msr;\r | |
1476 | \r | |
1477 | Msr = AsmReadMsr64 (MSR_XEON_PHI_PP0_ENERGY_STATUS);\r | |
1478 | @endcode\r | |
ad8a2f5e | 1479 | @note MSR_XEON_PHI_PP0_ENERGY_STATUS is defined as MSR_PP0_ENERGY_STATUS in SDM.\r |
3adf6316 | 1480 | **/\r |
2f88bd3a | 1481 | #define MSR_XEON_PHI_PP0_ENERGY_STATUS 0x00000639\r |
3adf6316 MK |
1482 | \r |
1483 | /**\r | |
ba1a2d11 | 1484 | Package. Base TDP Ratio (R/O) See Table 2-24.\r |
3adf6316 MK |
1485 | \r |
1486 | @param ECX MSR_XEON_PHI_CONFIG_TDP_NOMINAL (0x00000648)\r | |
1487 | @param EAX Lower 32-bits of MSR value.\r | |
1488 | @param EDX Upper 32-bits of MSR value.\r | |
1489 | \r | |
1490 | <b>Example usage</b>\r | |
1491 | @code\r | |
1492 | UINT64 Msr;\r | |
1493 | \r | |
1494 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_NOMINAL);\r | |
1495 | @endcode\r | |
ad8a2f5e | 1496 | @note MSR_XEON_PHI_CONFIG_TDP_NOMINAL is defined as MSR_CONFIG_TDP_NOMINAL in SDM.\r |
3adf6316 | 1497 | **/\r |
2f88bd3a | 1498 | #define MSR_XEON_PHI_CONFIG_TDP_NOMINAL 0x00000648\r |
3adf6316 MK |
1499 | \r |
1500 | /**\r | |
ba1a2d11 | 1501 | Package. ConfigTDP Level 1 ratio and power level (R/O) See Table 2-24.\r |
3adf6316 MK |
1502 | \r |
1503 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL1 (0x00000649)\r | |
1504 | @param EAX Lower 32-bits of MSR value.\r | |
1505 | @param EDX Upper 32-bits of MSR value.\r | |
1506 | \r | |
1507 | <b>Example usage</b>\r | |
1508 | @code\r | |
1509 | UINT64 Msr;\r | |
1510 | \r | |
1511 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL1);\r | |
1512 | @endcode\r | |
ad8a2f5e | 1513 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL1 is defined as MSR_CONFIG_TDP_LEVEL1 in SDM.\r |
3adf6316 | 1514 | **/\r |
2f88bd3a | 1515 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL1 0x00000649\r |
3adf6316 MK |
1516 | \r |
1517 | /**\r | |
ba1a2d11 | 1518 | Package. ConfigTDP Level 2 ratio and power level (R/O) See Table 2-24.\r |
3adf6316 MK |
1519 | \r |
1520 | @param ECX MSR_XEON_PHI_CONFIG_TDP_LEVEL2 (0x0000064A)\r | |
1521 | @param EAX Lower 32-bits of MSR value.\r | |
1522 | @param EDX Upper 32-bits of MSR value.\r | |
1523 | \r | |
1524 | <b>Example usage</b>\r | |
1525 | @code\r | |
1526 | UINT64 Msr;\r | |
1527 | \r | |
1528 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_LEVEL2);\r | |
1529 | @endcode\r | |
ad8a2f5e | 1530 | @note MSR_XEON_PHI_CONFIG_TDP_LEVEL2 is defined as MSR_CONFIG_TDP_LEVEL2 in SDM.\r |
3adf6316 | 1531 | **/\r |
2f88bd3a | 1532 | #define MSR_XEON_PHI_CONFIG_TDP_LEVEL2 0x0000064A\r |
3adf6316 MK |
1533 | \r |
1534 | /**\r | |
ba1a2d11 | 1535 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
3adf6316 MK |
1536 | \r |
1537 | @param ECX MSR_XEON_PHI_CONFIG_TDP_CONTROL (0x0000064B)\r | |
1538 | @param EAX Lower 32-bits of MSR value.\r | |
1539 | @param EDX Upper 32-bits of MSR value.\r | |
1540 | \r | |
1541 | <b>Example usage</b>\r | |
1542 | @code\r | |
1543 | UINT64 Msr;\r | |
1544 | \r | |
1545 | Msr = AsmReadMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL);\r | |
1546 | AsmWriteMsr64 (MSR_XEON_PHI_CONFIG_TDP_CONTROL, Msr);\r | |
1547 | @endcode\r | |
ad8a2f5e | 1548 | @note MSR_XEON_PHI_CONFIG_TDP_CONTROL is defined as MSR_CONFIG_TDP_CONTROL in SDM.\r |
3adf6316 | 1549 | **/\r |
2f88bd3a | 1550 | #define MSR_XEON_PHI_CONFIG_TDP_CONTROL 0x0000064B\r |
3adf6316 MK |
1551 | \r |
1552 | /**\r | |
ba1a2d11 | 1553 | Package. ConfigTDP Control (R/W) See Table 2-24.\r |
3adf6316 MK |
1554 | \r |
1555 | @param ECX MSR_XEON_PHI_TURBO_ACTIVATION_RATIO (0x0000064C)\r | |
1556 | @param EAX Lower 32-bits of MSR value.\r | |
1557 | @param EDX Upper 32-bits of MSR value.\r | |
1558 | \r | |
1559 | <b>Example usage</b>\r | |
1560 | @code\r | |
1561 | UINT64 Msr;\r | |
1562 | \r | |
1563 | Msr = AsmReadMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO);\r | |
1564 | AsmWriteMsr64 (MSR_XEON_PHI_TURBO_ACTIVATION_RATIO, Msr);\r | |
1565 | @endcode\r | |
ad8a2f5e | 1566 | @note MSR_XEON_PHI_TURBO_ACTIVATION_RATIO is defined as MSR_TURBO_ACTIVATION_RATIO in SDM.\r |
3adf6316 | 1567 | **/\r |
2f88bd3a | 1568 | #define MSR_XEON_PHI_TURBO_ACTIVATION_RATIO 0x0000064C\r |
3adf6316 MK |
1569 | \r |
1570 | /**\r | |
1571 | Package. Indicator of Frequency Clipping in Processor Cores (R/W) (frequency\r | |
1572 | refers to processor core frequency).\r | |
1573 | \r | |
1574 | @param ECX MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS (0x00000690)\r | |
1575 | @param EAX Lower 32-bits of MSR value.\r | |
1576 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1577 | @param EDX Upper 32-bits of MSR value.\r | |
1578 | Described by the type MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER.\r | |
1579 | \r | |
1580 | <b>Example usage</b>\r | |
1581 | @code\r | |
1582 | MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER Msr;\r | |
1583 | \r | |
1584 | Msr.Uint64 = AsmReadMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS);\r | |
1585 | AsmWriteMsr64 (MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS, Msr.Uint64);\r | |
1586 | @endcode\r | |
ad8a2f5e | 1587 | @note MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS is defined as MSR_CORE_PERF_LIMIT_REASONS in SDM.\r |
3adf6316 | 1588 | **/\r |
2f88bd3a | 1589 | #define MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS 0x00000690\r |
3adf6316 MK |
1590 | \r |
1591 | /**\r | |
1592 | MSR information returned for MSR index #MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS\r | |
1593 | **/\r | |
1594 | typedef union {\r | |
1595 | ///\r | |
1596 | /// Individual bit fields\r | |
1597 | ///\r | |
1598 | struct {\r | |
1599 | ///\r | |
1600 | /// [Bit 0] PROCHOT Status (R0).\r | |
1601 | ///\r | |
2f88bd3a | 1602 | UINT32 PROCHOT_Status : 1;\r |
3adf6316 MK |
1603 | ///\r |
1604 | /// [Bit 1] Thermal Status (R0).\r | |
1605 | ///\r | |
2f88bd3a MK |
1606 | UINT32 ThermalStatus : 1;\r |
1607 | UINT32 Reserved1 : 4;\r | |
3adf6316 MK |
1608 | ///\r |
1609 | /// [Bit 6] VR Therm Alert Status (R0).\r | |
1610 | ///\r | |
2f88bd3a MK |
1611 | UINT32 VRThermAlertStatus : 1;\r |
1612 | UINT32 Reserved2 : 1;\r | |
3adf6316 MK |
1613 | ///\r |
1614 | /// [Bit 8] Electrical Design Point Status (R0).\r | |
1615 | ///\r | |
2f88bd3a MK |
1616 | UINT32 ElectricalDesignPointStatus : 1;\r |
1617 | UINT32 Reserved3 : 23;\r | |
1618 | UINT32 Reserved4 : 32;\r | |
3adf6316 MK |
1619 | } Bits;\r |
1620 | ///\r | |
1621 | /// All bit fields as a 32-bit value\r | |
1622 | ///\r | |
2f88bd3a | 1623 | UINT32 Uint32;\r |
3adf6316 MK |
1624 | ///\r |
1625 | /// All bit fields as a 64-bit value\r | |
1626 | ///\r | |
2f88bd3a | 1627 | UINT64 Uint64;\r |
3adf6316 MK |
1628 | } MSR_XEON_PHI_CORE_PERF_LIMIT_REASONS_REGISTER;\r |
1629 | \r | |
1630 | #endif\r |