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32304af2 | 1 | /** @file\r |
9095d37b LG |
2 | Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg\r |
3 | versions are null functions used to make sure things will compile.\r | |
32304af2 | 4 | \r |
9095d37b | 5 | Copyright (c) 2006 - 2018, Intel Corporation. All rights reserved.<BR>\r |
2f7c0ad1 | 6 | Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
9344f092 | 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
32304af2 | 8 | \r |
9 | **/\r | |
10 | \r | |
11 | //\r | |
12 | // Include common header file for this module.\r | |
13 | //\r | |
14 | #include <Base.h>\r | |
15 | #include <Library/DebugLib.h>\r | |
16 | \r | |
17 | /**\r | |
18 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
19 | calling CPU.\r | |
20 | \r | |
21 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
22 | calling CPU.\r | |
23 | \r | |
24 | **/\r | |
25 | VOID\r | |
26 | EFIAPI\r | |
27 | InvalidateInstructionCache (\r | |
28 | VOID\r | |
29 | )\r | |
30 | {\r | |
2f88bd3a | 31 | ASSERT (FALSE);\r |
32304af2 | 32 | }\r |
33 | \r | |
34 | /**\r | |
35 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
36 | of the calling CPU.\r | |
37 | \r | |
38 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
39 | Address is not aligned on a cache line boundary, then entire instruction\r | |
40 | cache line containing Address is invalidated. If Address + Length is not\r | |
41 | aligned on a cache line boundary, then the entire instruction cache line\r | |
42 | containing Address + Length -1 is invalidated. This function may choose to\r | |
43 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 44 | invalidating the specified range. If Length is 0, then no instruction cache\r |
32304af2 | 45 | lines are invalidated. Address is returned.\r |
46 | \r | |
47 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
48 | \r | |
49 | @param Address The base address of the instruction cache lines to\r | |
50 | invalidate. If the CPU is in a physical addressing mode, then\r | |
51 | Address is a physical address. If the CPU is in a virtual\r | |
52 | addressing mode, then Address is a virtual address.\r | |
53 | \r | |
54 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
55 | \r | |
56 | @return Address\r | |
57 | \r | |
58 | **/\r | |
59 | VOID *\r | |
60 | EFIAPI\r | |
61 | InvalidateInstructionCacheRange (\r | |
2f88bd3a MK |
62 | IN VOID *Address,\r |
63 | IN UINTN Length\r | |
32304af2 | 64 | )\r |
65 | {\r | |
229fe3a2 | 66 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
2f88bd3a | 67 | ASSERT (FALSE);\r |
32304af2 | 68 | return Address;\r |
69 | }\r | |
70 | \r | |
71 | /**\r | |
35a17154 | 72 | Writes back and invalidates the entire data cache in cache coherency domain\r |
32304af2 | 73 | of the calling CPU.\r |
74 | \r | |
75 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
76 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
77 | written back to system memory, and also invalidates all the data cache lines\r | |
78 | in the cache coherency domain of the calling CPU.\r | |
79 | \r | |
80 | **/\r | |
81 | VOID\r | |
82 | EFIAPI\r | |
83 | WriteBackInvalidateDataCache (\r | |
84 | VOID\r | |
85 | )\r | |
86 | {\r | |
2f88bd3a | 87 | ASSERT (FALSE);\r |
32304af2 | 88 | }\r |
89 | \r | |
90 | /**\r | |
35a17154 | 91 | Writes back and invalidates a range of data cache lines in the cache\r |
32304af2 | 92 | coherency domain of the calling CPU.\r |
93 | \r | |
35a17154 | 94 | Writes back and invalidates the data cache lines specified by Address and\r |
32304af2 | 95 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
96 | cache line containing Address is written back and invalidated. If Address +\r | |
97 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
98 | line containing Address + Length -1 is written back and invalidated. This\r | |
99 | function may choose to write back and invalidate the entire data cache if\r | |
100 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 101 | range. If Length is 0, then no data cache lines are written back and\r |
32304af2 | 102 | invalidated. Address is returned.\r |
103 | \r | |
104 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
105 | \r | |
106 | @param Address The base address of the data cache lines to write back and\r | |
107 | invalidate. If the CPU is in a physical addressing mode, then\r | |
108 | Address is a physical address. If the CPU is in a virtual\r | |
109 | addressing mode, then Address is a virtual address.\r | |
110 | @param Length The number of bytes to write back and invalidate from the\r | |
111 | data cache.\r | |
112 | \r | |
113 | @return Address\r | |
114 | \r | |
115 | **/\r | |
116 | VOID *\r | |
117 | EFIAPI\r | |
118 | WriteBackInvalidateDataCacheRange (\r | |
2f88bd3a MK |
119 | IN VOID *Address,\r |
120 | IN UINTN Length\r | |
32304af2 | 121 | )\r |
122 | {\r | |
229fe3a2 | 123 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
2f88bd3a | 124 | ASSERT (FALSE);\r |
32304af2 | 125 | return Address;\r |
126 | }\r | |
127 | \r | |
128 | /**\r | |
35a17154 | 129 | Writes back the entire data cache in cache coherency domain of the calling\r |
32304af2 | 130 | CPU.\r |
131 | \r | |
35a17154 | 132 | Writes back the entire data cache in cache coherency domain of the calling\r |
32304af2 | 133 | CPU. This function guarantees that all dirty cache lines are written back to\r |
134 | system memory. This function may also invalidate all the data cache lines in\r | |
135 | the cache coherency domain of the calling CPU.\r | |
136 | \r | |
137 | **/\r | |
138 | VOID\r | |
139 | EFIAPI\r | |
140 | WriteBackDataCache (\r | |
141 | VOID\r | |
142 | )\r | |
143 | {\r | |
2f88bd3a | 144 | ASSERT (FALSE);\r |
32304af2 | 145 | }\r |
146 | \r | |
147 | /**\r | |
35a17154 | 148 | Writes back a range of data cache lines in the cache coherency domain of the\r |
32304af2 | 149 | calling CPU.\r |
150 | \r | |
35a17154 | 151 | Writes back the data cache lines specified by Address and Length. If Address\r |
32304af2 | 152 | is not aligned on a cache line boundary, then entire data cache line\r |
153 | containing Address is written back. If Address + Length is not aligned on a\r | |
154 | cache line boundary, then the entire data cache line containing Address +\r | |
155 | Length -1 is written back. This function may choose to write back the entire\r | |
156 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 157 | If Length is 0, then no data cache lines are written back. This function may\r |
32304af2 | 158 | also invalidate all the data cache lines in the specified range of the cache\r |
159 | coherency domain of the calling CPU. Address is returned.\r | |
160 | \r | |
161 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
162 | \r | |
163 | @param Address The base address of the data cache lines to write back. If\r | |
164 | the CPU is in a physical addressing mode, then Address is a\r | |
165 | physical address. If the CPU is in a virtual addressing\r | |
166 | mode, then Address is a virtual address.\r | |
167 | @param Length The number of bytes to write back from the data cache.\r | |
168 | \r | |
169 | @return Address\r | |
170 | \r | |
171 | **/\r | |
172 | VOID *\r | |
173 | EFIAPI\r | |
174 | WriteBackDataCacheRange (\r | |
2f88bd3a MK |
175 | IN VOID *Address,\r |
176 | IN UINTN Length\r | |
32304af2 | 177 | )\r |
178 | {\r | |
229fe3a2 | 179 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
2f88bd3a | 180 | ASSERT (FALSE);\r |
32304af2 | 181 | return Address;\r |
182 | }\r | |
183 | \r | |
184 | /**\r | |
185 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
186 | CPU.\r | |
187 | \r | |
188 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
189 | CPU. This function must be used with care because dirty cache lines are not\r | |
190 | written back to system memory. It is typically used for cache diagnostics. If\r | |
191 | the CPU does not support invalidation of the entire data cache, then a write\r | |
192 | back and invalidate operation should be performed on the entire data cache.\r | |
193 | \r | |
194 | **/\r | |
195 | VOID\r | |
196 | EFIAPI\r | |
197 | InvalidateDataCache (\r | |
198 | VOID\r | |
199 | )\r | |
200 | {\r | |
2f88bd3a | 201 | ASSERT (FALSE);\r |
32304af2 | 202 | }\r |
203 | \r | |
204 | /**\r | |
205 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
206 | calling CPU.\r | |
207 | \r | |
208 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
209 | is not aligned on a cache line boundary, then entire data cache line\r | |
210 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
211 | cache line boundary, then the entire data cache line containing Address +\r | |
212 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 213 | outside the specified range. If Length is 0, then no data cache lines are\r |
32304af2 | 214 | invalidated. Address is returned. This function must be used with care\r |
215 | because dirty cache lines are not written back to system memory. It is\r | |
216 | typically used for cache diagnostics. If the CPU does not support\r | |
217 | invalidation of a data cache range, then a write back and invalidate\r | |
218 | operation should be performed on the data cache range.\r | |
219 | \r | |
220 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
221 | \r | |
222 | @param Address The base address of the data cache lines to invalidate. If\r | |
223 | the CPU is in a physical addressing mode, then Address is a\r | |
224 | physical address. If the CPU is in a virtual addressing mode,\r | |
225 | then Address is a virtual address.\r | |
226 | @param Length The number of bytes to invalidate from the data cache.\r | |
227 | \r | |
228 | @return Address\r | |
229 | \r | |
230 | **/\r | |
231 | VOID *\r | |
232 | EFIAPI\r | |
233 | InvalidateDataCacheRange (\r | |
2f88bd3a MK |
234 | IN VOID *Address,\r |
235 | IN UINTN Length\r | |
32304af2 | 236 | )\r |
237 | {\r | |
229fe3a2 | 238 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
2f88bd3a | 239 | ASSERT (FALSE);\r |
32304af2 | 240 | return Address;\r |
241 | }\r |