]>
Commit | Line | Data |
---|---|---|
32304af2 | 1 | /** @file\r |
2 | Cache Maintenance Functions. These functions vary by ARM architecture so the MdePkg \r | |
3 | versions are null functions used to make sure things will compile. \r | |
4 | \r | |
2f7c0ad1 HT |
5 | Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r |
6 | Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r | |
7 | This program and the accompanying materials\r | |
32304af2 | 8 | are licensed and made available under the terms and conditions of the BSD License\r |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
35a17154 | 10 | http://opensource.org/licenses/bsd-license.php.\r |
32304af2 | 11 | \r |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | //\r | |
18 | // Include common header file for this module.\r | |
19 | //\r | |
20 | #include <Base.h>\r | |
21 | #include <Library/DebugLib.h>\r | |
22 | \r | |
23 | /**\r | |
24 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
25 | calling CPU.\r | |
26 | \r | |
27 | Invalidates the entire instruction cache in cache coherency domain of the\r | |
28 | calling CPU.\r | |
29 | \r | |
30 | **/\r | |
31 | VOID\r | |
32 | EFIAPI\r | |
33 | InvalidateInstructionCache (\r | |
34 | VOID\r | |
35 | )\r | |
36 | {\r | |
37 | ASSERT(FALSE);\r | |
38 | }\r | |
39 | \r | |
40 | /**\r | |
41 | Invalidates a range of instruction cache lines in the cache coherency domain\r | |
42 | of the calling CPU.\r | |
43 | \r | |
44 | Invalidates the instruction cache lines specified by Address and Length. If\r | |
45 | Address is not aligned on a cache line boundary, then entire instruction\r | |
46 | cache line containing Address is invalidated. If Address + Length is not\r | |
47 | aligned on a cache line boundary, then the entire instruction cache line\r | |
48 | containing Address + Length -1 is invalidated. This function may choose to\r | |
49 | invalidate the entire instruction cache if that is more efficient than\r | |
35a17154 | 50 | invalidating the specified range. If Length is 0, then no instruction cache\r |
32304af2 | 51 | lines are invalidated. Address is returned.\r |
52 | \r | |
53 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
54 | \r | |
55 | @param Address The base address of the instruction cache lines to\r | |
56 | invalidate. If the CPU is in a physical addressing mode, then\r | |
57 | Address is a physical address. If the CPU is in a virtual\r | |
58 | addressing mode, then Address is a virtual address.\r | |
59 | \r | |
60 | @param Length The number of bytes to invalidate from the instruction cache.\r | |
61 | \r | |
62 | @return Address\r | |
63 | \r | |
64 | **/\r | |
65 | VOID *\r | |
66 | EFIAPI\r | |
67 | InvalidateInstructionCacheRange (\r | |
68 | IN VOID *Address,\r | |
69 | IN UINTN Length\r | |
70 | )\r | |
71 | {\r | |
229fe3a2 | 72 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
32304af2 | 73 | ASSERT(FALSE);\r |
74 | return Address;\r | |
75 | }\r | |
76 | \r | |
77 | /**\r | |
35a17154 | 78 | Writes back and invalidates the entire data cache in cache coherency domain\r |
32304af2 | 79 | of the calling CPU.\r |
80 | \r | |
81 | Writes Back and Invalidates the entire data cache in cache coherency domain\r | |
82 | of the calling CPU. This function guarantees that all dirty cache lines are\r | |
83 | written back to system memory, and also invalidates all the data cache lines\r | |
84 | in the cache coherency domain of the calling CPU.\r | |
85 | \r | |
86 | **/\r | |
87 | VOID\r | |
88 | EFIAPI\r | |
89 | WriteBackInvalidateDataCache (\r | |
90 | VOID\r | |
91 | )\r | |
92 | {\r | |
93 | ASSERT(FALSE);\r | |
94 | }\r | |
95 | \r | |
96 | /**\r | |
35a17154 | 97 | Writes back and invalidates a range of data cache lines in the cache\r |
32304af2 | 98 | coherency domain of the calling CPU.\r |
99 | \r | |
35a17154 | 100 | Writes back and invalidates the data cache lines specified by Address and\r |
32304af2 | 101 | Length. If Address is not aligned on a cache line boundary, then entire data\r |
102 | cache line containing Address is written back and invalidated. If Address +\r | |
103 | Length is not aligned on a cache line boundary, then the entire data cache\r | |
104 | line containing Address + Length -1 is written back and invalidated. This\r | |
105 | function may choose to write back and invalidate the entire data cache if\r | |
106 | that is more efficient than writing back and invalidating the specified\r | |
35a17154 | 107 | range. If Length is 0, then no data cache lines are written back and\r |
32304af2 | 108 | invalidated. Address is returned.\r |
109 | \r | |
110 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
111 | \r | |
112 | @param Address The base address of the data cache lines to write back and\r | |
113 | invalidate. If the CPU is in a physical addressing mode, then\r | |
114 | Address is a physical address. If the CPU is in a virtual\r | |
115 | addressing mode, then Address is a virtual address.\r | |
116 | @param Length The number of bytes to write back and invalidate from the\r | |
117 | data cache.\r | |
118 | \r | |
119 | @return Address\r | |
120 | \r | |
121 | **/\r | |
122 | VOID *\r | |
123 | EFIAPI\r | |
124 | WriteBackInvalidateDataCacheRange (\r | |
125 | IN VOID *Address,\r | |
126 | IN UINTN Length\r | |
127 | )\r | |
128 | {\r | |
229fe3a2 | 129 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
32304af2 | 130 | ASSERT(FALSE);\r |
131 | return Address;\r | |
132 | }\r | |
133 | \r | |
134 | /**\r | |
35a17154 | 135 | Writes back the entire data cache in cache coherency domain of the calling\r |
32304af2 | 136 | CPU.\r |
137 | \r | |
35a17154 | 138 | Writes back the entire data cache in cache coherency domain of the calling\r |
32304af2 | 139 | CPU. This function guarantees that all dirty cache lines are written back to\r |
140 | system memory. This function may also invalidate all the data cache lines in\r | |
141 | the cache coherency domain of the calling CPU.\r | |
142 | \r | |
143 | **/\r | |
144 | VOID\r | |
145 | EFIAPI\r | |
146 | WriteBackDataCache (\r | |
147 | VOID\r | |
148 | )\r | |
149 | {\r | |
150 | ASSERT(FALSE);\r | |
151 | }\r | |
152 | \r | |
153 | /**\r | |
35a17154 | 154 | Writes back a range of data cache lines in the cache coherency domain of the\r |
32304af2 | 155 | calling CPU.\r |
156 | \r | |
35a17154 | 157 | Writes back the data cache lines specified by Address and Length. If Address\r |
32304af2 | 158 | is not aligned on a cache line boundary, then entire data cache line\r |
159 | containing Address is written back. If Address + Length is not aligned on a\r | |
160 | cache line boundary, then the entire data cache line containing Address +\r | |
161 | Length -1 is written back. This function may choose to write back the entire\r | |
162 | data cache if that is more efficient than writing back the specified range.\r | |
35a17154 | 163 | If Length is 0, then no data cache lines are written back. This function may\r |
32304af2 | 164 | also invalidate all the data cache lines in the specified range of the cache\r |
165 | coherency domain of the calling CPU. Address is returned.\r | |
166 | \r | |
167 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
168 | \r | |
169 | @param Address The base address of the data cache lines to write back. If\r | |
170 | the CPU is in a physical addressing mode, then Address is a\r | |
171 | physical address. If the CPU is in a virtual addressing\r | |
172 | mode, then Address is a virtual address.\r | |
173 | @param Length The number of bytes to write back from the data cache.\r | |
174 | \r | |
175 | @return Address\r | |
176 | \r | |
177 | **/\r | |
178 | VOID *\r | |
179 | EFIAPI\r | |
180 | WriteBackDataCacheRange (\r | |
181 | IN VOID *Address,\r | |
182 | IN UINTN Length\r | |
183 | )\r | |
184 | {\r | |
229fe3a2 | 185 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
32304af2 | 186 | ASSERT(FALSE);\r |
187 | return Address;\r | |
188 | }\r | |
189 | \r | |
190 | /**\r | |
191 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
192 | CPU.\r | |
193 | \r | |
194 | Invalidates the entire data cache in cache coherency domain of the calling\r | |
195 | CPU. This function must be used with care because dirty cache lines are not\r | |
196 | written back to system memory. It is typically used for cache diagnostics. If\r | |
197 | the CPU does not support invalidation of the entire data cache, then a write\r | |
198 | back and invalidate operation should be performed on the entire data cache.\r | |
199 | \r | |
200 | **/\r | |
201 | VOID\r | |
202 | EFIAPI\r | |
203 | InvalidateDataCache (\r | |
204 | VOID\r | |
205 | )\r | |
206 | {\r | |
207 | ASSERT(FALSE);\r | |
208 | }\r | |
209 | \r | |
210 | /**\r | |
211 | Invalidates a range of data cache lines in the cache coherency domain of the\r | |
212 | calling CPU.\r | |
213 | \r | |
214 | Invalidates the data cache lines specified by Address and Length. If Address\r | |
215 | is not aligned on a cache line boundary, then entire data cache line\r | |
216 | containing Address is invalidated. If Address + Length is not aligned on a\r | |
217 | cache line boundary, then the entire data cache line containing Address +\r | |
218 | Length -1 is invalidated. This function must never invalidate any cache lines\r | |
35a17154 | 219 | outside the specified range. If Length is 0, then no data cache lines are\r |
32304af2 | 220 | invalidated. Address is returned. This function must be used with care\r |
221 | because dirty cache lines are not written back to system memory. It is\r | |
222 | typically used for cache diagnostics. If the CPU does not support\r | |
223 | invalidation of a data cache range, then a write back and invalidate\r | |
224 | operation should be performed on the data cache range.\r | |
225 | \r | |
226 | If Length is greater than (MAX_ADDRESS - Address + 1), then ASSERT().\r | |
227 | \r | |
228 | @param Address The base address of the data cache lines to invalidate. If\r | |
229 | the CPU is in a physical addressing mode, then Address is a\r | |
230 | physical address. If the CPU is in a virtual addressing mode,\r | |
231 | then Address is a virtual address.\r | |
232 | @param Length The number of bytes to invalidate from the data cache.\r | |
233 | \r | |
234 | @return Address\r | |
235 | \r | |
236 | **/\r | |
237 | VOID *\r | |
238 | EFIAPI\r | |
239 | InvalidateDataCacheRange (\r | |
240 | IN VOID *Address,\r | |
241 | IN UINTN Length\r | |
242 | )\r | |
243 | {\r | |
229fe3a2 | 244 | ASSERT (Length <= MAX_ADDRESS - (UINTN)Address + 1);\r |
32304af2 | 245 | ASSERT(FALSE);\r |
246 | return Address;\r | |
247 | }\r |