projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 2aefd3c3 JJ |
1 | ;------------------------------------------------------------------------------\r |
| 2 | ;\r | |
| 3 | ; Copyright (c) 2006 - 2015, Intel Corporation. All rights reserved.<BR>\r | |
| 9344f092 | 4 | ; SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 2aefd3c3 JJ |
5 | ;\r |
| 6 | ; Module Name:\r | |
| 7 | ;\r | |
| 8 | ; FlushCacheLine.Asm\r | |
| 9 | ;\r | |
| 10 | ; Abstract:\r | |
| 11 | ;\r | |
| 12 | ; AsmFlushCacheLine function\r | |
| 13 | ;\r | |
| 14 | ; Notes:\r | |
| 15 | ;\r | |
| 16 | ;------------------------------------------------------------------------------\r | |
| 17 | \r | |
| 18 | SECTION .text\r | |
| 19 | \r | |
| 20 | ;------------------------------------------------------------------------------\r | |
| 21 | ; VOID *\r | |
| 22 | ; EFIAPI\r | |
| 23 | ; AsmFlushCacheLine (\r | |
| 24 | ; IN VOID *LinearAddress\r | |
| 25 | ; );\r | |
| 26 | ;------------------------------------------------------------------------------\r | |
| 27 | global ASM_PFX(AsmFlushCacheLine)\r | |
| 28 | ASM_PFX(AsmFlushCacheLine):\r | |
| 29 | ;\r | |
| 30 | ; If the CPU does not support CLFLUSH instruction,\r | |
| 31 | ; then promote flush range to flush entire cache.\r | |
| 32 | ;\r | |
| 33 | mov eax, 1\r | |
| 34 | push ebx\r | |
| 35 | cpuid\r | |
| 36 | pop ebx\r | |
| 37 | mov eax, [esp + 4]\r | |
| 38 | test edx, BIT19\r | |
| 39 | jz .0\r | |
| 40 | clflush [eax]\r | |
| 41 | ret\r | |
| 42 | .0:\r | |
| 43 | wbinvd\r | |
| 44 | ret\r | |
| 45 | \r |