Added AsmSwitchStackAndBackingStore() to BaseLib.h for stack switching on IPF.

[mirror_edk2.git] / MdePkg / Library / BaseLib / Ipf / CpuBreakpoint.c

/** @file\r
  Base Library CPU functions for Itanium\r
\r
  Copyright (c) 2006, Intel Corporation<BR>\r
  All rights reserved. This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
//void __mfa (void);\r
\r
#pragma intrinsic (_enable)\r
#pragma intrinsic (_disable)\r
#pragma intrinsic (__break)\r
#pragma intrinsic (__mfa)\r
\r
typedef struct {\r
  UINT64                            Status;\r
  UINT64                            r9;\r
  UINT64                            r10;\r
  UINT64                            r11;\r
} PAL_PROC_RETURN;\r
\r
PAL_PROC_RETURN\r
PalCallStatic (\r
  IN      CONST VOID                *PalEntryPoint,\r
  IN      UINT64                    Arg1,\r
  IN      UINT64                    Arg2,\r
  IN      UINT64                    Arg3,\r
  IN      UINT64                    Arg4\r
  );\r
\r
/**\r
  Generates a breakpoint on the CPU.\r
\r
  Generates a breakpoint on the CPU. The breakpoint must be implemented such\r
  that code can resume normal execution after the breakpoint.\r
\r
**/\r
VOID\r
EFIAPI\r
CpuBreakpoint (\r
  VOID\r
  )\r
{\r
  __break (0);\r
}\r
\r
/**\r
  Used to serialize load and store operations.\r
\r
  All loads and stores that proceed calls to this function are guaranteed to be\r
  globally visible when this function returns.\r
\r
**/\r
VOID\r
EFIAPI\r
MemoryFence (\r
  VOID\r
  )\r
{\r
  __mfa ();\r
}\r
\r
/**\r
  Disables CPU interrupts.\r
\r
  Disables CPU interrupts.\r
\r
**/\r
VOID\r
EFIAPI\r
DisableInterrupts (\r
  VOID\r
  )\r
{\r
  _disable ();\r
}\r
\r
/**\r
  Enables CPU interrupts.\r
\r
  Enables CPU interrupts.\r
\r
**/\r
VOID\r
EFIAPI\r
EnableInterrupts (\r
  VOID\r
  )\r
{\r
  _enable ();\r
}\r
\r
/**\r
  Enables CPU interrupts for the smallest window required to capture any\r
  pending interrupts.\r
\r
  Enables CPU interrupts for the smallest window required to capture any\r
  pending interrupts.\r
\r
**/\r
VOID\r
EFIAPI\r
EnableDisableInterrupts (\r
  VOID\r
  )\r
{\r
  EnableInterrupts ();\r
  DisableInterrupts ();\r
}\r
\r
/**\r
  Places the CPU in a sleep state until an interrupt is received.\r
\r
  Places the CPU in a sleep state until an interrupt is received. If interrupts\r
  are disabled prior to calling this function, then the CPU will be placed in a\r
  sleep state indefinitely.\r
\r
**/\r
VOID\r
EFIAPI\r
CpuSleep (\r
  VOID\r
  )\r
{\r
  PalCallStatic (NULL, 29, 0, 0, 0);\r
}\r