[mirror_edk2.git] / MdePkg / Library / BaseLib / UnitTestHostBaseLib.inf

## @file\r
#  Base Library implementation for use with host based unit tests, and\r
#  can also be used by emulation platforms such as EmulatorPkg.\r
#\r
#  Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
#  Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
#  Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
#  Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
#\r
#  SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
#\r
##\r
\r
[Defines]\r
  INF_VERSION                    = 0x00010005\r
  BASE_NAME                      = UnitTestHostBaseLib\r
  MODULE_UNI_FILE                = UnitTestHostBaseLib.uni\r
  FILE_GUID                      = 9555A0D3-09BA-46C4-A51A-45198E3C765E\r
  MODULE_TYPE                    = BASE\r
  VERSION_STRING                 = 1.1\r
  LIBRARY_CLASS                  = BaseLib\r
  LIBRARY_CLASS                  = UnitTestHostBaseLib|HOST_APPLICATION\r
\r
#\r
#  VALID_ARCHITECTURES           = IA32 X64 EBC ARM AARCH64 RISCV64\r
#\r
\r
[Sources]\r
  CheckSum.c\r
  SwitchStack.c\r
  SwapBytes64.c\r
  SwapBytes32.c\r
  SwapBytes16.c\r
  LongJump.c\r
  SetJump.c\r
  QuickSort.c\r
  RShiftU64.c\r
  RRotU64.c\r
  RRotU32.c\r
  MultU64x64.c\r
  MultU64x32.c\r
  MultS64x64.c\r
  ModU64x32.c\r
  LShiftU64.c\r
  LRotU64.c\r
  LRotU32.c\r
  LowBitSet64.c\r
  LowBitSet32.c\r
  HighBitSet64.c\r
  HighBitSet32.c\r
  GetPowerOfTwo64.c\r
  GetPowerOfTwo32.c\r
  DivU64x64Remainder.c\r
  DivU64x32Remainder.c\r
  DivU64x32.c\r
  DivS64x64Remainder.c\r
  ARShiftU64.c\r
  BitField.c\r
  CpuDeadLoop.c\r
  Cpu.c\r
  LinkedList.c\r
  SafeString.c\r
  String.c\r
  FilePaths.c\r
  BaseLibInternals.h\r
  UnitTestHost.c\r
  UnitTestHost.h\r
\r
[Sources.Ia32]\r
  Ia32/WriteMm7.c | MSFT\r
  Ia32/WriteMm6.c | MSFT\r
  Ia32/WriteMm5.c | MSFT\r
  Ia32/WriteMm4.c | MSFT\r
  Ia32/WriteMm3.c | MSFT\r
  Ia32/WriteMm2.c | MSFT\r
  Ia32/WriteMm1.c | MSFT\r
  Ia32/WriteMm0.c | MSFT\r
  Ia32/ReadMm7.c | MSFT\r
  Ia32/ReadMm6.c | MSFT\r
  Ia32/ReadMm5.c | MSFT\r
  Ia32/ReadMm4.c | MSFT\r
  Ia32/ReadMm3.c | MSFT\r
  Ia32/ReadMm2.c | MSFT\r
  Ia32/ReadMm1.c | MSFT\r
  Ia32/ReadMm0.c | MSFT\r
  Ia32/SwapBytes64.c | MSFT\r
  Ia32/RRotU64.c | MSFT\r
  Ia32/RShiftU64.c | MSFT\r
  Ia32/ReadTsc.c | MSFT\r
  Ia32/ReadEflags.c | MSFT\r
  Ia32/ModU64x32.c | MSFT\r
  Ia32/MultU64x64.c | MSFT\r
  Ia32/MultU64x32.c | MSFT\r
  Ia32/LShiftU64.c | MSFT\r
  Ia32/LRotU64.c | MSFT\r
  Ia32/FxRestore.c | MSFT\r
  Ia32/FxSave.c | MSFT\r
  Ia32/DivU64x32Remainder.c | MSFT\r
  Ia32/DivU64x32.c | MSFT\r
  Ia32/CpuPause.c | MSFT\r
  Ia32/CpuBreakpoint.c | MSFT\r
  Ia32/ARShiftU64.c | MSFT\r
  Ia32/GccInline.c | GCC\r
  Ia32/LongJump.nasm\r
  Ia32/SetJump.nasm\r
  Ia32/SwapBytes64.nasm| GCC\r
  Ia32/DivU64x64Remainder.nasm\r
  Ia32/DivU64x32Remainder.nasm| GCC\r
  Ia32/ModU64x32.nasm| GCC\r
  Ia32/DivU64x32.nasm| GCC\r
  Ia32/MultU64x64.nasm| GCC\r
  Ia32/MultU64x32.nasm| GCC\r
  Ia32/RRotU64.nasm| GCC\r
  Ia32/LRotU64.nasm| GCC\r
  Ia32/ARShiftU64.nasm| GCC\r
  Ia32/RShiftU64.nasm| GCC\r
  Ia32/LShiftU64.nasm| GCC\r
  Ia32/RdRand.nasm\r
  Ia32/DivS64x64Remainder.c\r
  Ia32/InternalSwitchStack.c | MSFT\r
  Ia32/InternalSwitchStack.nasm | GCC\r
  Ia32/Non-existing.c\r
  Unaligned.c\r
  X86MemoryFence.c | MSFT\r
  X86FxSave.c\r
  X86FxRestore.c\r
  X86Msr.c\r
  X86RdRand.c\r
  X86SpeculationBarrier.c\r
  X86UnitTestHost.c\r
  IntelTdxNull.c\r
\r
[Sources.X64]\r
  X64/LongJump.nasm\r
  X64/SetJump.nasm\r
  X64/SwitchStack.nasm\r
  X64/CpuBreakpoint.c | MSFT\r
  X64/CpuPause.nasm| MSFT\r
  X64/ReadTsc.nasm| MSFT\r
  X64/WriteMm7.nasm| MSFT\r
  X64/WriteMm6.nasm| MSFT\r
  X64/WriteMm5.nasm| MSFT\r
  X64/WriteMm4.nasm| MSFT\r
  X64/WriteMm3.nasm| MSFT\r
  X64/WriteMm2.nasm| MSFT\r
  X64/WriteMm1.nasm| MSFT\r
  X64/WriteMm0.nasm| MSFT\r
  X64/ReadMm7.nasm| MSFT\r
  X64/ReadMm6.nasm| MSFT\r
  X64/ReadMm5.nasm| MSFT\r
  X64/ReadMm4.nasm| MSFT\r
  X64/ReadMm3.nasm| MSFT\r
  X64/ReadMm2.nasm| MSFT\r
  X64/ReadMm1.nasm| MSFT\r
  X64/ReadMm0.nasm| MSFT\r
  X64/FxRestore.nasm| MSFT\r
  X64/FxSave.nasm| MSFT\r
  X64/ReadEflags.nasm| MSFT\r
  X64/Non-existing.c\r
  Math64.c\r
  Unaligned.c\r
  X86MemoryFence.c | MSFT\r
  X86FxSave.c\r
  X86FxRestore.c\r
  X86Msr.c\r
  X86RdRand.c\r
  X86SpeculationBarrier.c\r
  X64/GccInline.c | GCC\r
  X64/RdRand.nasm\r
  ChkStkGcc.c  | GCC\r
  X86UnitTestHost.c\r
  IntelTdxNull.c\r
\r
[Sources.EBC]\r
  Ebc/CpuBreakpoint.c\r
  Ebc/SetJumpLongJump.c\r
  Ebc/SwitchStack.c\r
  Ebc/SpeculationBarrier.c\r
  Unaligned.c\r
  Math64.c\r
\r
[Sources.ARM]\r
  Arm/InternalSwitchStack.c\r
  Arm/Unaligned.c\r
  Math64.c                   | MSFT\r
\r
  Arm/SwitchStack.asm        | MSFT\r
  Arm/SetJumpLongJump.asm    | MSFT\r
  Arm/CpuPause.asm           | MSFT\r
  Arm/CpuBreakpoint.asm      | MSFT\r
  Arm/MemoryFence.asm        | MSFT\r
  Arm/SpeculationBarrier.asm | MSFT\r
\r
  Arm/Math64.S                  | GCC\r
  Arm/SwitchStack.S             | GCC\r
  Arm/SetJumpLongJump.S         | GCC\r
  Arm/CpuBreakpoint.S           | GCC\r
  Arm/MemoryFence.S             | GCC\r
  Arm/SpeculationBarrier.S      | GCC\r
\r
[Sources.AARCH64]\r
  Arm/InternalSwitchStack.c\r
  Arm/Unaligned.c\r
  Math64.c\r
\r
  AArch64/MemoryFence.S             | GCC\r
  AArch64/SwitchStack.S             | GCC\r
  AArch64/SetJumpLongJump.S         | GCC\r
  AArch64/CpuBreakpoint.S           | GCC\r
  AArch64/SpeculationBarrier.S      | GCC\r
\r
  AArch64/MemoryFence.asm           | MSFT\r
  AArch64/SwitchStack.asm           | MSFT\r
  AArch64/SetJumpLongJump.asm       | MSFT\r
  AArch64/CpuBreakpoint.asm         | MSFT\r
  AArch64/SpeculationBarrier.asm    | MSFT\r
\r
[Sources.RISCV64]\r
  Math64.c\r
  Unaligned.c\r
  RiscV64/InternalSwitchStack.c\r
  RiscV64/CpuBreakpoint.c\r
  RiscV64/CpuPause.c\r
  RiscV64/RiscVSetJumpLongJump.S    | GCC\r
  RiscV64/RiscVCpuBreakpoint.S      | GCC\r
  RiscV64/RiscVCpuPause.S           | GCC\r
  RiscV64/RiscVInterrupt.S          | GCC\r
  RiscV64/FlushCache.S              | GCC\r
\r
[Packages]\r
  MdePkg/MdePkg.dec\r
\r
[LibraryClasses]\r
  PcdLib\r
  DebugLib\r
  BaseMemoryLib\r
\r
[Pcd]\r
  gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength      ## SOMETIMES_CONSUMES\r
  gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength     ## SOMETIMES_CONSUMES\r
  gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength   ## SOMETIMES_CONSUMES\r
  gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask   ## SOMETIMES_CONSUMES\r
  gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType       ## SOMETIMES_CONSUMES\r
\r
[FeaturePcd]\r
  gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList  ## CONSUMES\r
Commit	Line	Data
540fd45f	1	## @file\r
d103840c ZL	2	# Base Library implementation for use with host based unit tests, and\r
d103840c ZL	3	# can also be used by emulation platforms such as EmulatorPkg.\r
540fd45f	4	#\r
d103840c	5	# Copyright (c) 2007 - 2022, Intel Corporation. All rights reserved.<BR>\r
540fd45f MK	6	# Portions copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
	7	# Portions copyright (c) 2011 - 2013, ARM Ltd. All rights reserved.<BR>\r
	8	# Copyright (c) 2020, Hewlett Packard Enterprise Development LP. All rights reserved.<BR>\r
	9	#\r
	10	# SPDX-License-Identifier: BSD-2-Clause-Patent\r
	11	#\r
	12	#\r
	13	##\r
	14	\r
	15	[Defines]\r
	16	INF_VERSION = 0x00010005\r
	17	BASE_NAME = UnitTestHostBaseLib\r
	18	MODULE_UNI_FILE = UnitTestHostBaseLib.uni\r
	19	FILE_GUID = 9555A0D3-09BA-46C4-A51A-45198E3C765E\r
	20	MODULE_TYPE = BASE\r
	21	VERSION_STRING = 1.1\r
d103840c	22	LIBRARY_CLASS = BaseLib\r
540fd45f MK	23	LIBRARY_CLASS = UnitTestHostBaseLib\|HOST_APPLICATION\r
	24	\r
	25	#\r
	26	# VALID_ARCHITECTURES = IA32 X64 EBC ARM AARCH64 RISCV64\r
	27	#\r
	28	\r
	29	[Sources]\r
	30	CheckSum.c\r
	31	SwitchStack.c\r
	32	SwapBytes64.c\r
	33	SwapBytes32.c\r
	34	SwapBytes16.c\r
	35	LongJump.c\r
	36	SetJump.c\r
4225a464	37	QuickSort.c\r
540fd45f MK	38	RShiftU64.c\r
	39	RRotU64.c\r
	40	RRotU32.c\r
	41	MultU64x64.c\r
	42	MultU64x32.c\r
	43	MultS64x64.c\r
	44	ModU64x32.c\r
	45	LShiftU64.c\r
	46	LRotU64.c\r
	47	LRotU32.c\r
	48	LowBitSet64.c\r
	49	LowBitSet32.c\r
	50	HighBitSet64.c\r
	51	HighBitSet32.c\r
	52	GetPowerOfTwo64.c\r
	53	GetPowerOfTwo32.c\r
	54	DivU64x64Remainder.c\r
	55	DivU64x32Remainder.c\r
	56	DivU64x32.c\r
	57	DivS64x64Remainder.c\r
	58	ARShiftU64.c\r
	59	BitField.c\r
	60	CpuDeadLoop.c\r
	61	Cpu.c\r
	62	LinkedList.c\r
	63	SafeString.c\r
	64	String.c\r
	65	FilePaths.c\r
	66	BaseLibInternals.h\r
	67	UnitTestHost.c\r
	68	UnitTestHost.h\r
	69	\r
	70	[Sources.Ia32]\r
744ad444 MK	71	Ia32/WriteMm7.c \| MSFT\r
	72	Ia32/WriteMm6.c \| MSFT\r
	73	Ia32/WriteMm5.c \| MSFT\r
	74	Ia32/WriteMm4.c \| MSFT\r
	75	Ia32/WriteMm3.c \| MSFT\r
	76	Ia32/WriteMm2.c \| MSFT\r
	77	Ia32/WriteMm1.c \| MSFT\r
	78	Ia32/WriteMm0.c \| MSFT\r
	79	Ia32/ReadMm7.c \| MSFT\r
	80	Ia32/ReadMm6.c \| MSFT\r
	81	Ia32/ReadMm5.c \| MSFT\r
	82	Ia32/ReadMm4.c \| MSFT\r
	83	Ia32/ReadMm3.c \| MSFT\r
	84	Ia32/ReadMm2.c \| MSFT\r
	85	Ia32/ReadMm1.c \| MSFT\r
	86	Ia32/ReadMm0.c \| MSFT\r
540fd45f MK	87	Ia32/SwapBytes64.c \| MSFT\r
	88	Ia32/RRotU64.c \| MSFT\r
	89	Ia32/RShiftU64.c \| MSFT\r
	90	Ia32/ReadTsc.c \| MSFT\r
	91	Ia32/ReadEflags.c \| MSFT\r
	92	Ia32/ModU64x32.c \| MSFT\r
	93	Ia32/MultU64x64.c \| MSFT\r
	94	Ia32/MultU64x32.c \| MSFT\r
	95	Ia32/LShiftU64.c \| MSFT\r
	96	Ia32/LRotU64.c \| MSFT\r
	97	Ia32/FxRestore.c \| MSFT\r
	98	Ia32/FxSave.c \| MSFT\r
	99	Ia32/DivU64x32Remainder.c \| MSFT\r
	100	Ia32/DivU64x32.c \| MSFT\r
	101	Ia32/CpuPause.c \| MSFT\r
	102	Ia32/CpuBreakpoint.c \| MSFT\r
	103	Ia32/ARShiftU64.c \| MSFT\r
	104	Ia32/GccInline.c \| GCC\r
	105	Ia32/LongJump.nasm\r
	106	Ia32/SetJump.nasm\r
	107	Ia32/SwapBytes64.nasm\| GCC\r
	108	Ia32/DivU64x64Remainder.nasm\r
	109	Ia32/DivU64x32Remainder.nasm\| GCC\r
	110	Ia32/ModU64x32.nasm\| GCC\r
	111	Ia32/DivU64x32.nasm\| GCC\r
	112	Ia32/MultU64x64.nasm\| GCC\r
	113	Ia32/MultU64x32.nasm\| GCC\r
	114	Ia32/RRotU64.nasm\| GCC\r
	115	Ia32/LRotU64.nasm\| GCC\r
	116	Ia32/ARShiftU64.nasm\| GCC\r
	117	Ia32/RShiftU64.nasm\| GCC\r
	118	Ia32/LShiftU64.nasm\| GCC\r
	119	Ia32/RdRand.nasm\r
	120	Ia32/DivS64x64Remainder.c\r
	121	Ia32/InternalSwitchStack.c \| MSFT\r
	122	Ia32/InternalSwitchStack.nasm \| GCC\r
	123	Ia32/Non-existing.c\r
	124	Unaligned.c\r
744ad444	125	X86MemoryFence.c \| MSFT\r
540fd45f MK	126	X86FxSave.c\r
	127	X86FxRestore.c\r
	128	X86Msr.c\r
	129	X86RdRand.c\r
	130	X86SpeculationBarrier.c\r
	131	X86UnitTestHost.c\r
d103840c	132	IntelTdxNull.c\r
540fd45f MK	133	\r
	134	[Sources.X64]\r
	135	X64/LongJump.nasm\r
	136	X64/SetJump.nasm\r
	137	X64/SwitchStack.nasm\r
	138	X64/CpuBreakpoint.c \| MSFT\r
	139	X64/CpuPause.nasm\| MSFT\r
	140	X64/ReadTsc.nasm\| MSFT\r
744ad444 MK	141	X64/WriteMm7.nasm\| MSFT\r
	142	X64/WriteMm6.nasm\| MSFT\r
	143	X64/WriteMm5.nasm\| MSFT\r
	144	X64/WriteMm4.nasm\| MSFT\r
	145	X64/WriteMm3.nasm\| MSFT\r
	146	X64/WriteMm2.nasm\| MSFT\r
	147	X64/WriteMm1.nasm\| MSFT\r
	148	X64/WriteMm0.nasm\| MSFT\r
	149	X64/ReadMm7.nasm\| MSFT\r
	150	X64/ReadMm6.nasm\| MSFT\r
	151	X64/ReadMm5.nasm\| MSFT\r
	152	X64/ReadMm4.nasm\| MSFT\r
	153	X64/ReadMm3.nasm\| MSFT\r
	154	X64/ReadMm2.nasm\| MSFT\r
	155	X64/ReadMm1.nasm\| MSFT\r
	156	X64/ReadMm0.nasm\| MSFT\r
540fd45f MK	157	X64/FxRestore.nasm\| MSFT\r
	158	X64/FxSave.nasm\| MSFT\r
	159	X64/ReadEflags.nasm\| MSFT\r
	160	X64/Non-existing.c\r
	161	Math64.c\r
	162	Unaligned.c\r
744ad444	163	X86MemoryFence.c \| MSFT\r
540fd45f MK	164	X86FxSave.c\r
	165	X86FxRestore.c\r
	166	X86Msr.c\r
	167	X86RdRand.c\r
	168	X86SpeculationBarrier.c\r
	169	X64/GccInline.c \| GCC\r
	170	X64/RdRand.nasm\r
	171	ChkStkGcc.c \| GCC\r
	172	X86UnitTestHost.c\r
d103840c	173	IntelTdxNull.c\r
540fd45f MK	174	\r
	175	[Sources.EBC]\r
	176	Ebc/CpuBreakpoint.c\r
	177	Ebc/SetJumpLongJump.c\r
	178	Ebc/SwitchStack.c\r
	179	Ebc/SpeculationBarrier.c\r
	180	Unaligned.c\r
	181	Math64.c\r
	182	\r
	183	[Sources.ARM]\r
	184	Arm/InternalSwitchStack.c\r
	185	Arm/Unaligned.c\r
540fd45f MK	186	Math64.c \| MSFT\r
540fd45f MK	187	\r
540fd45f MK	188	Arm/SwitchStack.asm \| MSFT\r
	189	Arm/SetJumpLongJump.asm \| MSFT\r
	190	Arm/CpuPause.asm \| MSFT\r
	191	Arm/CpuBreakpoint.asm \| MSFT\r
	192	Arm/MemoryFence.asm \| MSFT\r
	193	Arm/SpeculationBarrier.asm \| MSFT\r
	194	\r
	195	Arm/Math64.S \| GCC\r
	196	Arm/SwitchStack.S \| GCC\r
	197	Arm/SetJumpLongJump.S \| GCC\r
	198	Arm/CpuBreakpoint.S \| GCC\r
	199	Arm/MemoryFence.S \| GCC\r
	200	Arm/SpeculationBarrier.S \| GCC\r
	201	\r
	202	[Sources.AARCH64]\r
	203	Arm/InternalSwitchStack.c\r
	204	Arm/Unaligned.c\r
	205	Math64.c\r
	206	\r
	207	AArch64/MemoryFence.S \| GCC\r
	208	AArch64/SwitchStack.S \| GCC\r
	209	AArch64/SetJumpLongJump.S \| GCC\r
	210	AArch64/CpuBreakpoint.S \| GCC\r
	211	AArch64/SpeculationBarrier.S \| GCC\r
	212	\r
	213	AArch64/MemoryFence.asm \| MSFT\r
	214	AArch64/SwitchStack.asm \| MSFT\r
	215	AArch64/SetJumpLongJump.asm \| MSFT\r
	216	AArch64/CpuBreakpoint.asm \| MSFT\r
	217	AArch64/SpeculationBarrier.asm \| MSFT\r
	218	\r
	219	[Sources.RISCV64]\r
	220	Math64.c\r
	221	Unaligned.c\r
	222	RiscV64/InternalSwitchStack.c\r
	223	RiscV64/CpuBreakpoint.c\r
	224	RiscV64/CpuPause.c\r
	225	RiscV64/RiscVSetJumpLongJump.S \| GCC\r
	226	RiscV64/RiscVCpuBreakpoint.S \| GCC\r
	227	RiscV64/RiscVCpuPause.S \| GCC\r
	228	RiscV64/RiscVInterrupt.S \| GCC\r
	229	RiscV64/FlushCache.S \| GCC\r
	230	\r
	231	[Packages]\r
	232	MdePkg/MdePkg.dec\r
	233	\r
	234	[LibraryClasses]\r
	235	PcdLib\r
	236	DebugLib\r
	237	BaseMemoryLib\r
	238	\r
	239	[Pcd]\r
	240	gEfiMdePkgTokenSpaceGuid.PcdMaximumLinkedListLength ## SOMETIMES_CONSUMES\r
	241	gEfiMdePkgTokenSpaceGuid.PcdMaximumAsciiStringLength ## SOMETIMES_CONSUMES\r
	242	gEfiMdePkgTokenSpaceGuid.PcdMaximumUnicodeStringLength ## SOMETIMES_CONSUMES\r
	243	gEfiMdePkgTokenSpaceGuid.PcdControlFlowEnforcementPropertyMask ## SOMETIMES_CONSUMES\r
	244	gEfiMdePkgTokenSpaceGuid.PcdSpeculationBarrierType ## SOMETIMES_CONSUMES\r
	245	\r
	246	[FeaturePcd]\r
	247	gEfiMdePkgTokenSpaceGuid.PcdVerifyNodeInList ## CONSUMES\r