[mirror_edk2.git] / MdePkg / Library / BaseLib / X64 / Thunk16.S

#------------------------------------------------------------------------------\r
#\r
# Copyright (c) 2006 - 2008, Intel Corporation\r
# All rights reserved. This program and the accompanying materials\r
# are licensed and made available under the terms and conditions of the BSD License\r
# which accompanies this distribution.  The full text of the license may be found at\r
# http://opensource.org/licenses/bsd-license.php\r
#\r
# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
#\r
# Module Name:\r
#\r
#   Thunk16.S\r
#\r
# Abstract:\r
#\r
#   Real mode thunk\r
#\r
#------------------------------------------------------------------------------\r
\r
#include <Library/BaseLib.h>\r
\r
.globl ASM_PFX(m16Start)\r
.globl ASM_PFX(m16Size)\r
.globl ASM_PFX(mThunk16Attr)\r
.globl ASM_PFX(m16Gdt)\r
.globl ASM_PFX(m16GdtrBase)\r
.globl ASM_PFX(mTransition)\r
.globl ASM_PFX(InternalAsmThunk16)\r
\r
# define the structure of IA32_REGS\r
.equ  _EDI, 0       #size 4\r
.equ  _ESI, 4       #size 4\r
.equ  _EBP, 8       #size 4\r
.equ  _ESP, 12      #size 4\r
.equ  _EBX, 16      #size 4\r
.equ  _EDX, 20      #size 4\r
.equ  _ECX, 24      #size 4\r
.equ  _EAX, 28      #size 4\r
.equ  _DS,  32      #size 2\r
.equ  _ES,  34      #size 2\r
.equ  _FS,  36      #size 2\r
.equ  _GS,  38      #size 2\r
.equ  _EFLAGS, 40   #size 8\r
.equ  _EIP, 48      #size 4\r
.equ  _CS, 52       #size 2\r
.equ  _SS, 54       #size 2\r
.equ  IA32_REGS_SIZE, 56\r
\r
    .data\r
\r
ASM_PFX(m16Size):         .word      ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
ASM_PFX(mThunk16Attr):    .word      _ThunkAttr - ASM_PFX(m16Start)\r
ASM_PFX(m16Gdt):          .word      _NullSeg - ASM_PFX(m16Start)\r
ASM_PFX(m16GdtrBase):     .word      _16GdtrBase - ASM_PFX(m16Start)\r
ASM_PFX(mTransition):     .word      _EntryPoint - ASM_PFX(m16Start)\r
\r
    .text\r
\r
ASM_PFX(m16Start):\r
\r
SavedGdt:    .space 10\r
\r
#------------------------------------------------------------------------------\r
# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
# by user code. It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
.globl ASM_PFX(BackFromUserCode)\r
ASM_PFX(BackFromUserCode):\r
    #\r
    # The order of saved registers on the stack matches the order they appears\r
    # in IA32_REGS structure. This facilitates wrapper function to extract them\r
    # into that structure.\r
    #\r
    # Some instructions for manipulation of segment registers have to be written\r
    # in opcode since 64-bit MASM prevents accesses to those registers.\r
    #\r
    .byte 0x16                          # push ss\r
    .byte 0xe                           # push cs\r
    .byte 0x66\r
    call    L_Base                       # push eip\r
L_Base: \r
    .byte 0x66\r
    pushq   $0                          # reserved high order 32 bits of EFlags\r
    .byte 0x66, 0x9c                    # pushfd actually\r
    cli                                 # disable interrupts\r
    push    %gs\r
    push    %fs\r
    .byte 6                             # push es\r
    .byte 0x1e                          # push ds\r
    .byte 0x66,0x60                     # pushad\r
    .byte 0x66,0xba                     # mov edx, imm32\r
_ThunkAttr:  .space  4\r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
    jz      L_1\r
    movl    $0x15cd2401,%eax            # mov ax, 2401h & int 15h\r
    cli                                 # disable interrupts\r
    jnc     L_2\r
L_1: \r
    testb   $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
    jz      L_2\r
    inb     $0x92,%al\r
    orb     $2,%al\r
    outb    %al, $0x92                   # deactivate A20M#\r
L_2: \r
    movl    %ss,%eax\r
    lea     IA32_REGS_SIZE(%esp), %bp\r
    #\r
    # rsi in the following 2 instructions is indeed bp in 16-bit code\r
    #\r
    movw    %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
    .byte 0x66\r
    movl    (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
    shlw    $4,%ax                      # shl eax, 4\r
    addw    %ax,%bp                     # add ebp, eax\r
    movw    %cs,%ax\r
    shlw    $4,%ax\r
    lea     (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
    .byte 0x66,0x2e,0x89,0x87           # mov cs:[bx + (L_64Eip - L_Base)], eax\r
    .word   L_64Eip - L_Base\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr4:   .space  4\r
    movq    %rax, %cr4\r
    #\r
    # rdi in the instruction below is indeed bx in 16-bit code\r
    #\r
    .byte 0x66,0x2e                     # 2eh is "cs:" segment override\r
    lgdt    (SavedGdt - L_Base)(%rdi)\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    rdmsr\r
    orb     $1,%ah\r
    wrmsr\r
    .byte 0x66,0xb8                     # mov eax, imm32\r
SavedCr0:    .space      4\r
    movq    %rax, %cr0\r
    .byte 0x66,0xea                     # jmp far cs:L_64Bit\r
L_64Eip:      .space      4\r
SavedCs:     .space      2\r
L_64BitCode: \r
    movq     %r8, %rsp\r
    ret\r
\r
_EntryPoint: .long      ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
             .word      CODE16\r
_16Gdtr:     .word      GDT_SIZE - 1\r
_16GdtrBase: .quad      _NullSeg\r
_16Idtr:     .word      0x3ff\r
             .long      0\r
\r
#------------------------------------------------------------------------------\r
# _ToUserCode() takes control in real mode before passing control to user code.\r
# It will be shadowed to somewhere in memory below 1MB.\r
#------------------------------------------------------------------------------\r
.globl ASM_PFX(ToUserCode)\r
ASM_PFX(ToUserCode):\r
    movl    %edx,%ss                    # set new segment selectors\r
    movl    %edx,%ds\r
    movl    %edx,%es\r
    movl    %edx,%fs\r
    movl    %edx,%gs\r
    .byte 0x66\r
    movl    $0xc0000080,%ecx\r
    movq    %rax, %cr0\r
    rdmsr\r
    andb    $0b11111110, %ah \r
    wrmsr\r
    movq    %rbp, %cr4\r
    movl    %esi,%ss                    # set up 16-bit stack segment\r
    movw    %bx,%sp                     # set up 16-bit stack pointer\r
    .byte 0x66                          # make the following call 32-bit\r
    call    L_Base1                       # push eip\r
L_Base1: \r
    popw    %bp                         # ebp <- address of L_Base1\r
    pushq   (IA32_REGS_SIZE + 2)(%esp)\r
    lea     0x0c(%rsi), %eax\r
    pushq   %rax\r
    lret                                # execution begins at next instruction\r
L_RealMode: \r
    .byte 0x66,0x2e                     # CS and operand size override\r
    lidt    (_16Idtr - L_Base1)(%rsi)\r
    .byte 0x66,0x61                     # popad\r
    .byte 0x1f                          # pop ds\r
    .byte 0x7                           # pop es\r
    .byte 0x0f, 0xa1                    # pop fs\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x66, 0x9d                    # popfd\r
    leaw    4(%esp),%sp                 # skip high order 32 bits of EFlags\r
    .byte 0x66                          # make the following retf 32-bit\r
    lret                                # transfer control to user code\r
\r
.equ  CODE16,  ASM_PFX(16Code) - .\r
.equ  DATA16,  ASM_PFX(16Data) - .\r
.equ  DATA32,  ASM_PFX(32Data) - .\r
\r
_NullSeg:   .quad      0\r
ASM_PFX(16Code):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x9b\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(16Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0x8f                  # 16-bit segment, 4GB limit\r
            .byte 0\r
ASM_PFX(32Data):\r
            .word -1\r
            .word 0\r
            .byte 0\r
            .byte 0x93\r
            .byte 0xcf                  # 16-bit segment, 4GB limit\r
            .byte 0\r
\r
.equ  GDT_SIZE, . - ASM_PFX(NullSeg)\r
\r
#------------------------------------------------------------------------------\r
# IA32_REGISTER_SET *\r
# EFIAPI\r
# InternalAsmThunk16 (\r
#   IN      IA32_REGISTER_SET         *RegisterSet,\r
#   IN OUT  VOID                      *Transition\r
#   );\r
#------------------------------------------------------------------------------\r
# MISMATCH: "InternalAsmThunk16  PROC    USES    rbp rbx rsi rdi"\r
\r
.globl ASM_PFX(InternalAsmThunk16)\r
ASM_PFX(InternalAsmThunk16):\r
    pushq   %rbp\r
    pushq   %rbx\r
    pushq   %rsi\r
    pushq   %rdi\r
    \r
    movl    %ds, %r10d                  # r9 ~ r11 are not accessible in 16-bit\r
    movl    %es, %r11d                  # so use them for saving seg registers\r
    movl    %ss, %r9d\r
    .byte   0x0f, 0xa0                  #push   fs\r
    .byte   0x0f, 0xa8                  #push   gs\r
    movq    %rcx, %rsi\r
    movzwl  _SS(%rsi), %r8d\r
    movl    _ESP(%rsi), %edi\r
    lea     -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
    imul    $16, %r8d, %eax \r
    movl    %edi,%ebx                   # ebx <- stack for 16-bit code\r
    pushq   $(IA32_REGS_SIZE / 4)\r
    addl    %eax,%edi                   # edi <- linear address of 16-bit stack\r
    popq    %rcx\r
    rep\r
    movsl                               # copy RegSet\r
    lea     (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
    movl    %edx,%eax                   # eax <- transition code address\r
    andl    $0xf,%edx\r
    shll    $12,%eax                    # segment address in high order 16 bits\r
    lea     (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
    stosl                               # [edi] <- return address of user code\r
    sgdt    (SavedGdt - SavedCr4)(%rcx) \r
    sidt    0x38(%rsp)\r
    movq    %cr0, %rax\r
    movl    %eax, (SavedCr0 - SavedCr4)(%rcx)\r
    andl    $0x7ffffffe,%eax            # clear PE, PG bits\r
    movq    %cr4, %rbp\r
    movl    %ebp, (%rcx)                # save CR4 in SavedCr4\r
    andl    $0x300,%ebp                 # clear all but PCE and OSFXSR bits\r
    movl    %r8d, %esi                  # esi <- 16-bit stack segment\r
    .byte      0x6a, DATA32\r
    popq    %rdx\r
    lgdt    (_16Gdtr - SavedCr4)(%rcx)\r
    movl    %edx,%ss\r
    pushfq\r
    lea     -8(%rdx), %edx\r
    lea     L_RetFromRealMode, %r8\r
    pushq   %r8\r
    movl    %cs, %r8d\r
    movw    %r8w, (SavedCs - SavedCr4)(%rcx)\r
    movq     %rsp, %r8\r
    .byte   0xff, 0x69                  #  jmp (_EntryPoint - SavedCr4)(%rcx)\r
    .byte   _EntryPoint - SavedCr4\r
L_RetFromRealMode: \r
    popfq\r
    lidt    0x38(%rsp)\r
    lea     -IA32_REGS_SIZE(%rbp), %eax\r
    .byte 0x0f, 0xa9                    # pop gs\r
    .byte 0x0f, 0xa1                    # pop fs\r
    movl    %r9d, %ss\r
    movl    %r11d, %es\r
    movl    %r10d, %ds\r
    \r
    popq    %rdi\r
    popq    %rsi\r
    popq    %rbx\r
    popq    %rbp\r
\r
    ret\r
Commit	Line	Data
b1ff428c	1	#------------------------------------------------------------------------------\r
	2	#\r
	3	# Copyright (c) 2006 - 2008, Intel Corporation\r
	4	# All rights reserved. This program and the accompanying materials\r
	5	# are licensed and made available under the terms and conditions of the BSD License\r
	6	# which accompanies this distribution. The full text of the license may be found at\r
	7	# http://opensource.org/licenses/bsd-license.php\r
	8	#\r
	9	# THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	10	# WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	11	#\r
	12	# Module Name:\r
	13	#\r
	14	# Thunk16.S\r
	15	#\r
	16	# Abstract:\r
	17	#\r
	18	# Real mode thunk\r
	19	#\r
	20	#------------------------------------------------------------------------------\r
	21	\r
	22	#include <Library/BaseLib.h>\r
	23	\r
	24	.globl ASM_PFX(m16Start)\r
	25	.globl ASM_PFX(m16Size)\r
	26	.globl ASM_PFX(mThunk16Attr)\r
	27	.globl ASM_PFX(m16Gdt)\r
	28	.globl ASM_PFX(m16GdtrBase)\r
	29	.globl ASM_PFX(mTransition)\r
	30	.globl ASM_PFX(InternalAsmThunk16)\r
	31	\r
	32	# define the structure of IA32_REGS\r
	33	.equ _EDI, 0 #size 4\r
	34	.equ _ESI, 4 #size 4\r
	35	.equ _EBP, 8 #size 4\r
	36	.equ _ESP, 12 #size 4\r
	37	.equ _EBX, 16 #size 4\r
	38	.equ _EDX, 20 #size 4\r
	39	.equ _ECX, 24 #size 4\r
	40	.equ _EAX, 28 #size 4\r
	41	.equ _DS, 32 #size 2\r
	42	.equ _ES, 34 #size 2\r
	43	.equ _FS, 36 #size 2\r
	44	.equ _GS, 38 #size 2\r
	45	.equ _EFLAGS, 40 #size 8\r
	46	.equ _EIP, 48 #size 4\r
	47	.equ _CS, 52 #size 2\r
	48	.equ _SS, 54 #size 2\r
	49	.equ IA32_REGS_SIZE, 56\r
	50	\r
	51	.data\r
	52	\r
	53	ASM_PFX(m16Size): .word ASM_PFX(InternalAsmThunk16) - ASM_PFX(m16Start)\r
	54	ASM_PFX(mThunk16Attr): .word _ThunkAttr - ASM_PFX(m16Start)\r
	55	ASM_PFX(m16Gdt): .word _NullSeg - ASM_PFX(m16Start)\r
	56	ASM_PFX(m16GdtrBase): .word _16GdtrBase - ASM_PFX(m16Start)\r
	57	ASM_PFX(mTransition): .word _EntryPoint - ASM_PFX(m16Start)\r
	58	\r
	59	.text\r
	60	\r
	61	ASM_PFX(m16Start):\r
	62	\r
	63	SavedGdt: .space 10\r
	64	\r
65	#------------------------------------------------------------------------------\r
66	# _BackFromUserCode() takes control in real mode after 'retf' has been executed\r
67	# by user code. It will be shadowed to somewhere in memory below 1MB.\r
68	#------------------------------------------------------------------------------\r
69	.globl ASM_PFX(BackFromUserCode)\r
70	ASM_PFX(BackFromUserCode):\r
71	#\r
72	# The order of saved registers on the stack matches the order they appears\r
73	# in IA32_REGS structure. This facilitates wrapper function to extract them\r
74	# into that structure.\r
75	#\r
76	# Some instructions for manipulation of segment registers have to be written\r
77	# in opcode since 64-bit MASM prevents accesses to those registers.\r
78	#\r
79	.byte 0x16 # push ss\r
80	.byte 0xe # push cs\r
81	.byte 0x66\r
82	call L_Base # push eip\r
83	L_Base: \r
84	.byte 0x66\r
85	pushq $0 # reserved high order 32 bits of EFlags\r
86	.byte 0x66, 0x9c # pushfd actually\r
87	cli # disable interrupts\r
88	push %gs\r
89	push %fs\r
90	.byte 6 # push es\r
91	.byte 0x1e # push ds\r
92	.byte 0x66,0x60 # pushad\r
93	.byte 0x66,0xba # mov edx, imm32\r
94	_ThunkAttr: .space 4\r
95	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15, %dl\r
96	jz L_1\r
97	movl $0x15cd2401,%eax # mov ax, 2401h & int 15h\r
98	cli # disable interrupts\r
99	jnc L_2\r
100	L_1: \r
101	testb $THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL, %dl\r
102	jz L_2\r
103	inb $0x92,%al\r
104	orb $2,%al\r
105	outb %al, $0x92 # deactivate A20M#\r
106	L_2: \r
107	movl %ss,%eax\r
108	lea IA32_REGS_SIZE(%esp), %bp\r
109	#\r
110	# rsi in the following 2 instructions is indeed bp in 16-bit code\r
111	#\r
112	movw %bp, (_ESP - IA32_REGS_SIZE)(%rsi)\r
113	.byte 0x66\r
114	movl (_EIP - IA32_REGS_SIZE)(%rsi), %ebx\r
115	shlw $4,%ax # shl eax, 4\r
116	addw %ax,%bp # add ebp, eax\r
117	movw %cs,%ax\r
118	shlw $4,%ax\r
119	lea (L_64BitCode - L_Base)(%ebx, %eax), %ax\r
120	.byte 0x66,0x2e,0x89,0x87 # mov cs:[bx + (L_64Eip - L_Base)], eax\r
121	.word L_64Eip - L_Base\r
122	.byte 0x66,0xb8 # mov eax, imm32\r
123	SavedCr4: .space 4\r
124	movq %rax, %cr4\r
125	#\r
126	# rdi in the instruction below is indeed bx in 16-bit code\r
127	#\r
128	.byte 0x66,0x2e # 2eh is "cs:" segment override\r
129	lgdt (SavedGdt - L_Base)(%rdi)\r
130	.byte 0x66\r
131	movl $0xc0000080,%ecx\r
132	rdmsr\r
133	orb $1,%ah\r
134	wrmsr\r
135	.byte 0x66,0xb8 # mov eax, imm32\r
136	SavedCr0: .space 4\r
137	movq %rax, %cr0\r
138	.byte 0x66,0xea # jmp far cs:L_64Bit\r
139	L_64Eip: .space 4\r
140	SavedCs: .space 2\r
141	L_64BitCode: \r
142	movq %r8, %rsp\r
143	ret\r
144	\r
145	_EntryPoint: .long ASM_PFX(ToUserCode) - ASM_PFX(m16Start)\r
146	.word CODE16\r
147	_16Gdtr: .word GDT_SIZE - 1\r
148	_16GdtrBase: .quad _NullSeg\r
149	_16Idtr: .word 0x3ff\r
150	.long 0\r
151	\r
152	#------------------------------------------------------------------------------\r
153	# _ToUserCode() takes control in real mode before passing control to user code.\r
154	# It will be shadowed to somewhere in memory below 1MB.\r
155	#------------------------------------------------------------------------------\r
156	.globl ASM_PFX(ToUserCode)\r
157	ASM_PFX(ToUserCode):\r
158	movl %edx,%ss # set new segment selectors\r
159	movl %edx,%ds\r
160	movl %edx,%es\r
161	movl %edx,%fs\r
162	movl %edx,%gs\r
163	.byte 0x66\r
164	movl $0xc0000080,%ecx\r
165	movq %rax, %cr0\r
166	rdmsr\r
167	andb $0b11111110, %ah \r
168	wrmsr\r
169	movq %rbp, %cr4\r
170	movl %esi,%ss # set up 16-bit stack segment\r
171	movw %bx,%sp # set up 16-bit stack pointer\r
172	.byte 0x66 # make the following call 32-bit\r
173	call L_Base1 # push eip\r
174	L_Base1: \r
175	popw %bp # ebp <- address of L_Base1\r
176	pushq (IA32_REGS_SIZE + 2)(%esp)\r
177	lea 0x0c(%rsi), %eax\r
178	pushq %rax\r
179	lret # execution begins at next instruction\r
180	L_RealMode: \r
181	.byte 0x66,0x2e # CS and operand size override\r
182	lidt (_16Idtr - L_Base1)(%rsi)\r
183	.byte 0x66,0x61 # popad\r
184	.byte 0x1f # pop ds\r
185	.byte 0x7 # pop es\r
186	.byte 0x0f, 0xa1 # pop fs\r
187	.byte 0x0f, 0xa9 # pop gs\r
188	.byte 0x66, 0x9d # popfd\r
189	leaw 4(%esp),%sp # skip high order 32 bits of EFlags\r
190	.byte 0x66 # make the following retf 32-bit\r
191	lret # transfer control to user code\r
192	\r
193	.equ CODE16, ASM_PFX(16Code) - .\r
194	.equ DATA16, ASM_PFX(16Data) - .\r
195	.equ DATA32, ASM_PFX(32Data) - .\r
196	\r
197	_NullSeg: .quad 0\r
198	ASM_PFX(16Code):\r
199	.word -1\r
200	.word 0\r
201	.byte 0\r
202	.byte 0x9b\r
203	.byte 0x8f # 16-bit segment, 4GB limit\r
204	.byte 0\r
205	ASM_PFX(16Data):\r
206	.word -1\r
207	.word 0\r
208	.byte 0\r
209	.byte 0x93\r
210	.byte 0x8f # 16-bit segment, 4GB limit\r
211	.byte 0\r
212	ASM_PFX(32Data):\r
213	.word -1\r
214	.word 0\r
215	.byte 0\r
216	.byte 0x93\r
217	.byte 0xcf # 16-bit segment, 4GB limit\r
218	.byte 0\r
219	\r
220	.equ GDT_SIZE, . - ASM_PFX(NullSeg)\r
221	\r
222	#------------------------------------------------------------------------------\r
223	# IA32_REGISTER_SET *\r
224	# EFIAPI\r
225	# InternalAsmThunk16 (\r
226	# IN IA32_REGISTER_SET *RegisterSet,\r
227	# IN OUT VOID *Transition\r
228	# );\r
229	#------------------------------------------------------------------------------\r
230	# MISMATCH: "InternalAsmThunk16 PROC USES rbp rbx rsi rdi"\r
231	\r
232	.globl ASM_PFX(InternalAsmThunk16)\r
233	ASM_PFX(InternalAsmThunk16):\r
234	pushq %rbp\r
235	pushq %rbx\r
236	pushq %rsi\r
237	pushq %rdi\r
238	\r
239	movl %ds, %r10d # r9 ~ r11 are not accessible in 16-bit\r
240	movl %es, %r11d # so use them for saving seg registers\r
241	movl %ss, %r9d\r
242	.byte 0x0f, 0xa0 #push fs\r
243	.byte 0x0f, 0xa8 #push gs\r
244	movq %rcx, %rsi\r
245	movzwl _SS(%rsi), %r8d\r
246	movl _ESP(%rsi), %edi\r
247	lea -(IA32_REGS_SIZE + 4)(%edi), %rdi\r
248	imul $16, %r8d, %eax \r
249	movl %edi,%ebx # ebx <- stack for 16-bit code\r
250	pushq $(IA32_REGS_SIZE / 4)\r
251	addl %eax,%edi # edi <- linear address of 16-bit stack\r
252	popq %rcx\r
253	rep\r
254	movsl # copy RegSet\r
255	lea (SavedCr4 - ASM_PFX(m16Start))(%rdx), %ecx\r
256	movl %edx,%eax # eax <- transition code address\r
257	andl $0xf,%edx\r
258	shll $12,%eax # segment address in high order 16 bits\r
259	lea (_BackFromUserCode - ASM_PFX(m16Start))(%rdx), %ax\r
260	stosl # [edi] <- return address of user code\r
261	sgdt (SavedGdt - SavedCr4)(%rcx) \r
262	sidt 0x38(%rsp)\r
263	movq %cr0, %rax\r
264	movl %eax, (SavedCr0 - SavedCr4)(%rcx)\r
265	andl $0x7ffffffe,%eax # clear PE, PG bits\r
266	movq %cr4, %rbp\r
267	movl %ebp, (%rcx) # save CR4 in SavedCr4\r
268	andl $0x300,%ebp # clear all but PCE and OSFXSR bits\r
269	movl %r8d, %esi # esi <- 16-bit stack segment\r
270	.byte 0x6a, DATA32\r
271	popq %rdx\r
272	lgdt (_16Gdtr - SavedCr4)(%rcx)\r
273	movl %edx,%ss\r
274	pushfq\r
275	lea -8(%rdx), %edx\r
276	lea L_RetFromRealMode, %r8\r
277	pushq %r8\r
278	movl %cs, %r8d\r
279	movw %r8w, (SavedCs - SavedCr4)(%rcx)\r
280	movq %rsp, %r8\r
281	.byte 0xff, 0x69 # jmp (_EntryPoint - SavedCr4)(%rcx)\r
282	.byte _EntryPoint - SavedCr4\r
283	L_RetFromRealMode: \r
284	popfq\r
285	lidt 0x38(%rsp)\r
286	lea -IA32_REGS_SIZE(%rbp), %eax\r
287	.byte 0x0f, 0xa9 # pop gs\r
288	.byte 0x0f, 0xa1 # pop fs\r
289	movl %r9d, %ss\r
290	movl %r11d, %es\r
291	movl %r10d, %ds\r
292	\r
293	popq %rdi\r
294	popq %rsi\r
295	popq %rbx\r
296	popq %rbp\r
297	\r
298	ret\r