projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 540fd45f MK |
1 | /** @file\r |
| 2 | IA32/X64 specific Unit Test Host functions.\r | |
| 3 | \r | |
| 4 | Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r | |
| 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | \r | |
| 7 | **/\r | |
| 8 | \r | |
| 9 | #include "UnitTestHost.h"\r | |
| 10 | \r | |
| 11 | ///\r | |
| 12 | /// Defines for mUnitTestHostBaseLibSegment indexes\r | |
| 13 | ///\r | |
| 14 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS 0\r | |
| 15 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS 1\r | |
| 16 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES 2\r | |
| 17 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS 3\r | |
| 18 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS 4\r | |
| 19 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS 5\r | |
| 20 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR 6\r | |
| 21 | #define UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR 7\r | |
| 22 | \r | |
| 23 | ///\r | |
| 24 | /// Module global variables for simple system emulation of MSRs, CRx, DRx,\r | |
| 25 | /// GDTR, IDTR, and Segment Selectors.\r | |
| 26 | ///\r | |
| 27 | STATIC UINT64 mUnitTestHostBaseLibMsr[2][0x1000];\r | |
| 28 | STATIC UINTN mUnitTestHostBaseLibCr[5];\r | |
| 29 | STATIC UINTN mUnitTestHostBaseLibDr[8];\r | |
| 30 | STATIC UINT16 mUnitTestHostBaseLibSegment[8];\r | |
| 31 | STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibGdtr;\r | |
| 32 | STATIC IA32_DESCRIPTOR mUnitTestHostBaseLibIdtr;\r | |
| 33 | \r | |
| 34 | /**\r | |
| 35 | Retrieves CPUID information.\r | |
| 36 | \r | |
| 37 | Executes the CPUID instruction with EAX set to the value specified by Index.\r | |
| 38 | This function always returns Index.\r | |
| 39 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
| 40 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
| 41 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
| 42 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
| 43 | This function is only available on IA-32 and x64.\r | |
| 44 | \r | |
| 45 | @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r | |
| 46 | instruction.\r | |
| 47 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
| 48 | instruction. This is an optional parameter that may be NULL.\r | |
| 49 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
| 50 | instruction. This is an optional parameter that may be NULL.\r | |
| 51 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
| 52 | instruction. This is an optional parameter that may be NULL.\r | |
| 53 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
| 54 | instruction. This is an optional parameter that may be NULL.\r | |
| 55 | \r | |
| 56 | @return Index.\r | |
| 57 | \r | |
| 58 | **/\r | |
| 59 | UINT32\r | |
| 60 | EFIAPI\r | |
| 61 | UnitTestHostBaseLibAsmCpuid (\r | |
| 62 | IN UINT32 Index,\r | |
| d0e2f823 MK |
63 | OUT UINT32 *Eax OPTIONAL,\r |
| 64 | OUT UINT32 *Ebx OPTIONAL,\r | |
| 65 | OUT UINT32 *Ecx OPTIONAL,\r | |
| 540fd45f MK |
66 | OUT UINT32 *Edx OPTIONAL\r |
| 67 | )\r | |
| 68 | {\r | |
| 69 | if (Eax != NULL) {\r | |
| 70 | *Eax = 0;\r | |
| 71 | }\r | |
| 72 | if (Ebx != NULL) {\r | |
| 73 | *Ebx = 0;\r | |
| 74 | }\r | |
| 75 | if (Ecx != NULL) {\r | |
| 76 | *Ecx = 0;\r | |
| 77 | }\r | |
| 78 | if (Edx != NULL) {\r | |
| 79 | *Edx = 0;\r | |
| 80 | }\r | |
| 81 | return Index;\r | |
| 82 | }\r | |
| 83 | \r | |
| 84 | /**\r | |
| 85 | Retrieves CPUID information using an extended leaf identifier.\r | |
| 86 | \r | |
| 87 | Executes the CPUID instruction with EAX set to the value specified by Index\r | |
| 88 | and ECX set to the value specified by SubIndex. This function always returns\r | |
| 89 | Index. This function is only available on IA-32 and x64.\r | |
| 90 | \r | |
| 91 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
| 92 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
| 93 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
| 94 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
| 95 | \r | |
| 96 | @param Index The 32-bit value to load into EAX prior to invoking the\r | |
| 97 | CPUID instruction.\r | |
| 98 | @param SubIndex The 32-bit value to load into ECX prior to invoking the\r | |
| 99 | CPUID instruction.\r | |
| 100 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
| 101 | instruction. This is an optional parameter that may be\r | |
| 102 | NULL.\r | |
| 103 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
| 104 | instruction. This is an optional parameter that may be\r | |
| 105 | NULL.\r | |
| 106 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
| 107 | instruction. This is an optional parameter that may be\r | |
| 108 | NULL.\r | |
| 109 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
| 110 | instruction. This is an optional parameter that may be\r | |
| 111 | NULL.\r | |
| 112 | \r | |
| 113 | @return Index.\r | |
| 114 | \r | |
| 115 | **/\r | |
| 116 | UINT32\r | |
| 117 | EFIAPI\r | |
| 118 | UnitTestHostBaseLibAsmCpuidEx (\r | |
| 119 | IN UINT32 Index,\r | |
| 120 | IN UINT32 SubIndex,\r | |
| d0e2f823 MK |
121 | OUT UINT32 *Eax OPTIONAL,\r |
| 122 | OUT UINT32 *Ebx OPTIONAL,\r | |
| 123 | OUT UINT32 *Ecx OPTIONAL,\r | |
| 540fd45f MK |
124 | OUT UINT32 *Edx OPTIONAL\r |
| 125 | )\r | |
| 126 | {\r | |
| 127 | if (Eax != NULL) {\r | |
| 128 | *Eax = 0;\r | |
| 129 | }\r | |
| 130 | if (Ebx != NULL) {\r | |
| 131 | *Ebx = 0;\r | |
| 132 | }\r | |
| 133 | if (Ecx != NULL) {\r | |
| 134 | *Ecx = 0;\r | |
| 135 | }\r | |
| 136 | if (Edx != NULL) {\r | |
| 137 | *Edx = 0;\r | |
| 138 | }\r | |
| 139 | return Index;\r | |
| 140 | }\r | |
| 141 | \r | |
| 142 | /**\r | |
| 143 | Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r | |
| 144 | \r | |
| 145 | Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r | |
| 146 | and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r | |
| 147 | \r | |
| 148 | **/\r | |
| 149 | VOID\r | |
| 150 | EFIAPI\r | |
| 151 | UnitTestHostBaseLibAsmDisableCache (\r | |
| 152 | VOID\r | |
| 153 | )\r | |
| 154 | {\r | |
| 155 | }\r | |
| 156 | \r | |
| 157 | /**\r | |
| 158 | Perform a WBINVD and clear both the CD and NW bits of CR0.\r | |
| 159 | \r | |
| 160 | Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r | |
| 161 | bits of CR0 to 0. This function is only available on IA-32 and x64.\r | |
| 162 | \r | |
| 163 | **/\r | |
| 164 | VOID\r | |
| 165 | EFIAPI\r | |
| 166 | UnitTestHostBaseLibAsmEnableCache (\r | |
| 167 | VOID\r | |
| 168 | )\r | |
| 169 | {\r | |
| 170 | }\r | |
| 171 | \r | |
| 172 | /**\r | |
| 173 | Returns a 64-bit Machine Specific Register(MSR).\r | |
| 174 | \r | |
| 175 | Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r | |
| 176 | performed on Index, and some Index values may cause CPU exceptions. The\r | |
| 177 | caller must either guarantee that Index is valid, or the caller must set up\r | |
| 178 | exception handlers to catch the exceptions. This function is only available\r | |
| 179 | on IA-32 and x64.\r | |
| 180 | \r | |
| 181 | @param Index The 32-bit MSR index to read.\r | |
| 182 | \r | |
| 183 | @return The value of the MSR identified by Index.\r | |
| 184 | \r | |
| 185 | **/\r | |
| 186 | UINT64\r | |
| 187 | EFIAPI\r | |
| 188 | UnitTestHostBaseLibAsmReadMsr64 (\r | |
| 189 | IN UINT32 Index\r | |
| 190 | )\r | |
| 191 | {\r | |
| 192 | if (Index < 0x1000) {\r | |
| 193 | return mUnitTestHostBaseLibMsr[0][Index];\r | |
| 194 | }\r | |
| 195 | if (Index >= 0xC0000000 && Index < 0xC0001000) {\r | |
| 196 | return mUnitTestHostBaseLibMsr[1][Index];\r | |
| 197 | }\r | |
| 198 | return 0;\r | |
| 199 | }\r | |
| 200 | \r | |
| 201 | /**\r | |
| 202 | Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r | |
| 203 | value.\r | |
| 204 | \r | |
| 205 | Writes the 64-bit value specified by Value to the MSR specified by Index. The\r | |
| 206 | 64-bit value written to the MSR is returned. No parameter checking is\r | |
| 207 | performed on Index or Value, and some of these may cause CPU exceptions. The\r | |
| 208 | caller must either guarantee that Index and Value are valid, or the caller\r | |
| 209 | must establish proper exception handlers. This function is only available on\r | |
| 210 | IA-32 and x64.\r | |
| 211 | \r | |
| 212 | @param Index The 32-bit MSR index to write.\r | |
| 213 | @param Value The 64-bit value to write to the MSR.\r | |
| 214 | \r | |
| 215 | @return Value\r | |
| 216 | \r | |
| 217 | **/\r | |
| 218 | UINT64\r | |
| 219 | EFIAPI\r | |
| 220 | UnitTestHostBaseLibAsmWriteMsr64 (\r | |
| 221 | IN UINT32 Index,\r | |
| 222 | IN UINT64 Value\r | |
| 223 | )\r | |
| 224 | {\r | |
| 225 | if (Index < 0x1000) {\r | |
| 226 | mUnitTestHostBaseLibMsr[0][Index] = Value;\r | |
| 227 | }\r | |
| 228 | if (Index >= 0xC0000000 && Index < 0xC0001000) {\r | |
| 229 | mUnitTestHostBaseLibMsr[1][Index - 0xC00000000] = Value;\r | |
| 230 | }\r | |
| 231 | return Value;\r | |
| 232 | }\r | |
| 233 | \r | |
| 234 | /**\r | |
| 235 | Reads the current value of the Control Register 0 (CR0).\r | |
| 236 | \r | |
| 237 | Reads and returns the current value of CR0. This function is only available\r | |
| 238 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 239 | x64.\r | |
| 240 | \r | |
| 241 | @return The value of the Control Register 0 (CR0).\r | |
| 242 | \r | |
| 243 | **/\r | |
| 244 | UINTN\r | |
| 245 | EFIAPI\r | |
| 246 | UnitTestHostBaseLibAsmReadCr0 (\r | |
| 247 | VOID\r | |
| 248 | )\r | |
| 249 | {\r | |
| 250 | return mUnitTestHostBaseLibCr[0];\r | |
| 251 | }\r | |
| 252 | \r | |
| 253 | /**\r | |
| 254 | Reads the current value of the Control Register 2 (CR2).\r | |
| 255 | \r | |
| 256 | Reads and returns the current value of CR2. This function is only available\r | |
| 257 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 258 | x64.\r | |
| 259 | \r | |
| 260 | @return The value of the Control Register 2 (CR2).\r | |
| 261 | \r | |
| 262 | **/\r | |
| 263 | UINTN\r | |
| 264 | EFIAPI\r | |
| 265 | UnitTestHostBaseLibAsmReadCr2 (\r | |
| 266 | VOID\r | |
| 267 | )\r | |
| 268 | {\r | |
| 269 | return mUnitTestHostBaseLibCr[2];\r | |
| 270 | }\r | |
| 271 | \r | |
| 272 | /**\r | |
| 273 | Reads the current value of the Control Register 3 (CR3).\r | |
| 274 | \r | |
| 275 | Reads and returns the current value of CR3. This function is only available\r | |
| 276 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 277 | x64.\r | |
| 278 | \r | |
| 279 | @return The value of the Control Register 3 (CR3).\r | |
| 280 | \r | |
| 281 | **/\r | |
| 282 | UINTN\r | |
| 283 | EFIAPI\r | |
| 284 | UnitTestHostBaseLibAsmReadCr3 (\r | |
| 285 | VOID\r | |
| 286 | )\r | |
| 287 | {\r | |
| 288 | return mUnitTestHostBaseLibCr[3];\r | |
| 289 | }\r | |
| 290 | \r | |
| 291 | /**\r | |
| 292 | Reads the current value of the Control Register 4 (CR4).\r | |
| 293 | \r | |
| 294 | Reads and returns the current value of CR4. This function is only available\r | |
| 295 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 296 | x64.\r | |
| 297 | \r | |
| 298 | @return The value of the Control Register 4 (CR4).\r | |
| 299 | \r | |
| 300 | **/\r | |
| 301 | UINTN\r | |
| 302 | EFIAPI\r | |
| 303 | UnitTestHostBaseLibAsmReadCr4 (\r | |
| 304 | VOID\r | |
| 305 | )\r | |
| 306 | {\r | |
| 307 | return mUnitTestHostBaseLibCr[4];\r | |
| 308 | }\r | |
| 309 | \r | |
| 310 | /**\r | |
| 311 | Writes a value to Control Register 0 (CR0).\r | |
| 312 | \r | |
| 313 | Writes and returns a new value to CR0. This function is only available on\r | |
| 314 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 315 | \r | |
| 316 | @param Cr0 The value to write to CR0.\r | |
| 317 | \r | |
| 318 | @return The value written to CR0.\r | |
| 319 | \r | |
| 320 | **/\r | |
| 321 | UINTN\r | |
| 322 | EFIAPI\r | |
| 323 | UnitTestHostBaseLibAsmWriteCr0 (\r | |
| 324 | UINTN Cr0\r | |
| 325 | )\r | |
| 326 | {\r | |
| 327 | mUnitTestHostBaseLibCr[0] = Cr0;\r | |
| 328 | return Cr0;\r | |
| 329 | }\r | |
| 330 | \r | |
| 331 | /**\r | |
| 332 | Writes a value to Control Register 2 (CR2).\r | |
| 333 | \r | |
| 334 | Writes and returns a new value to CR2. This function is only available on\r | |
| 335 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 336 | \r | |
| 337 | @param Cr2 The value to write to CR2.\r | |
| 338 | \r | |
| 339 | @return The value written to CR2.\r | |
| 340 | \r | |
| 341 | **/\r | |
| 342 | UINTN\r | |
| 343 | EFIAPI\r | |
| 344 | UnitTestHostBaseLibAsmWriteCr2 (\r | |
| 345 | UINTN Cr2\r | |
| 346 | )\r | |
| 347 | {\r | |
| 348 | mUnitTestHostBaseLibCr[2] = Cr2;\r | |
| 349 | return Cr2;\r | |
| 350 | }\r | |
| 351 | \r | |
| 352 | /**\r | |
| 353 | Writes a value to Control Register 3 (CR3).\r | |
| 354 | \r | |
| 355 | Writes and returns a new value to CR3. This function is only available on\r | |
| 356 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 357 | \r | |
| 358 | @param Cr3 The value to write to CR3.\r | |
| 359 | \r | |
| 360 | @return The value written to CR3.\r | |
| 361 | \r | |
| 362 | **/\r | |
| 363 | UINTN\r | |
| 364 | EFIAPI\r | |
| 365 | UnitTestHostBaseLibAsmWriteCr3 (\r | |
| 366 | UINTN Cr3\r | |
| 367 | )\r | |
| 368 | {\r | |
| 369 | mUnitTestHostBaseLibCr[3] = Cr3;\r | |
| 370 | return Cr3;\r | |
| 371 | }\r | |
| 372 | \r | |
| 373 | /**\r | |
| 374 | Writes a value to Control Register 4 (CR4).\r | |
| 375 | \r | |
| 376 | Writes and returns a new value to CR4. This function is only available on\r | |
| 377 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 378 | \r | |
| 379 | @param Cr4 The value to write to CR4.\r | |
| 380 | \r | |
| 381 | @return The value written to CR4.\r | |
| 382 | \r | |
| 383 | **/\r | |
| 384 | UINTN\r | |
| 385 | EFIAPI\r | |
| 386 | UnitTestHostBaseLibAsmWriteCr4 (\r | |
| 387 | UINTN Cr4\r | |
| 388 | )\r | |
| 389 | {\r | |
| 390 | mUnitTestHostBaseLibCr[4] = Cr4;\r | |
| 391 | return Cr4;\r | |
| 392 | }\r | |
| 393 | \r | |
| 394 | /**\r | |
| 395 | Reads the current value of Debug Register 0 (DR0).\r | |
| 396 | \r | |
| 397 | Reads and returns the current value of DR0. This function is only available\r | |
| 398 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 399 | x64.\r | |
| 400 | \r | |
| 401 | @return The value of Debug Register 0 (DR0).\r | |
| 402 | \r | |
| 403 | **/\r | |
| 404 | UINTN\r | |
| 405 | EFIAPI\r | |
| 406 | UnitTestHostBaseLibAsmReadDr0 (\r | |
| 407 | VOID\r | |
| 408 | )\r | |
| 409 | {\r | |
| 410 | return mUnitTestHostBaseLibDr[0];\r | |
| 411 | }\r | |
| 412 | \r | |
| 413 | /**\r | |
| 414 | Reads the current value of Debug Register 1 (DR1).\r | |
| 415 | \r | |
| 416 | Reads and returns the current value of DR1. This function is only available\r | |
| 417 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 418 | x64.\r | |
| 419 | \r | |
| 420 | @return The value of Debug Register 1 (DR1).\r | |
| 421 | \r | |
| 422 | **/\r | |
| 423 | UINTN\r | |
| 424 | EFIAPI\r | |
| 425 | UnitTestHostBaseLibAsmReadDr1 (\r | |
| 426 | VOID\r | |
| 427 | )\r | |
| 428 | {\r | |
| 429 | return mUnitTestHostBaseLibDr[1];\r | |
| 430 | }\r | |
| 431 | \r | |
| 432 | /**\r | |
| 433 | Reads the current value of Debug Register 2 (DR2).\r | |
| 434 | \r | |
| 435 | Reads and returns the current value of DR2. This function is only available\r | |
| 436 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 437 | x64.\r | |
| 438 | \r | |
| 439 | @return The value of Debug Register 2 (DR2).\r | |
| 440 | \r | |
| 441 | **/\r | |
| 442 | UINTN\r | |
| 443 | EFIAPI\r | |
| 444 | UnitTestHostBaseLibAsmReadDr2 (\r | |
| 445 | VOID\r | |
| 446 | )\r | |
| 447 | {\r | |
| 448 | return mUnitTestHostBaseLibDr[2];\r | |
| 449 | }\r | |
| 450 | \r | |
| 451 | /**\r | |
| 452 | Reads the current value of Debug Register 3 (DR3).\r | |
| 453 | \r | |
| 454 | Reads and returns the current value of DR3. This function is only available\r | |
| 455 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 456 | x64.\r | |
| 457 | \r | |
| 458 | @return The value of Debug Register 3 (DR3).\r | |
| 459 | \r | |
| 460 | **/\r | |
| 461 | UINTN\r | |
| 462 | EFIAPI\r | |
| 463 | UnitTestHostBaseLibAsmReadDr3 (\r | |
| 464 | VOID\r | |
| 465 | )\r | |
| 466 | {\r | |
| 467 | return mUnitTestHostBaseLibDr[3];\r | |
| 468 | }\r | |
| 469 | \r | |
| 470 | /**\r | |
| 471 | Reads the current value of Debug Register 4 (DR4).\r | |
| 472 | \r | |
| 473 | Reads and returns the current value of DR4. This function is only available\r | |
| 474 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 475 | x64.\r | |
| 476 | \r | |
| 477 | @return The value of Debug Register 4 (DR4).\r | |
| 478 | \r | |
| 479 | **/\r | |
| 480 | UINTN\r | |
| 481 | EFIAPI\r | |
| 482 | UnitTestHostBaseLibAsmReadDr4 (\r | |
| 483 | VOID\r | |
| 484 | )\r | |
| 485 | {\r | |
| 486 | return mUnitTestHostBaseLibDr[4];\r | |
| 487 | }\r | |
| 488 | \r | |
| 489 | /**\r | |
| 490 | Reads the current value of Debug Register 5 (DR5).\r | |
| 491 | \r | |
| 492 | Reads and returns the current value of DR5. This function is only available\r | |
| 493 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 494 | x64.\r | |
| 495 | \r | |
| 496 | @return The value of Debug Register 5 (DR5).\r | |
| 497 | \r | |
| 498 | **/\r | |
| 499 | UINTN\r | |
| 500 | EFIAPI\r | |
| 501 | UnitTestHostBaseLibAsmReadDr5 (\r | |
| 502 | VOID\r | |
| 503 | )\r | |
| 504 | {\r | |
| 505 | return mUnitTestHostBaseLibDr[5];\r | |
| 506 | }\r | |
| 507 | \r | |
| 508 | /**\r | |
| 509 | Reads the current value of Debug Register 6 (DR6).\r | |
| 510 | \r | |
| 511 | Reads and returns the current value of DR6. This function is only available\r | |
| 512 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 513 | x64.\r | |
| 514 | \r | |
| 515 | @return The value of Debug Register 6 (DR6).\r | |
| 516 | \r | |
| 517 | **/\r | |
| 518 | UINTN\r | |
| 519 | EFIAPI\r | |
| 520 | UnitTestHostBaseLibAsmReadDr6 (\r | |
| 521 | VOID\r | |
| 522 | )\r | |
| 523 | {\r | |
| 524 | return mUnitTestHostBaseLibDr[6];\r | |
| 525 | }\r | |
| 526 | \r | |
| 527 | /**\r | |
| 528 | Reads the current value of Debug Register 7 (DR7).\r | |
| 529 | \r | |
| 530 | Reads and returns the current value of DR7. This function is only available\r | |
| 531 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 532 | x64.\r | |
| 533 | \r | |
| 534 | @return The value of Debug Register 7 (DR7).\r | |
| 535 | \r | |
| 536 | **/\r | |
| 537 | UINTN\r | |
| 538 | EFIAPI\r | |
| 539 | UnitTestHostBaseLibAsmReadDr7 (\r | |
| 540 | VOID\r | |
| 541 | )\r | |
| 542 | {\r | |
| 543 | return mUnitTestHostBaseLibDr[7];\r | |
| 544 | }\r | |
| 545 | \r | |
| 546 | /**\r | |
| 547 | Writes a value to Debug Register 0 (DR0).\r | |
| 548 | \r | |
| 549 | Writes and returns a new value to DR0. This function is only available on\r | |
| 550 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 551 | \r | |
| 552 | @param Dr0 The value to write to Dr0.\r | |
| 553 | \r | |
| 554 | @return The value written to Debug Register 0 (DR0).\r | |
| 555 | \r | |
| 556 | **/\r | |
| 557 | UINTN\r | |
| 558 | EFIAPI\r | |
| 559 | UnitTestHostBaseLibAsmWriteDr0 (\r | |
| 560 | UINTN Dr0\r | |
| 561 | )\r | |
| 562 | {\r | |
| 563 | mUnitTestHostBaseLibDr[0] = Dr0;\r | |
| 564 | return Dr0;\r | |
| 565 | }\r | |
| 566 | \r | |
| 567 | /**\r | |
| 568 | Writes a value to Debug Register 1 (DR1).\r | |
| 569 | \r | |
| 570 | Writes and returns a new value to DR1. This function is only available on\r | |
| 571 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 572 | \r | |
| 573 | @param Dr1 The value to write to Dr1.\r | |
| 574 | \r | |
| 575 | @return The value written to Debug Register 1 (DR1).\r | |
| 576 | \r | |
| 577 | **/\r | |
| 578 | UINTN\r | |
| 579 | EFIAPI\r | |
| 580 | UnitTestHostBaseLibAsmWriteDr1 (\r | |
| 581 | UINTN Dr1\r | |
| 582 | )\r | |
| 583 | {\r | |
| 584 | mUnitTestHostBaseLibDr[1] = Dr1;\r | |
| 585 | return Dr1;\r | |
| 586 | }\r | |
| 587 | \r | |
| 588 | /**\r | |
| 589 | Writes a value to Debug Register 2 (DR2).\r | |
| 590 | \r | |
| 591 | Writes and returns a new value to DR2. This function is only available on\r | |
| 592 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 593 | \r | |
| 594 | @param Dr2 The value to write to Dr2.\r | |
| 595 | \r | |
| 596 | @return The value written to Debug Register 2 (DR2).\r | |
| 597 | \r | |
| 598 | **/\r | |
| 599 | UINTN\r | |
| 600 | EFIAPI\r | |
| 601 | UnitTestHostBaseLibAsmWriteDr2 (\r | |
| 602 | UINTN Dr2\r | |
| 603 | )\r | |
| 604 | {\r | |
| 605 | mUnitTestHostBaseLibDr[2] = Dr2;\r | |
| 606 | return Dr2;\r | |
| 607 | }\r | |
| 608 | \r | |
| 609 | /**\r | |
| 610 | Writes a value to Debug Register 3 (DR3).\r | |
| 611 | \r | |
| 612 | Writes and returns a new value to DR3. This function is only available on\r | |
| 613 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 614 | \r | |
| 615 | @param Dr3 The value to write to Dr3.\r | |
| 616 | \r | |
| 617 | @return The value written to Debug Register 3 (DR3).\r | |
| 618 | \r | |
| 619 | **/\r | |
| 620 | UINTN\r | |
| 621 | EFIAPI\r | |
| 622 | UnitTestHostBaseLibAsmWriteDr3 (\r | |
| 623 | UINTN Dr3\r | |
| 624 | )\r | |
| 625 | {\r | |
| 626 | mUnitTestHostBaseLibDr[3] = Dr3;\r | |
| 627 | return Dr3;\r | |
| 628 | }\r | |
| 629 | \r | |
| 630 | /**\r | |
| 631 | Writes a value to Debug Register 4 (DR4).\r | |
| 632 | \r | |
| 633 | Writes and returns a new value to DR4. This function is only available on\r | |
| 634 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 635 | \r | |
| 636 | @param Dr4 The value to write to Dr4.\r | |
| 637 | \r | |
| 638 | @return The value written to Debug Register 4 (DR4).\r | |
| 639 | \r | |
| 640 | **/\r | |
| 641 | UINTN\r | |
| 642 | EFIAPI\r | |
| 643 | UnitTestHostBaseLibAsmWriteDr4 (\r | |
| 644 | UINTN Dr4\r | |
| 645 | )\r | |
| 646 | {\r | |
| 647 | mUnitTestHostBaseLibDr[4] = Dr4;\r | |
| 648 | return Dr4;\r | |
| 649 | }\r | |
| 650 | \r | |
| 651 | /**\r | |
| 652 | Writes a value to Debug Register 5 (DR5).\r | |
| 653 | \r | |
| 654 | Writes and returns a new value to DR5. This function is only available on\r | |
| 655 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 656 | \r | |
| 657 | @param Dr5 The value to write to Dr5.\r | |
| 658 | \r | |
| 659 | @return The value written to Debug Register 5 (DR5).\r | |
| 660 | \r | |
| 661 | **/\r | |
| 662 | UINTN\r | |
| 663 | EFIAPI\r | |
| 664 | UnitTestHostBaseLibAsmWriteDr5 (\r | |
| 665 | UINTN Dr5\r | |
| 666 | )\r | |
| 667 | {\r | |
| 668 | mUnitTestHostBaseLibDr[5] = Dr5;\r | |
| 669 | return Dr5;\r | |
| 670 | }\r | |
| 671 | \r | |
| 672 | /**\r | |
| 673 | Writes a value to Debug Register 6 (DR6).\r | |
| 674 | \r | |
| 675 | Writes and returns a new value to DR6. This function is only available on\r | |
| 676 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 677 | \r | |
| 678 | @param Dr6 The value to write to Dr6.\r | |
| 679 | \r | |
| 680 | @return The value written to Debug Register 6 (DR6).\r | |
| 681 | \r | |
| 682 | **/\r | |
| 683 | UINTN\r | |
| 684 | EFIAPI\r | |
| 685 | UnitTestHostBaseLibAsmWriteDr6 (\r | |
| 686 | UINTN Dr6\r | |
| 687 | )\r | |
| 688 | {\r | |
| 689 | mUnitTestHostBaseLibDr[6] = Dr6;\r | |
| 690 | return Dr6;\r | |
| 691 | }\r | |
| 692 | \r | |
| 693 | /**\r | |
| 694 | Writes a value to Debug Register 7 (DR7).\r | |
| 695 | \r | |
| 696 | Writes and returns a new value to DR7. This function is only available on\r | |
| 697 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 698 | \r | |
| 699 | @param Dr7 The value to write to Dr7.\r | |
| 700 | \r | |
| 701 | @return The value written to Debug Register 7 (DR7).\r | |
| 702 | \r | |
| 703 | **/\r | |
| 704 | UINTN\r | |
| 705 | EFIAPI\r | |
| 706 | UnitTestHostBaseLibAsmWriteDr7 (\r | |
| 707 | UINTN Dr7\r | |
| 708 | )\r | |
| 709 | {\r | |
| 710 | mUnitTestHostBaseLibDr[7] = Dr7;\r | |
| 711 | return Dr7;\r | |
| 712 | }\r | |
| 713 | \r | |
| 714 | /**\r | |
| 715 | Reads the current value of Code Segment Register (CS).\r | |
| 716 | \r | |
| 717 | Reads and returns the current value of CS. This function is only available on\r | |
| 718 | IA-32 and x64.\r | |
| 719 | \r | |
| 720 | @return The current value of CS.\r | |
| 721 | \r | |
| 722 | **/\r | |
| 723 | UINT16\r | |
| 724 | EFIAPI\r | |
| 725 | UnitTestHostBaseLibAsmReadCs (\r | |
| 726 | VOID\r | |
| 727 | )\r | |
| 728 | {\r | |
| 729 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_CS];\r | |
| 730 | }\r | |
| 731 | \r | |
| 732 | /**\r | |
| 733 | Reads the current value of Data Segment Register (DS).\r | |
| 734 | \r | |
| 735 | Reads and returns the current value of DS. This function is only available on\r | |
| 736 | IA-32 and x64.\r | |
| 737 | \r | |
| 738 | @return The current value of DS.\r | |
| 739 | \r | |
| 740 | **/\r | |
| 741 | UINT16\r | |
| 742 | EFIAPI\r | |
| 743 | UnitTestHostBaseLibAsmReadDs (\r | |
| 744 | VOID\r | |
| 745 | )\r | |
| 746 | {\r | |
| 747 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_DS];\r | |
| 748 | }\r | |
| 749 | \r | |
| 750 | /**\r | |
| 751 | Reads the current value of Extra Segment Register (ES).\r | |
| 752 | \r | |
| 753 | Reads and returns the current value of ES. This function is only available on\r | |
| 754 | IA-32 and x64.\r | |
| 755 | \r | |
| 756 | @return The current value of ES.\r | |
| 757 | \r | |
| 758 | **/\r | |
| 759 | UINT16\r | |
| 760 | EFIAPI\r | |
| 761 | UnitTestHostBaseLibAsmReadEs (\r | |
| 762 | VOID\r | |
| 763 | )\r | |
| 764 | {\r | |
| 765 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_ES];\r | |
| 766 | }\r | |
| 767 | \r | |
| 768 | /**\r | |
| 769 | Reads the current value of FS Data Segment Register (FS).\r | |
| 770 | \r | |
| 771 | Reads and returns the current value of FS. This function is only available on\r | |
| 772 | IA-32 and x64.\r | |
| 773 | \r | |
| 774 | @return The current value of FS.\r | |
| 775 | \r | |
| 776 | **/\r | |
| 777 | UINT16\r | |
| 778 | EFIAPI\r | |
| 779 | UnitTestHostBaseLibAsmReadFs (\r | |
| 780 | VOID\r | |
| 781 | )\r | |
| 782 | {\r | |
| 783 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_FS];\r | |
| 784 | }\r | |
| 785 | \r | |
| 786 | /**\r | |
| 787 | Reads the current value of GS Data Segment Register (GS).\r | |
| 788 | \r | |
| 789 | Reads and returns the current value of GS. This function is only available on\r | |
| 790 | IA-32 and x64.\r | |
| 791 | \r | |
| 792 | @return The current value of GS.\r | |
| 793 | \r | |
| 794 | **/\r | |
| 795 | UINT16\r | |
| 796 | EFIAPI\r | |
| 797 | UnitTestHostBaseLibAsmReadGs (\r | |
| 798 | VOID\r | |
| 799 | )\r | |
| 800 | {\r | |
| 801 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_GS];\r | |
| 802 | }\r | |
| 803 | \r | |
| 804 | /**\r | |
| 805 | Reads the current value of Stack Segment Register (SS).\r | |
| 806 | \r | |
| 807 | Reads and returns the current value of SS. This function is only available on\r | |
| 808 | IA-32 and x64.\r | |
| 809 | \r | |
| 810 | @return The current value of SS.\r | |
| 811 | \r | |
| 812 | **/\r | |
| 813 | UINT16\r | |
| 814 | EFIAPI\r | |
| 815 | UnitTestHostBaseLibAsmReadSs (\r | |
| 816 | VOID\r | |
| 817 | )\r | |
| 818 | {\r | |
| 819 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_SS];\r | |
| 820 | }\r | |
| 821 | \r | |
| 822 | /**\r | |
| 823 | Reads the current value of Task Register (TR).\r | |
| 824 | \r | |
| 825 | Reads and returns the current value of TR. This function is only available on\r | |
| 826 | IA-32 and x64.\r | |
| 827 | \r | |
| 828 | @return The current value of TR.\r | |
| 829 | \r | |
| 830 | **/\r | |
| 831 | UINT16\r | |
| 832 | EFIAPI\r | |
| 833 | UnitTestHostBaseLibAsmReadTr (\r | |
| 834 | VOID\r | |
| 835 | )\r | |
| 836 | {\r | |
| 837 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR];\r | |
| 838 | }\r | |
| 839 | \r | |
| 840 | /**\r | |
| 841 | Reads the current Global Descriptor Table Register(GDTR) descriptor.\r | |
| 842 | \r | |
| 843 | Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r | |
| 844 | function is only available on IA-32 and x64.\r | |
| 845 | \r | |
| 846 | If Gdtr is NULL, then ASSERT().\r | |
| 847 | \r | |
| 848 | @param Gdtr The pointer to a GDTR descriptor.\r | |
| 849 | \r | |
| 850 | **/\r | |
| 851 | VOID\r | |
| 852 | EFIAPI\r | |
| 853 | UnitTestHostBaseLibAsmReadGdtr (\r | |
| 854 | OUT IA32_DESCRIPTOR *Gdtr\r | |
| 855 | )\r | |
| 856 | {\r | |
| 857 | Gdtr = &mUnitTestHostBaseLibGdtr;\r | |
| 858 | }\r | |
| 859 | \r | |
| 860 | /**\r | |
| 861 | Writes the current Global Descriptor Table Register (GDTR) descriptor.\r | |
| 862 | \r | |
| 863 | Writes and the current GDTR descriptor specified by Gdtr. This function is\r | |
| 864 | only available on IA-32 and x64.\r | |
| 865 | \r | |
| 866 | If Gdtr is NULL, then ASSERT().\r | |
| 867 | \r | |
| 868 | @param Gdtr The pointer to a GDTR descriptor.\r | |
| 869 | \r | |
| 870 | **/\r | |
| 871 | VOID\r | |
| 872 | EFIAPI\r | |
| 873 | UnitTestHostBaseLibAsmWriteGdtr (\r | |
| 874 | IN CONST IA32_DESCRIPTOR *Gdtr\r | |
| 875 | )\r | |
| 876 | {\r | |
| 877 | CopyMem (&mUnitTestHostBaseLibGdtr, Gdtr, sizeof (IA32_DESCRIPTOR));\r | |
| 878 | }\r | |
| 879 | \r | |
| 880 | /**\r | |
| 881 | Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
| 882 | \r | |
| 883 | Reads and returns the current IDTR descriptor and returns it in Idtr. This\r | |
| 884 | function is only available on IA-32 and x64.\r | |
| 885 | \r | |
| 886 | If Idtr is NULL, then ASSERT().\r | |
| 887 | \r | |
| 888 | @param Idtr The pointer to a IDTR descriptor.\r | |
| 889 | \r | |
| 890 | **/\r | |
| 891 | VOID\r | |
| 892 | EFIAPI\r | |
| 893 | UnitTestHostBaseLibAsmReadIdtr (\r | |
| 894 | OUT IA32_DESCRIPTOR *Idtr\r | |
| 895 | )\r | |
| 896 | {\r | |
| 897 | Idtr = &mUnitTestHostBaseLibIdtr;\r | |
| 898 | }\r | |
| 899 | \r | |
| 900 | /**\r | |
| 901 | Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
| 902 | \r | |
| 903 | Writes the current IDTR descriptor and returns it in Idtr. This function is\r | |
| 904 | only available on IA-32 and x64.\r | |
| 905 | \r | |
| 906 | If Idtr is NULL, then ASSERT().\r | |
| 907 | \r | |
| 908 | @param Idtr The pointer to a IDTR descriptor.\r | |
| 909 | \r | |
| 910 | **/\r | |
| 911 | VOID\r | |
| 912 | EFIAPI\r | |
| 913 | UnitTestHostBaseLibAsmWriteIdtr (\r | |
| 914 | IN CONST IA32_DESCRIPTOR *Idtr\r | |
| 915 | )\r | |
| 916 | {\r | |
| 917 | CopyMem (&mUnitTestHostBaseLibIdtr, Idtr, sizeof (IA32_DESCRIPTOR));\r | |
| 918 | }\r | |
| 919 | \r | |
| 920 | /**\r | |
| 921 | Reads the current Local Descriptor Table Register(LDTR) selector.\r | |
| 922 | \r | |
| 923 | Reads and returns the current 16-bit LDTR descriptor value. This function is\r | |
| 924 | only available on IA-32 and x64.\r | |
| 925 | \r | |
| 926 | @return The current selector of LDT.\r | |
| 927 | \r | |
| 928 | **/\r | |
| 929 | UINT16\r | |
| 930 | EFIAPI\r | |
| 931 | UnitTestHostBaseLibAsmReadLdtr (\r | |
| 932 | VOID\r | |
| 933 | )\r | |
| 934 | {\r | |
| 935 | return mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR];\r | |
| 936 | }\r | |
| 937 | \r | |
| 938 | /**\r | |
| 939 | Writes the current Local Descriptor Table Register (LDTR) selector.\r | |
| 940 | \r | |
| 941 | Writes and the current LDTR descriptor specified by Ldtr. This function is\r | |
| 942 | only available on IA-32 and x64.\r | |
| 943 | \r | |
| 944 | @param Ldtr 16-bit LDTR selector value.\r | |
| 945 | \r | |
| 946 | **/\r | |
| 947 | VOID\r | |
| 948 | EFIAPI\r | |
| 949 | UnitTestHostBaseLibAsmWriteLdtr (\r | |
| 950 | IN UINT16 Ldtr\r | |
| 951 | )\r | |
| 952 | {\r | |
| 953 | mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_LDTR] = Ldtr;\r | |
| 954 | }\r | |
| 955 | \r | |
| 956 | /**\r | |
| 957 | Reads the current value of a Performance Counter (PMC).\r | |
| 958 | \r | |
| 959 | Reads and returns the current value of performance counter specified by\r | |
| 960 | Index. This function is only available on IA-32 and x64.\r | |
| 961 | \r | |
| 962 | @param Index The 32-bit Performance Counter index to read.\r | |
| 963 | \r | |
| 964 | @return The value of the PMC specified by Index.\r | |
| 965 | \r | |
| 966 | **/\r | |
| 967 | UINT64\r | |
| 968 | EFIAPI\r | |
| 969 | UnitTestHostBaseLibAsmReadPmc (\r | |
| 970 | IN UINT32 Index\r | |
| 971 | )\r | |
| 972 | {\r | |
| 973 | return 0;\r | |
| 974 | }\r | |
| 975 | \r | |
| 976 | /**\r | |
| 977 | Sets up a monitor buffer that is used by AsmMwait().\r | |
| 978 | \r | |
| 979 | Executes a MONITOR instruction with the register state specified by Eax, Ecx\r | |
| 980 | and Edx. Returns Eax. This function is only available on IA-32 and x64.\r | |
| 981 | \r | |
| 982 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
| 983 | instruction.\r | |
| 984 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
| 985 | instruction.\r | |
| 986 | @param Edx The value to load into EDX or RDX before executing the MONITOR\r | |
| 987 | instruction.\r | |
| 988 | \r | |
| 989 | @return Eax\r | |
| 990 | \r | |
| 991 | **/\r | |
| 992 | UINTN\r | |
| 993 | EFIAPI\r | |
| 994 | UnitTestHostBaseLibAsmMonitor (\r | |
| 995 | IN UINTN Eax,\r | |
| 996 | IN UINTN Ecx,\r | |
| 997 | IN UINTN Edx\r | |
| 998 | )\r | |
| 999 | {\r | |
| 1000 | return Eax;\r | |
| 1001 | }\r | |
| 1002 | \r | |
| 1003 | /**\r | |
| 1004 | Executes an MWAIT instruction.\r | |
| 1005 | \r | |
| 1006 | Executes an MWAIT instruction with the register state specified by Eax and\r | |
| 1007 | Ecx. Returns Eax. This function is only available on IA-32 and x64.\r | |
| 1008 | \r | |
| 1009 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
| 1010 | instruction.\r | |
| 1011 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
| 1012 | instruction.\r | |
| 1013 | \r | |
| 1014 | @return Eax\r | |
| 1015 | \r | |
| 1016 | **/\r | |
| 1017 | UINTN\r | |
| 1018 | EFIAPI\r | |
| 1019 | UnitTestHostBaseLibAsmMwait (\r | |
| 1020 | IN UINTN Eax,\r | |
| 1021 | IN UINTN Ecx\r | |
| 1022 | )\r | |
| 1023 | {\r | |
| 1024 | return Eax;\r | |
| 1025 | }\r | |
| 1026 | \r | |
| 1027 | /**\r | |
| 1028 | Executes a WBINVD instruction.\r | |
| 1029 | \r | |
| 1030 | Executes a WBINVD instruction. This function is only available on IA-32 and\r | |
| 1031 | x64.\r | |
| 1032 | \r | |
| 1033 | **/\r | |
| 1034 | VOID\r | |
| 1035 | EFIAPI\r | |
| 1036 | UnitTestHostBaseLibAsmWbinvd (\r | |
| 1037 | VOID\r | |
| 1038 | )\r | |
| 1039 | {\r | |
| 1040 | }\r | |
| 1041 | \r | |
| 1042 | /**\r | |
| 1043 | Executes a INVD instruction.\r | |
| 1044 | \r | |
| 1045 | Executes a INVD instruction. This function is only available on IA-32 and\r | |
| 1046 | x64.\r | |
| 1047 | \r | |
| 1048 | **/\r | |
| 1049 | VOID\r | |
| 1050 | EFIAPI\r | |
| 1051 | UnitTestHostBaseLibAsmInvd (\r | |
| 1052 | VOID\r | |
| 1053 | )\r | |
| 1054 | {\r | |
| 1055 | }\r | |
| 1056 | \r | |
| 1057 | /**\r | |
| 1058 | Flushes a cache line from all the instruction and data caches within the\r | |
| 1059 | coherency domain of the CPU.\r | |
| 1060 | \r | |
| 1061 | Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r | |
| 1062 | This function is only available on IA-32 and x64.\r | |
| 1063 | \r | |
| 1064 | @param LinearAddress The address of the cache line to flush. If the CPU is\r | |
| 1065 | in a physical addressing mode, then LinearAddress is a\r | |
| 1066 | physical address. If the CPU is in a virtual\r | |
| 1067 | addressing mode, then LinearAddress is a virtual\r | |
| 1068 | address.\r | |
| 1069 | \r | |
| 1070 | @return LinearAddress.\r | |
| 1071 | **/\r | |
| 1072 | VOID *\r | |
| 1073 | EFIAPI\r | |
| 1074 | UnitTestHostBaseLibAsmFlushCacheLine (\r | |
| 1075 | IN VOID *LinearAddress\r | |
| 1076 | )\r | |
| 1077 | {\r | |
| 1078 | return LinearAddress;\r | |
| 1079 | }\r | |
| 1080 | \r | |
| 1081 | /**\r | |
| 1082 | Enables the 32-bit paging mode on the CPU.\r | |
| 1083 | \r | |
| 1084 | Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
| 1085 | must be properly initialized prior to calling this service. This function\r | |
| 1086 | assumes the current execution mode is 32-bit protected mode. This function is\r | |
| 1087 | only available on IA-32. After the 32-bit paging mode is enabled, control is\r | |
| 1088 | transferred to the function specified by EntryPoint using the new stack\r | |
| 1089 | specified by NewStack and passing in the parameters specified by Context1 and\r | |
| 1090 | Context2. Context1 and Context2 are optional and may be NULL. The function\r | |
| 1091 | EntryPoint must never return.\r | |
| 1092 | \r | |
| 1093 | If the current execution mode is not 32-bit protected mode, then ASSERT().\r | |
| 1094 | If EntryPoint is NULL, then ASSERT().\r | |
| 1095 | If NewStack is NULL, then ASSERT().\r | |
| 1096 | \r | |
| 1097 | There are a number of constraints that must be followed before calling this\r | |
| 1098 | function:\r | |
| 1099 | 1) Interrupts must be disabled.\r | |
| 1100 | 2) The caller must be in 32-bit protected mode with flat descriptors. This\r | |
| 1101 | means all descriptors must have a base of 0 and a limit of 4GB.\r | |
| 1102 | 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r | |
| 1103 | descriptors.\r | |
| 1104 | 4) CR3 must point to valid page tables that will be used once the transition\r | |
| 1105 | is complete, and those page tables must guarantee that the pages for this\r | |
| 1106 | function and the stack are identity mapped.\r | |
| 1107 | \r | |
| 1108 | @param EntryPoint A pointer to function to call with the new stack after\r | |
| 1109 | paging is enabled.\r | |
| 1110 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
| 1111 | function as the first parameter after paging is enabled.\r | |
| 1112 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
| 1113 | function as the second parameter after paging is enabled.\r | |
| 1114 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
| 1115 | function after paging is enabled.\r | |
| 1116 | \r | |
| 1117 | **/\r | |
| 1118 | VOID\r | |
| 1119 | EFIAPI\r | |
| 1120 | UnitTestHostBaseLibAsmEnablePaging32 (\r | |
| 1121 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
| d0e2f823 MK |
1122 | IN VOID *Context1 OPTIONAL,\r |
| 1123 | IN VOID *Context2 OPTIONAL,\r | |
| 540fd45f MK |
1124 | IN VOID *NewStack\r |
| 1125 | )\r | |
| 1126 | {\r | |
| 1127 | EntryPoint (Context1, Context2);\r | |
| 1128 | }\r | |
| 1129 | \r | |
| 1130 | /**\r | |
| 1131 | Disables the 32-bit paging mode on the CPU.\r | |
| 1132 | \r | |
| 1133 | Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r | |
| 1134 | mode. This function assumes the current execution mode is 32-paged protected\r | |
| 1135 | mode. This function is only available on IA-32. After the 32-bit paging mode\r | |
| 1136 | is disabled, control is transferred to the function specified by EntryPoint\r | |
| 1137 | using the new stack specified by NewStack and passing in the parameters\r | |
| 1138 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
| 1139 | may be NULL. The function EntryPoint must never return.\r | |
| 1140 | \r | |
| 1141 | If the current execution mode is not 32-bit paged mode, then ASSERT().\r | |
| 1142 | If EntryPoint is NULL, then ASSERT().\r | |
| 1143 | If NewStack is NULL, then ASSERT().\r | |
| 1144 | \r | |
| 1145 | There are a number of constraints that must be followed before calling this\r | |
| 1146 | function:\r | |
| 1147 | 1) Interrupts must be disabled.\r | |
| 1148 | 2) The caller must be in 32-bit paged mode.\r | |
| 1149 | 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r | |
| 1150 | 4) CR3 must point to valid page tables that guarantee that the pages for\r | |
| 1151 | this function and the stack are identity mapped.\r | |
| 1152 | \r | |
| 1153 | @param EntryPoint A pointer to function to call with the new stack after\r | |
| 1154 | paging is disabled.\r | |
| 1155 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
| 1156 | function as the first parameter after paging is disabled.\r | |
| 1157 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
| 1158 | function as the second parameter after paging is\r | |
| 1159 | disabled.\r | |
| 1160 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
| 1161 | function after paging is disabled.\r | |
| 1162 | \r | |
| 1163 | **/\r | |
| 1164 | VOID\r | |
| 1165 | EFIAPI\r | |
| 1166 | UnitTestHostBaseLibAsmDisablePaging32 (\r | |
| 1167 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
| d0e2f823 MK |
1168 | IN VOID *Context1 OPTIONAL,\r |
| 1169 | IN VOID *Context2 OPTIONAL,\r | |
| 540fd45f MK |
1170 | IN VOID *NewStack\r |
| 1171 | )\r | |
| 1172 | {\r | |
| 1173 | EntryPoint (Context1, Context2);\r | |
| 1174 | }\r | |
| 1175 | \r | |
| 1176 | /**\r | |
| 1177 | Enables the 64-bit paging mode on the CPU.\r | |
| 1178 | \r | |
| 1179 | Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
| 1180 | must be properly initialized prior to calling this service. This function\r | |
| 1181 | assumes the current execution mode is 32-bit protected mode with flat\r | |
| 1182 | descriptors. This function is only available on IA-32. After the 64-bit\r | |
| 1183 | paging mode is enabled, control is transferred to the function specified by\r | |
| 1184 | EntryPoint using the new stack specified by NewStack and passing in the\r | |
| 1185 | parameters specified by Context1 and Context2. Context1 and Context2 are\r | |
| 1186 | optional and may be 0. The function EntryPoint must never return.\r | |
| 1187 | \r | |
| 1188 | If the current execution mode is not 32-bit protected mode with flat\r | |
| 1189 | descriptors, then ASSERT().\r | |
| 1190 | If EntryPoint is 0, then ASSERT().\r | |
| 1191 | If NewStack is 0, then ASSERT().\r | |
| 1192 | \r | |
| 1193 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
| 1194 | is called. The descriptor in the GDT that this selector\r | |
| 1195 | references must be setup for long mode.\r | |
| 1196 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
| 1197 | the new stack after paging is enabled.\r | |
| 1198 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
| 1199 | the EntryPoint function as the first parameter after\r | |
| 1200 | paging is enabled.\r | |
| 1201 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
| 1202 | the EntryPoint function as the second parameter after\r | |
| 1203 | paging is enabled.\r | |
| 1204 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
| 1205 | the EntryPoint function after paging is enabled.\r | |
| 1206 | \r | |
| 1207 | **/\r | |
| 1208 | VOID\r | |
| 1209 | EFIAPI\r | |
| 1210 | UnitTestHostBaseLibAsmEnablePaging64 (\r | |
| 1211 | IN UINT16 Cs,\r | |
| 1212 | IN UINT64 EntryPoint,\r | |
| d0e2f823 MK |
1213 | IN UINT64 Context1 OPTIONAL,\r |
| 1214 | IN UINT64 Context2 OPTIONAL,\r | |
| 540fd45f MK |
1215 | IN UINT64 NewStack\r |
| 1216 | )\r | |
| 1217 | {\r | |
| 1218 | SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r | |
| 1219 | \r | |
| 1220 | NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);\r | |
| 1221 | NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);\r | |
| 1222 | }\r | |
| 1223 | \r | |
| 1224 | /**\r | |
| 1225 | Disables the 64-bit paging mode on the CPU.\r | |
| 1226 | \r | |
| 1227 | Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r | |
| 1228 | mode. This function assumes the current execution mode is 64-paging mode.\r | |
| 1229 | This function is only available on x64. After the 64-bit paging mode is\r | |
| 1230 | disabled, control is transferred to the function specified by EntryPoint\r | |
| 1231 | using the new stack specified by NewStack and passing in the parameters\r | |
| 1232 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
| 1233 | may be 0. The function EntryPoint must never return.\r | |
| 1234 | \r | |
| 1235 | If the current execution mode is not 64-bit paged mode, then ASSERT().\r | |
| 1236 | If EntryPoint is 0, then ASSERT().\r | |
| 1237 | If NewStack is 0, then ASSERT().\r | |
| 1238 | \r | |
| 1239 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
| 1240 | is called. The descriptor in the GDT that this selector\r | |
| 1241 | references must be setup for 32-bit protected mode.\r | |
| 1242 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
| 1243 | the new stack after paging is disabled.\r | |
| 1244 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
| 1245 | the EntryPoint function as the first parameter after\r | |
| 1246 | paging is disabled.\r | |
| 1247 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
| 1248 | the EntryPoint function as the second parameter after\r | |
| 1249 | paging is disabled.\r | |
| 1250 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
| 1251 | the EntryPoint function after paging is disabled.\r | |
| 1252 | \r | |
| 1253 | **/\r | |
| 1254 | VOID\r | |
| 1255 | EFIAPI\r | |
| 1256 | UnitTestHostBaseLibAsmDisablePaging64 (\r | |
| 1257 | IN UINT16 Cs,\r | |
| 1258 | IN UINT32 EntryPoint,\r | |
| d0e2f823 MK |
1259 | IN UINT32 Context1 OPTIONAL,\r |
| 1260 | IN UINT32 Context2 OPTIONAL,\r | |
| 540fd45f MK |
1261 | IN UINT32 NewStack\r |
| 1262 | )\r | |
| 1263 | {\r | |
| 1264 | SWITCH_STACK_ENTRY_POINT NewEntryPoint;\r | |
| 1265 | \r | |
| 1266 | NewEntryPoint = (SWITCH_STACK_ENTRY_POINT)(UINTN)(EntryPoint);\r | |
| 1267 | NewEntryPoint ((VOID *)(UINTN)Context1, (VOID *)(UINTN)Context2);\r | |
| 1268 | }\r | |
| 1269 | \r | |
| 1270 | /**\r | |
| 1271 | Retrieves the properties for 16-bit thunk functions.\r | |
| 1272 | \r | |
| 1273 | Computes the size of the buffer and stack below 1MB required to use the\r | |
| 1274 | AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r | |
| 1275 | buffer size is returned in RealModeBufferSize, and the stack size is returned\r | |
| 1276 | in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r | |
| 1277 | then the actual minimum stack size is ExtraStackSize plus the maximum number\r | |
| 1278 | of bytes that need to be passed to the 16-bit real mode code.\r | |
| 1279 | \r | |
| 1280 | If RealModeBufferSize is NULL, then ASSERT().\r | |
| 1281 | If ExtraStackSize is NULL, then ASSERT().\r | |
| 1282 | \r | |
| 1283 | @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r | |
| 1284 | required to use the 16-bit thunk functions.\r | |
| 1285 | @param ExtraStackSize A pointer to the extra size of stack below 1MB\r | |
| 1286 | that the 16-bit thunk functions require for\r | |
| 1287 | temporary storage in the transition to and from\r | |
| 1288 | 16-bit real mode.\r | |
| 1289 | \r | |
| 1290 | **/\r | |
| 1291 | VOID\r | |
| 1292 | EFIAPI\r | |
| 1293 | UnitTestHostBaseLibAsmGetThunk16Properties (\r | |
| 1294 | OUT UINT32 *RealModeBufferSize,\r | |
| 1295 | OUT UINT32 *ExtraStackSize\r | |
| 1296 | )\r | |
| 1297 | {\r | |
| 1298 | *RealModeBufferSize = 0;\r | |
| 1299 | *ExtraStackSize = 0;\r | |
| 1300 | }\r | |
| 1301 | \r | |
| 1302 | /**\r | |
| 1303 | Prepares all structures a code required to use AsmThunk16().\r | |
| 1304 | \r | |
| 1305 | Prepares all structures and code required to use AsmThunk16().\r | |
| 1306 | \r | |
| 1307 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 1308 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
| 1309 | \r | |
| 1310 | If ThunkContext is NULL, then ASSERT().\r | |
| 1311 | \r | |
| 1312 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 1313 | 16-bit real mode code to call.\r | |
| 1314 | \r | |
| 1315 | **/\r | |
| 1316 | VOID\r | |
| 1317 | EFIAPI\r | |
| 1318 | UnitTestHostBaseLibAsmPrepareThunk16 (\r | |
| 1319 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 1320 | )\r | |
| 1321 | {\r | |
| 1322 | }\r | |
| 1323 | \r | |
| 1324 | /**\r | |
| 1325 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
| 1326 | \r | |
| 1327 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
| 1328 | AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r | |
| 1329 | This function must be called with interrupts disabled.\r | |
| 1330 | \r | |
| 1331 | The register state from the RealModeState field of ThunkContext is restored just prior\r | |
| 1332 | to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\r | |
| 1333 | which is used to set the interrupt state when a 16-bit real mode entry point is called.\r | |
| 1334 | Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r | |
| 1335 | The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\r | |
| 1336 | the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\r | |
| 1337 | The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r | |
| 1338 | so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\r | |
| 1339 | and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\r | |
| 1340 | point must exit with a RETF instruction. The register state is captured into RealModeState immediately\r | |
| 1341 | after the RETF instruction is executed.\r | |
| 1342 | \r | |
| 1343 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
| 1344 | or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\r | |
| 1345 | the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\r | |
| 1346 | \r | |
| 1347 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
| 1348 | then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\r | |
| 1349 | This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r | |
| 1350 | \r | |
| 1351 | If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\r | |
| 1352 | is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r | |
| 1353 | \r | |
| 1354 | If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
| 1355 | ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\r | |
| 1356 | disable the A20 mask.\r | |
| 1357 | \r | |
| 1358 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\r | |
| 1359 | ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\r | |
| 1360 | then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
| 1361 | \r | |
| 1362 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\r | |
| 1363 | ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
| 1364 | \r | |
| 1365 | If ThunkContext is NULL, then ASSERT().\r | |
| 1366 | If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r | |
| 1367 | If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
| 1368 | ThunkAttributes, then ASSERT().\r | |
| 1369 | \r | |
| 1370 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 1371 | virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.\r | |
| 1372 | \r | |
| 1373 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 1374 | 16-bit real mode code to call.\r | |
| 1375 | \r | |
| 1376 | **/\r | |
| 1377 | VOID\r | |
| 1378 | EFIAPI\r | |
| 1379 | UnitTestHostBaseLibAsmThunk16 (\r | |
| 1380 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 1381 | )\r | |
| 1382 | {\r | |
| 1383 | }\r | |
| 1384 | \r | |
| 1385 | /**\r | |
| 1386 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
| 1387 | control to a 16-bit real mode entry point, and returns the results.\r | |
| 1388 | \r | |
| 1389 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
| 1390 | control to a 16-bit real mode entry point, and returns the results. If the\r | |
| 1391 | caller only need to perform a single 16-bit real mode thunk, then this\r | |
| 1392 | service should be used. If the caller intends to make more than one 16-bit\r | |
| 1393 | real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r | |
| 1394 | once and AsmThunk16() can be called for each 16-bit real mode thunk.\r | |
| 1395 | \r | |
| 1396 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 1397 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
| 1398 | \r | |
| 1399 | See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r | |
| 1400 | \r | |
| 1401 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 1402 | 16-bit real mode code to call.\r | |
| 1403 | \r | |
| 1404 | **/\r | |
| 1405 | VOID\r | |
| 1406 | EFIAPI\r | |
| 1407 | UnitTestHostBaseLibAsmPrepareAndThunk16 (\r | |
| 1408 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 1409 | )\r | |
| 1410 | {\r | |
| 1411 | }\r | |
| 1412 | \r | |
| 1413 | /**\r | |
| 1414 | Load given selector into TR register.\r | |
| 1415 | \r | |
| 1416 | @param[in] Selector Task segment selector\r | |
| 1417 | **/\r | |
| 1418 | VOID\r | |
| 1419 | EFIAPI\r | |
| 1420 | UnitTestHostBaseLibAsmWriteTr (\r | |
| 1421 | IN UINT16 Selector\r | |
| 1422 | )\r | |
| 1423 | {\r | |
| 1424 | mUnitTestHostBaseLibSegment[UNIT_TEST_HOST_BASE_LIB_SEGMENT_TR] = Selector;\r | |
| 1425 | }\r | |
| 1426 | \r | |
| 1427 | /**\r | |
| 1428 | Performs a serializing operation on all load-from-memory instructions that\r | |
| 1429 | were issued prior the AsmLfence function.\r | |
| 1430 | \r | |
| 1431 | Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r | |
| 1432 | \r | |
| 1433 | **/\r | |
| 1434 | VOID\r | |
| 1435 | EFIAPI\r | |
| 1436 | UnitTestHostBaseLibAsmLfence (\r | |
| 1437 | VOID\r | |
| 1438 | )\r | |
| 1439 | {\r | |
| 1440 | }\r | |
| 1441 | \r | |
| 1442 | /**\r | |
| 1443 | Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r | |
| 1444 | word, dword or qword operand is encoded at the end of the instruction's\r | |
| 1445 | binary representation.\r | |
| 1446 | \r | |
| 1447 | This function should be used to update object code that was compiled with\r | |
| 1448 | NASM from assembly source code. Example:\r | |
| 1449 | \r | |
| 1450 | NASM source code:\r | |
| 1451 | \r | |
| 1452 | mov eax, strict dword 0 ; the imm32 zero operand will be patched\r | |
| 1453 | ASM_PFX(gPatchCr3):\r | |
| 1454 | mov cr3, eax\r | |
| 1455 | \r | |
| 1456 | C source code:\r | |
| 1457 | \r | |
| 1458 | X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r | |
| 1459 | PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r | |
| 1460 | \r | |
| 1461 | @param[out] InstructionEnd Pointer right past the instruction to patch. The\r | |
| 1462 | immediate operand to patch is expected to\r | |
| 1463 | comprise the trailing bytes of the instruction.\r | |
| 1464 | If InstructionEnd is closer to address 0 than\r | |
| 1465 | ValueSize permits, then ASSERT().\r | |
| 1466 | \r | |
| 1467 | @param[in] PatchValue The constant to write to the immediate operand.\r | |
| 1468 | The caller is responsible for ensuring that\r | |
| 1469 | PatchValue can be represented in the byte, word,\r | |
| 1470 | dword or qword operand (as indicated through\r | |
| 1471 | ValueSize); otherwise ASSERT().\r | |
| 1472 | \r | |
| 1473 | @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r | |
| 1474 | 4, or 8. ASSERT() otherwise.\r | |
| 1475 | **/\r | |
| 1476 | VOID\r | |
| 1477 | EFIAPI\r | |
| 1478 | UnitTestHostBaseLibPatchInstructionX86 (\r | |
| 1479 | OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r | |
| 1480 | IN UINT64 PatchValue,\r | |
| 1481 | IN UINTN ValueSize\r | |
| 1482 | )\r | |
| 1483 | {\r | |
| 1484 | }\r | |
| 1485 | \r | |
| 1486 | /**\r | |
| 1487 | Retrieves CPUID information.\r | |
| 1488 | \r | |
| 1489 | Executes the CPUID instruction with EAX set to the value specified by Index.\r | |
| 1490 | This function always returns Index.\r | |
| 1491 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
| 1492 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
| 1493 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
| 1494 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
| 1495 | This function is only available on IA-32 and x64.\r | |
| 1496 | \r | |
| 1497 | @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r | |
| 1498 | instruction.\r | |
| 1499 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
| 1500 | instruction. This is an optional parameter that may be NULL.\r | |
| 1501 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
| 1502 | instruction. This is an optional parameter that may be NULL.\r | |
| 1503 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
| 1504 | instruction. This is an optional parameter that may be NULL.\r | |
| 1505 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
| 1506 | instruction. This is an optional parameter that may be NULL.\r | |
| 1507 | \r | |
| 1508 | @return Index.\r | |
| 1509 | \r | |
| 1510 | **/\r | |
| 1511 | UINT32\r | |
| 1512 | EFIAPI\r | |
| 1513 | AsmCpuid (\r | |
| 1514 | IN UINT32 Index,\r | |
| d0e2f823 MK |
1515 | OUT UINT32 *Eax OPTIONAL,\r |
| 1516 | OUT UINT32 *Ebx OPTIONAL,\r | |
| 1517 | OUT UINT32 *Ecx OPTIONAL,\r | |
| 540fd45f MK |
1518 | OUT UINT32 *Edx OPTIONAL\r |
| 1519 | )\r | |
| 1520 | {\r | |
| 1521 | return gUnitTestHostBaseLib.X86->AsmCpuid (Index, Eax, Ebx, Ecx, Edx);\r | |
| 1522 | }\r | |
| 1523 | \r | |
| 1524 | /**\r | |
| 1525 | Retrieves CPUID information using an extended leaf identifier.\r | |
| 1526 | \r | |
| 1527 | Executes the CPUID instruction with EAX set to the value specified by Index\r | |
| 1528 | and ECX set to the value specified by SubIndex. This function always returns\r | |
| 1529 | Index. This function is only available on IA-32 and x64.\r | |
| 1530 | \r | |
| 1531 | If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r | |
| 1532 | If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r | |
| 1533 | If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r | |
| 1534 | If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r | |
| 1535 | \r | |
| 1536 | @param Index The 32-bit value to load into EAX prior to invoking the\r | |
| 1537 | CPUID instruction.\r | |
| 1538 | @param SubIndex The 32-bit value to load into ECX prior to invoking the\r | |
| 1539 | CPUID instruction.\r | |
| 1540 | @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r | |
| 1541 | instruction. This is an optional parameter that may be\r | |
| 1542 | NULL.\r | |
| 1543 | @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r | |
| 1544 | instruction. This is an optional parameter that may be\r | |
| 1545 | NULL.\r | |
| 1546 | @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r | |
| 1547 | instruction. This is an optional parameter that may be\r | |
| 1548 | NULL.\r | |
| 1549 | @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r | |
| 1550 | instruction. This is an optional parameter that may be\r | |
| 1551 | NULL.\r | |
| 1552 | \r | |
| 1553 | @return Index.\r | |
| 1554 | \r | |
| 1555 | **/\r | |
| 1556 | UINT32\r | |
| 1557 | EFIAPI\r | |
| 1558 | AsmCpuidEx (\r | |
| 1559 | IN UINT32 Index,\r | |
| 1560 | IN UINT32 SubIndex,\r | |
| d0e2f823 MK |
1561 | OUT UINT32 *Eax OPTIONAL,\r |
| 1562 | OUT UINT32 *Ebx OPTIONAL,\r | |
| 1563 | OUT UINT32 *Ecx OPTIONAL,\r | |
| 540fd45f MK |
1564 | OUT UINT32 *Edx OPTIONAL\r |
| 1565 | )\r | |
| 1566 | {\r | |
| 1567 | return gUnitTestHostBaseLib.X86->AsmCpuidEx (Index, SubIndex, Eax, Ebx, Ecx, Edx);\r | |
| 1568 | }\r | |
| 1569 | \r | |
| 1570 | /**\r | |
| 1571 | Set CD bit and clear NW bit of CR0 followed by a WBINVD.\r | |
| 1572 | \r | |
| 1573 | Disables the caches by setting the CD bit of CR0 to 1, clearing the NW bit of CR0 to 0,\r | |
| 1574 | and executing a WBINVD instruction. This function is only available on IA-32 and x64.\r | |
| 1575 | \r | |
| 1576 | **/\r | |
| 1577 | VOID\r | |
| 1578 | EFIAPI\r | |
| 1579 | AsmDisableCache (\r | |
| 1580 | VOID\r | |
| 1581 | )\r | |
| 1582 | {\r | |
| 1583 | gUnitTestHostBaseLib.X86->AsmDisableCache ();\r | |
| 1584 | }\r | |
| 1585 | \r | |
| 1586 | /**\r | |
| 1587 | Perform a WBINVD and clear both the CD and NW bits of CR0.\r | |
| 1588 | \r | |
| 1589 | Enables the caches by executing a WBINVD instruction and then clear both the CD and NW\r | |
| 1590 | bits of CR0 to 0. This function is only available on IA-32 and x64.\r | |
| 1591 | \r | |
| 1592 | **/\r | |
| 1593 | VOID\r | |
| 1594 | EFIAPI\r | |
| 1595 | AsmEnableCache (\r | |
| 1596 | VOID\r | |
| 1597 | )\r | |
| 1598 | {\r | |
| 1599 | gUnitTestHostBaseLib.X86->AsmEnableCache ();\r | |
| 1600 | }\r | |
| 1601 | \r | |
| 1602 | /**\r | |
| 1603 | Returns a 64-bit Machine Specific Register(MSR).\r | |
| 1604 | \r | |
| 1605 | Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r | |
| 1606 | performed on Index, and some Index values may cause CPU exceptions. The\r | |
| 1607 | caller must either guarantee that Index is valid, or the caller must set up\r | |
| 1608 | exception handlers to catch the exceptions. This function is only available\r | |
| 1609 | on IA-32 and x64.\r | |
| 1610 | \r | |
| 1611 | @param Index The 32-bit MSR index to read.\r | |
| 1612 | \r | |
| 1613 | @return The value of the MSR identified by Index.\r | |
| 1614 | \r | |
| 1615 | **/\r | |
| 1616 | UINT64\r | |
| 1617 | EFIAPI\r | |
| 1618 | AsmReadMsr64 (\r | |
| 1619 | IN UINT32 Index\r | |
| 1620 | )\r | |
| 1621 | {\r | |
| 1622 | return gUnitTestHostBaseLib.X86->AsmReadMsr64 (Index);\r | |
| 1623 | }\r | |
| 1624 | \r | |
| 1625 | /**\r | |
| 1626 | Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r | |
| 1627 | value.\r | |
| 1628 | \r | |
| 1629 | Writes the 64-bit value specified by Value to the MSR specified by Index. The\r | |
| 1630 | 64-bit value written to the MSR is returned. No parameter checking is\r | |
| 1631 | performed on Index or Value, and some of these may cause CPU exceptions. The\r | |
| 1632 | caller must either guarantee that Index and Value are valid, or the caller\r | |
| 1633 | must establish proper exception handlers. This function is only available on\r | |
| 1634 | IA-32 and x64.\r | |
| 1635 | \r | |
| 1636 | @param Index The 32-bit MSR index to write.\r | |
| 1637 | @param Value The 64-bit value to write to the MSR.\r | |
| 1638 | \r | |
| 1639 | @return Value\r | |
| 1640 | \r | |
| 1641 | **/\r | |
| 1642 | UINT64\r | |
| 1643 | EFIAPI\r | |
| 1644 | AsmWriteMsr64 (\r | |
| 1645 | IN UINT32 Index,\r | |
| 1646 | IN UINT64 Value\r | |
| 1647 | )\r | |
| 1648 | {\r | |
| 1649 | return gUnitTestHostBaseLib.X86->AsmWriteMsr64 (Index, Value);\r | |
| 1650 | }\r | |
| 1651 | \r | |
| 1652 | /**\r | |
| 1653 | Reads the current value of the Control Register 0 (CR0).\r | |
| 1654 | \r | |
| 1655 | Reads and returns the current value of CR0. This function is only available\r | |
| 1656 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1657 | x64.\r | |
| 1658 | \r | |
| 1659 | @return The value of the Control Register 0 (CR0).\r | |
| 1660 | \r | |
| 1661 | **/\r | |
| 1662 | UINTN\r | |
| 1663 | EFIAPI\r | |
| 1664 | AsmReadCr0 (\r | |
| 1665 | VOID\r | |
| 1666 | )\r | |
| 1667 | {\r | |
| 1668 | return gUnitTestHostBaseLib.X86->AsmReadCr0 ();\r | |
| 1669 | }\r | |
| 1670 | \r | |
| 1671 | /**\r | |
| 1672 | Reads the current value of the Control Register 2 (CR2).\r | |
| 1673 | \r | |
| 1674 | Reads and returns the current value of CR2. This function is only available\r | |
| 1675 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1676 | x64.\r | |
| 1677 | \r | |
| 1678 | @return The value of the Control Register 2 (CR2).\r | |
| 1679 | \r | |
| 1680 | **/\r | |
| 1681 | UINTN\r | |
| 1682 | EFIAPI\r | |
| 1683 | AsmReadCr2 (\r | |
| 1684 | VOID\r | |
| 1685 | )\r | |
| 1686 | {\r | |
| 1687 | return gUnitTestHostBaseLib.X86->AsmReadCr2 ();\r | |
| 1688 | }\r | |
| 1689 | \r | |
| 1690 | /**\r | |
| 1691 | Reads the current value of the Control Register 3 (CR3).\r | |
| 1692 | \r | |
| 1693 | Reads and returns the current value of CR3. This function is only available\r | |
| 1694 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1695 | x64.\r | |
| 1696 | \r | |
| 1697 | @return The value of the Control Register 3 (CR3).\r | |
| 1698 | \r | |
| 1699 | **/\r | |
| 1700 | UINTN\r | |
| 1701 | EFIAPI\r | |
| 1702 | AsmReadCr3 (\r | |
| 1703 | VOID\r | |
| 1704 | )\r | |
| 1705 | {\r | |
| 1706 | return gUnitTestHostBaseLib.X86->AsmReadCr3 ();\r | |
| 1707 | }\r | |
| 1708 | \r | |
| 1709 | /**\r | |
| 1710 | Reads the current value of the Control Register 4 (CR4).\r | |
| 1711 | \r | |
| 1712 | Reads and returns the current value of CR4. This function is only available\r | |
| 1713 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1714 | x64.\r | |
| 1715 | \r | |
| 1716 | @return The value of the Control Register 4 (CR4).\r | |
| 1717 | \r | |
| 1718 | **/\r | |
| 1719 | UINTN\r | |
| 1720 | EFIAPI\r | |
| 1721 | AsmReadCr4 (\r | |
| 1722 | VOID\r | |
| 1723 | )\r | |
| 1724 | {\r | |
| 1725 | return gUnitTestHostBaseLib.X86->AsmReadCr4 ();\r | |
| 1726 | }\r | |
| 1727 | \r | |
| 1728 | /**\r | |
| 1729 | Writes a value to Control Register 0 (CR0).\r | |
| 1730 | \r | |
| 1731 | Writes and returns a new value to CR0. This function is only available on\r | |
| 1732 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1733 | \r | |
| 1734 | @param Cr0 The value to write to CR0.\r | |
| 1735 | \r | |
| 1736 | @return The value written to CR0.\r | |
| 1737 | \r | |
| 1738 | **/\r | |
| 1739 | UINTN\r | |
| 1740 | EFIAPI\r | |
| 1741 | AsmWriteCr0 (\r | |
| 1742 | UINTN Cr0\r | |
| 1743 | )\r | |
| 1744 | {\r | |
| 1745 | return gUnitTestHostBaseLib.X86->AsmWriteCr0 (Cr0);\r | |
| 1746 | }\r | |
| 1747 | \r | |
| 1748 | /**\r | |
| 1749 | Writes a value to Control Register 2 (CR2).\r | |
| 1750 | \r | |
| 1751 | Writes and returns a new value to CR2. This function is only available on\r | |
| 1752 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1753 | \r | |
| 1754 | @param Cr2 The value to write to CR2.\r | |
| 1755 | \r | |
| 1756 | @return The value written to CR2.\r | |
| 1757 | \r | |
| 1758 | **/\r | |
| 1759 | UINTN\r | |
| 1760 | EFIAPI\r | |
| 1761 | AsmWriteCr2 (\r | |
| 1762 | UINTN Cr2\r | |
| 1763 | )\r | |
| 1764 | {\r | |
| 1765 | return gUnitTestHostBaseLib.X86->AsmWriteCr2 (Cr2);\r | |
| 1766 | }\r | |
| 1767 | \r | |
| 1768 | /**\r | |
| 1769 | Writes a value to Control Register 3 (CR3).\r | |
| 1770 | \r | |
| 1771 | Writes and returns a new value to CR3. This function is only available on\r | |
| 1772 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1773 | \r | |
| 1774 | @param Cr3 The value to write to CR3.\r | |
| 1775 | \r | |
| 1776 | @return The value written to CR3.\r | |
| 1777 | \r | |
| 1778 | **/\r | |
| 1779 | UINTN\r | |
| 1780 | EFIAPI\r | |
| 1781 | AsmWriteCr3 (\r | |
| 1782 | UINTN Cr3\r | |
| 1783 | )\r | |
| 1784 | {\r | |
| 1785 | return gUnitTestHostBaseLib.X86->AsmWriteCr3 (Cr3);\r | |
| 1786 | }\r | |
| 1787 | \r | |
| 1788 | /**\r | |
| 1789 | Writes a value to Control Register 4 (CR4).\r | |
| 1790 | \r | |
| 1791 | Writes and returns a new value to CR4. This function is only available on\r | |
| 1792 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1793 | \r | |
| 1794 | @param Cr4 The value to write to CR4.\r | |
| 1795 | \r | |
| 1796 | @return The value written to CR4.\r | |
| 1797 | \r | |
| 1798 | **/\r | |
| 1799 | UINTN\r | |
| 1800 | EFIAPI\r | |
| 1801 | AsmWriteCr4 (\r | |
| 1802 | UINTN Cr4\r | |
| 1803 | )\r | |
| 1804 | {\r | |
| 1805 | return gUnitTestHostBaseLib.X86->AsmWriteCr4 (Cr4);\r | |
| 1806 | }\r | |
| 1807 | \r | |
| 1808 | /**\r | |
| 1809 | Reads the current value of Debug Register 0 (DR0).\r | |
| 1810 | \r | |
| 1811 | Reads and returns the current value of DR0. This function is only available\r | |
| 1812 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1813 | x64.\r | |
| 1814 | \r | |
| 1815 | @return The value of Debug Register 0 (DR0).\r | |
| 1816 | \r | |
| 1817 | **/\r | |
| 1818 | UINTN\r | |
| 1819 | EFIAPI\r | |
| 1820 | AsmReadDr0 (\r | |
| 1821 | VOID\r | |
| 1822 | )\r | |
| 1823 | {\r | |
| 1824 | return gUnitTestHostBaseLib.X86->AsmReadDr0 ();\r | |
| 1825 | }\r | |
| 1826 | \r | |
| 1827 | /**\r | |
| 1828 | Reads the current value of Debug Register 1 (DR1).\r | |
| 1829 | \r | |
| 1830 | Reads and returns the current value of DR1. This function is only available\r | |
| 1831 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1832 | x64.\r | |
| 1833 | \r | |
| 1834 | @return The value of Debug Register 1 (DR1).\r | |
| 1835 | \r | |
| 1836 | **/\r | |
| 1837 | UINTN\r | |
| 1838 | EFIAPI\r | |
| 1839 | AsmReadDr1 (\r | |
| 1840 | VOID\r | |
| 1841 | )\r | |
| 1842 | {\r | |
| 1843 | return gUnitTestHostBaseLib.X86->AsmReadDr1 ();\r | |
| 1844 | }\r | |
| 1845 | \r | |
| 1846 | /**\r | |
| 1847 | Reads the current value of Debug Register 2 (DR2).\r | |
| 1848 | \r | |
| 1849 | Reads and returns the current value of DR2. This function is only available\r | |
| 1850 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1851 | x64.\r | |
| 1852 | \r | |
| 1853 | @return The value of Debug Register 2 (DR2).\r | |
| 1854 | \r | |
| 1855 | **/\r | |
| 1856 | UINTN\r | |
| 1857 | EFIAPI\r | |
| 1858 | AsmReadDr2 (\r | |
| 1859 | VOID\r | |
| 1860 | )\r | |
| 1861 | {\r | |
| 1862 | return gUnitTestHostBaseLib.X86->AsmReadDr2 ();\r | |
| 1863 | }\r | |
| 1864 | \r | |
| 1865 | /**\r | |
| 1866 | Reads the current value of Debug Register 3 (DR3).\r | |
| 1867 | \r | |
| 1868 | Reads and returns the current value of DR3. This function is only available\r | |
| 1869 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1870 | x64.\r | |
| 1871 | \r | |
| 1872 | @return The value of Debug Register 3 (DR3).\r | |
| 1873 | \r | |
| 1874 | **/\r | |
| 1875 | UINTN\r | |
| 1876 | EFIAPI\r | |
| 1877 | AsmReadDr3 (\r | |
| 1878 | VOID\r | |
| 1879 | )\r | |
| 1880 | {\r | |
| 1881 | return gUnitTestHostBaseLib.X86->AsmReadDr3 ();\r | |
| 1882 | }\r | |
| 1883 | \r | |
| 1884 | /**\r | |
| 1885 | Reads the current value of Debug Register 4 (DR4).\r | |
| 1886 | \r | |
| 1887 | Reads and returns the current value of DR4. This function is only available\r | |
| 1888 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1889 | x64.\r | |
| 1890 | \r | |
| 1891 | @return The value of Debug Register 4 (DR4).\r | |
| 1892 | \r | |
| 1893 | **/\r | |
| 1894 | UINTN\r | |
| 1895 | EFIAPI\r | |
| 1896 | AsmReadDr4 (\r | |
| 1897 | VOID\r | |
| 1898 | )\r | |
| 1899 | {\r | |
| 1900 | return gUnitTestHostBaseLib.X86->AsmReadDr4 ();\r | |
| 1901 | }\r | |
| 1902 | \r | |
| 1903 | /**\r | |
| 1904 | Reads the current value of Debug Register 5 (DR5).\r | |
| 1905 | \r | |
| 1906 | Reads and returns the current value of DR5. This function is only available\r | |
| 1907 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1908 | x64.\r | |
| 1909 | \r | |
| 1910 | @return The value of Debug Register 5 (DR5).\r | |
| 1911 | \r | |
| 1912 | **/\r | |
| 1913 | UINTN\r | |
| 1914 | EFIAPI\r | |
| 1915 | AsmReadDr5 (\r | |
| 1916 | VOID\r | |
| 1917 | )\r | |
| 1918 | {\r | |
| 1919 | return gUnitTestHostBaseLib.X86->AsmReadDr5 ();\r | |
| 1920 | }\r | |
| 1921 | \r | |
| 1922 | /**\r | |
| 1923 | Reads the current value of Debug Register 6 (DR6).\r | |
| 1924 | \r | |
| 1925 | Reads and returns the current value of DR6. This function is only available\r | |
| 1926 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1927 | x64.\r | |
| 1928 | \r | |
| 1929 | @return The value of Debug Register 6 (DR6).\r | |
| 1930 | \r | |
| 1931 | **/\r | |
| 1932 | UINTN\r | |
| 1933 | EFIAPI\r | |
| 1934 | AsmReadDr6 (\r | |
| 1935 | VOID\r | |
| 1936 | )\r | |
| 1937 | {\r | |
| 1938 | return gUnitTestHostBaseLib.X86->AsmReadDr6 ();\r | |
| 1939 | }\r | |
| 1940 | \r | |
| 1941 | /**\r | |
| 1942 | Reads the current value of Debug Register 7 (DR7).\r | |
| 1943 | \r | |
| 1944 | Reads and returns the current value of DR7. This function is only available\r | |
| 1945 | on IA-32 and x64. This returns a 32-bit value on IA-32 and a 64-bit value on\r | |
| 1946 | x64.\r | |
| 1947 | \r | |
| 1948 | @return The value of Debug Register 7 (DR7).\r | |
| 1949 | \r | |
| 1950 | **/\r | |
| 1951 | UINTN\r | |
| 1952 | EFIAPI\r | |
| 1953 | AsmReadDr7 (\r | |
| 1954 | VOID\r | |
| 1955 | )\r | |
| 1956 | {\r | |
| 1957 | return gUnitTestHostBaseLib.X86->AsmReadDr7 ();\r | |
| 1958 | }\r | |
| 1959 | \r | |
| 1960 | /**\r | |
| 1961 | Writes a value to Debug Register 0 (DR0).\r | |
| 1962 | \r | |
| 1963 | Writes and returns a new value to DR0. This function is only available on\r | |
| 1964 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1965 | \r | |
| 1966 | @param Dr0 The value to write to Dr0.\r | |
| 1967 | \r | |
| 1968 | @return The value written to Debug Register 0 (DR0).\r | |
| 1969 | \r | |
| 1970 | **/\r | |
| 1971 | UINTN\r | |
| 1972 | EFIAPI\r | |
| 1973 | AsmWriteDr0 (\r | |
| 1974 | UINTN Dr0\r | |
| 1975 | )\r | |
| 1976 | {\r | |
| 1977 | return gUnitTestHostBaseLib.X86->AsmWriteDr0 (Dr0);\r | |
| 1978 | }\r | |
| 1979 | \r | |
| 1980 | /**\r | |
| 1981 | Writes a value to Debug Register 1 (DR1).\r | |
| 1982 | \r | |
| 1983 | Writes and returns a new value to DR1. This function is only available on\r | |
| 1984 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 1985 | \r | |
| 1986 | @param Dr1 The value to write to Dr1.\r | |
| 1987 | \r | |
| 1988 | @return The value written to Debug Register 1 (DR1).\r | |
| 1989 | \r | |
| 1990 | **/\r | |
| 1991 | UINTN\r | |
| 1992 | EFIAPI\r | |
| 1993 | AsmWriteDr1 (\r | |
| 1994 | UINTN Dr1\r | |
| 1995 | )\r | |
| 1996 | {\r | |
| 1997 | return gUnitTestHostBaseLib.X86->AsmWriteDr1 (Dr1);\r | |
| 1998 | }\r | |
| 1999 | \r | |
| 2000 | /**\r | |
| 2001 | Writes a value to Debug Register 2 (DR2).\r | |
| 2002 | \r | |
| 2003 | Writes and returns a new value to DR2. This function is only available on\r | |
| 2004 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2005 | \r | |
| 2006 | @param Dr2 The value to write to Dr2.\r | |
| 2007 | \r | |
| 2008 | @return The value written to Debug Register 2 (DR2).\r | |
| 2009 | \r | |
| 2010 | **/\r | |
| 2011 | UINTN\r | |
| 2012 | EFIAPI\r | |
| 2013 | AsmWriteDr2 (\r | |
| 2014 | UINTN Dr2\r | |
| 2015 | )\r | |
| 2016 | {\r | |
| 2017 | return gUnitTestHostBaseLib.X86->AsmWriteDr2 (Dr2);\r | |
| 2018 | }\r | |
| 2019 | \r | |
| 2020 | /**\r | |
| 2021 | Writes a value to Debug Register 3 (DR3).\r | |
| 2022 | \r | |
| 2023 | Writes and returns a new value to DR3. This function is only available on\r | |
| 2024 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2025 | \r | |
| 2026 | @param Dr3 The value to write to Dr3.\r | |
| 2027 | \r | |
| 2028 | @return The value written to Debug Register 3 (DR3).\r | |
| 2029 | \r | |
| 2030 | **/\r | |
| 2031 | UINTN\r | |
| 2032 | EFIAPI\r | |
| 2033 | AsmWriteDr3 (\r | |
| 2034 | UINTN Dr3\r | |
| 2035 | )\r | |
| 2036 | {\r | |
| 2037 | return gUnitTestHostBaseLib.X86->AsmWriteDr3 (Dr3);\r | |
| 2038 | }\r | |
| 2039 | \r | |
| 2040 | /**\r | |
| 2041 | Writes a value to Debug Register 4 (DR4).\r | |
| 2042 | \r | |
| 2043 | Writes and returns a new value to DR4. This function is only available on\r | |
| 2044 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2045 | \r | |
| 2046 | @param Dr4 The value to write to Dr4.\r | |
| 2047 | \r | |
| 2048 | @return The value written to Debug Register 4 (DR4).\r | |
| 2049 | \r | |
| 2050 | **/\r | |
| 2051 | UINTN\r | |
| 2052 | EFIAPI\r | |
| 2053 | AsmWriteDr4 (\r | |
| 2054 | UINTN Dr4\r | |
| 2055 | )\r | |
| 2056 | {\r | |
| 2057 | return gUnitTestHostBaseLib.X86->AsmWriteDr4 (Dr4);\r | |
| 2058 | }\r | |
| 2059 | \r | |
| 2060 | /**\r | |
| 2061 | Writes a value to Debug Register 5 (DR5).\r | |
| 2062 | \r | |
| 2063 | Writes and returns a new value to DR5. This function is only available on\r | |
| 2064 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2065 | \r | |
| 2066 | @param Dr5 The value to write to Dr5.\r | |
| 2067 | \r | |
| 2068 | @return The value written to Debug Register 5 (DR5).\r | |
| 2069 | \r | |
| 2070 | **/\r | |
| 2071 | UINTN\r | |
| 2072 | EFIAPI\r | |
| 2073 | AsmWriteDr5 (\r | |
| 2074 | UINTN Dr5\r | |
| 2075 | )\r | |
| 2076 | {\r | |
| 2077 | return gUnitTestHostBaseLib.X86->AsmWriteDr5 (Dr5);\r | |
| 2078 | }\r | |
| 2079 | \r | |
| 2080 | /**\r | |
| 2081 | Writes a value to Debug Register 6 (DR6).\r | |
| 2082 | \r | |
| 2083 | Writes and returns a new value to DR6. This function is only available on\r | |
| 2084 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2085 | \r | |
| 2086 | @param Dr6 The value to write to Dr6.\r | |
| 2087 | \r | |
| 2088 | @return The value written to Debug Register 6 (DR6).\r | |
| 2089 | \r | |
| 2090 | **/\r | |
| 2091 | UINTN\r | |
| 2092 | EFIAPI\r | |
| 2093 | AsmWriteDr6 (\r | |
| 2094 | UINTN Dr6\r | |
| 2095 | )\r | |
| 2096 | {\r | |
| 2097 | return gUnitTestHostBaseLib.X86->AsmWriteDr6 (Dr6);\r | |
| 2098 | }\r | |
| 2099 | \r | |
| 2100 | /**\r | |
| 2101 | Writes a value to Debug Register 7 (DR7).\r | |
| 2102 | \r | |
| 2103 | Writes and returns a new value to DR7. This function is only available on\r | |
| 2104 | IA-32 and x64. This writes a 32-bit value on IA-32 and a 64-bit value on x64.\r | |
| 2105 | \r | |
| 2106 | @param Dr7 The value to write to Dr7.\r | |
| 2107 | \r | |
| 2108 | @return The value written to Debug Register 7 (DR7).\r | |
| 2109 | \r | |
| 2110 | **/\r | |
| 2111 | UINTN\r | |
| 2112 | EFIAPI\r | |
| 2113 | AsmWriteDr7 (\r | |
| 2114 | UINTN Dr7\r | |
| 2115 | )\r | |
| 2116 | {\r | |
| 2117 | return gUnitTestHostBaseLib.X86->AsmWriteDr7 (Dr7);\r | |
| 2118 | }\r | |
| 2119 | \r | |
| 2120 | /**\r | |
| 2121 | Reads the current value of Code Segment Register (CS).\r | |
| 2122 | \r | |
| 2123 | Reads and returns the current value of CS. This function is only available on\r | |
| 2124 | IA-32 and x64.\r | |
| 2125 | \r | |
| 2126 | @return The current value of CS.\r | |
| 2127 | \r | |
| 2128 | **/\r | |
| 2129 | UINT16\r | |
| 2130 | EFIAPI\r | |
| 2131 | AsmReadCs (\r | |
| 2132 | VOID\r | |
| 2133 | )\r | |
| 2134 | {\r | |
| 2135 | return gUnitTestHostBaseLib.X86->AsmReadCs ();\r | |
| 2136 | }\r | |
| 2137 | \r | |
| 2138 | /**\r | |
| 2139 | Reads the current value of Data Segment Register (DS).\r | |
| 2140 | \r | |
| 2141 | Reads and returns the current value of DS. This function is only available on\r | |
| 2142 | IA-32 and x64.\r | |
| 2143 | \r | |
| 2144 | @return The current value of DS.\r | |
| 2145 | \r | |
| 2146 | **/\r | |
| 2147 | UINT16\r | |
| 2148 | EFIAPI\r | |
| 2149 | AsmReadDs (\r | |
| 2150 | VOID\r | |
| 2151 | )\r | |
| 2152 | {\r | |
| 2153 | return gUnitTestHostBaseLib.X86->AsmReadDs ();\r | |
| 2154 | }\r | |
| 2155 | \r | |
| 2156 | /**\r | |
| 2157 | Reads the current value of Extra Segment Register (ES).\r | |
| 2158 | \r | |
| 2159 | Reads and returns the current value of ES. This function is only available on\r | |
| 2160 | IA-32 and x64.\r | |
| 2161 | \r | |
| 2162 | @return The current value of ES.\r | |
| 2163 | \r | |
| 2164 | **/\r | |
| 2165 | UINT16\r | |
| 2166 | EFIAPI\r | |
| 2167 | AsmReadEs (\r | |
| 2168 | VOID\r | |
| 2169 | )\r | |
| 2170 | {\r | |
| 2171 | return gUnitTestHostBaseLib.X86->AsmReadEs ();\r | |
| 2172 | }\r | |
| 2173 | \r | |
| 2174 | /**\r | |
| 2175 | Reads the current value of FS Data Segment Register (FS).\r | |
| 2176 | \r | |
| 2177 | Reads and returns the current value of FS. This function is only available on\r | |
| 2178 | IA-32 and x64.\r | |
| 2179 | \r | |
| 2180 | @return The current value of FS.\r | |
| 2181 | \r | |
| 2182 | **/\r | |
| 2183 | UINT16\r | |
| 2184 | EFIAPI\r | |
| 2185 | AsmReadFs (\r | |
| 2186 | VOID\r | |
| 2187 | )\r | |
| 2188 | {\r | |
| 2189 | return gUnitTestHostBaseLib.X86->AsmReadFs ();\r | |
| 2190 | }\r | |
| 2191 | \r | |
| 2192 | /**\r | |
| 2193 | Reads the current value of GS Data Segment Register (GS).\r | |
| 2194 | \r | |
| 2195 | Reads and returns the current value of GS. This function is only available on\r | |
| 2196 | IA-32 and x64.\r | |
| 2197 | \r | |
| 2198 | @return The current value of GS.\r | |
| 2199 | \r | |
| 2200 | **/\r | |
| 2201 | UINT16\r | |
| 2202 | EFIAPI\r | |
| 2203 | AsmReadGs (\r | |
| 2204 | VOID\r | |
| 2205 | )\r | |
| 2206 | {\r | |
| 2207 | return gUnitTestHostBaseLib.X86->AsmReadGs ();\r | |
| 2208 | }\r | |
| 2209 | \r | |
| 2210 | /**\r | |
| 2211 | Reads the current value of Stack Segment Register (SS).\r | |
| 2212 | \r | |
| 2213 | Reads and returns the current value of SS. This function is only available on\r | |
| 2214 | IA-32 and x64.\r | |
| 2215 | \r | |
| 2216 | @return The current value of SS.\r | |
| 2217 | \r | |
| 2218 | **/\r | |
| 2219 | UINT16\r | |
| 2220 | EFIAPI\r | |
| 2221 | AsmReadSs (\r | |
| 2222 | VOID\r | |
| 2223 | )\r | |
| 2224 | {\r | |
| 2225 | return gUnitTestHostBaseLib.X86->AsmReadSs ();\r | |
| 2226 | }\r | |
| 2227 | \r | |
| 2228 | /**\r | |
| 2229 | Reads the current value of Task Register (TR).\r | |
| 2230 | \r | |
| 2231 | Reads and returns the current value of TR. This function is only available on\r | |
| 2232 | IA-32 and x64.\r | |
| 2233 | \r | |
| 2234 | @return The current value of TR.\r | |
| 2235 | \r | |
| 2236 | **/\r | |
| 2237 | UINT16\r | |
| 2238 | EFIAPI\r | |
| 2239 | AsmReadTr (\r | |
| 2240 | VOID\r | |
| 2241 | )\r | |
| 2242 | {\r | |
| 2243 | return gUnitTestHostBaseLib.X86->AsmReadTr ();\r | |
| 2244 | }\r | |
| 2245 | \r | |
| 2246 | /**\r | |
| 2247 | Reads the current Global Descriptor Table Register(GDTR) descriptor.\r | |
| 2248 | \r | |
| 2249 | Reads and returns the current GDTR descriptor and returns it in Gdtr. This\r | |
| 2250 | function is only available on IA-32 and x64.\r | |
| 2251 | \r | |
| 2252 | If Gdtr is NULL, then ASSERT().\r | |
| 2253 | \r | |
| 2254 | @param Gdtr The pointer to a GDTR descriptor.\r | |
| 2255 | \r | |
| 2256 | **/\r | |
| 2257 | VOID\r | |
| 2258 | EFIAPI\r | |
| 2259 | AsmReadGdtr (\r | |
| 2260 | OUT IA32_DESCRIPTOR *Gdtr\r | |
| 2261 | )\r | |
| 2262 | {\r | |
| 2263 | gUnitTestHostBaseLib.X86->AsmReadGdtr (Gdtr);\r | |
| 2264 | }\r | |
| 2265 | \r | |
| 2266 | /**\r | |
| 2267 | Writes the current Global Descriptor Table Register (GDTR) descriptor.\r | |
| 2268 | \r | |
| 2269 | Writes and the current GDTR descriptor specified by Gdtr. This function is\r | |
| 2270 | only available on IA-32 and x64.\r | |
| 2271 | \r | |
| 2272 | If Gdtr is NULL, then ASSERT().\r | |
| 2273 | \r | |
| 2274 | @param Gdtr The pointer to a GDTR descriptor.\r | |
| 2275 | \r | |
| 2276 | **/\r | |
| 2277 | VOID\r | |
| 2278 | EFIAPI\r | |
| 2279 | AsmWriteGdtr (\r | |
| 2280 | IN CONST IA32_DESCRIPTOR *Gdtr\r | |
| 2281 | )\r | |
| 2282 | {\r | |
| 2283 | gUnitTestHostBaseLib.X86->AsmWriteGdtr (Gdtr);\r | |
| 2284 | }\r | |
| 2285 | \r | |
| 2286 | /**\r | |
| 2287 | Reads the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
| 2288 | \r | |
| 2289 | Reads and returns the current IDTR descriptor and returns it in Idtr. This\r | |
| 2290 | function is only available on IA-32 and x64.\r | |
| 2291 | \r | |
| 2292 | If Idtr is NULL, then ASSERT().\r | |
| 2293 | \r | |
| 2294 | @param Idtr The pointer to a IDTR descriptor.\r | |
| 2295 | \r | |
| 2296 | **/\r | |
| 2297 | VOID\r | |
| 2298 | EFIAPI\r | |
| 2299 | AsmReadIdtr (\r | |
| 2300 | OUT IA32_DESCRIPTOR *Idtr\r | |
| 2301 | )\r | |
| 2302 | {\r | |
| 2303 | gUnitTestHostBaseLib.X86->AsmReadIdtr (Idtr);\r | |
| 2304 | }\r | |
| 2305 | \r | |
| 2306 | /**\r | |
| 2307 | Writes the current Interrupt Descriptor Table Register(IDTR) descriptor.\r | |
| 2308 | \r | |
| 2309 | Writes the current IDTR descriptor and returns it in Idtr. This function is\r | |
| 2310 | only available on IA-32 and x64.\r | |
| 2311 | \r | |
| 2312 | If Idtr is NULL, then ASSERT().\r | |
| 2313 | \r | |
| 2314 | @param Idtr The pointer to a IDTR descriptor.\r | |
| 2315 | \r | |
| 2316 | **/\r | |
| 2317 | VOID\r | |
| 2318 | EFIAPI\r | |
| 2319 | AsmWriteIdtr (\r | |
| 2320 | IN CONST IA32_DESCRIPTOR *Idtr\r | |
| 2321 | )\r | |
| 2322 | {\r | |
| 2323 | gUnitTestHostBaseLib.X86->AsmWriteIdtr (Idtr);\r | |
| 2324 | }\r | |
| 2325 | \r | |
| 2326 | /**\r | |
| 2327 | Reads the current Local Descriptor Table Register(LDTR) selector.\r | |
| 2328 | \r | |
| 2329 | Reads and returns the current 16-bit LDTR descriptor value. This function is\r | |
| 2330 | only available on IA-32 and x64.\r | |
| 2331 | \r | |
| 2332 | @return The current selector of LDT.\r | |
| 2333 | \r | |
| 2334 | **/\r | |
| 2335 | UINT16\r | |
| 2336 | EFIAPI\r | |
| 2337 | AsmReadLdtr (\r | |
| 2338 | VOID\r | |
| 2339 | )\r | |
| 2340 | {\r | |
| 2341 | return gUnitTestHostBaseLib.X86->AsmReadLdtr ();\r | |
| 2342 | }\r | |
| 2343 | \r | |
| 2344 | /**\r | |
| 2345 | Writes the current Local Descriptor Table Register (LDTR) selector.\r | |
| 2346 | \r | |
| 2347 | Writes and the current LDTR descriptor specified by Ldtr. This function is\r | |
| 2348 | only available on IA-32 and x64.\r | |
| 2349 | \r | |
| 2350 | @param Ldtr 16-bit LDTR selector value.\r | |
| 2351 | \r | |
| 2352 | **/\r | |
| 2353 | VOID\r | |
| 2354 | EFIAPI\r | |
| 2355 | AsmWriteLdtr (\r | |
| 2356 | IN UINT16 Ldtr\r | |
| 2357 | )\r | |
| 2358 | {\r | |
| 2359 | gUnitTestHostBaseLib.X86->AsmWriteLdtr (Ldtr);\r | |
| 2360 | }\r | |
| 2361 | \r | |
| 2362 | /**\r | |
| 2363 | Reads the current value of a Performance Counter (PMC).\r | |
| 2364 | \r | |
| 2365 | Reads and returns the current value of performance counter specified by\r | |
| 2366 | Index. This function is only available on IA-32 and x64.\r | |
| 2367 | \r | |
| 2368 | @param Index The 32-bit Performance Counter index to read.\r | |
| 2369 | \r | |
| 2370 | @return The value of the PMC specified by Index.\r | |
| 2371 | \r | |
| 2372 | **/\r | |
| 2373 | UINT64\r | |
| 2374 | EFIAPI\r | |
| 2375 | AsmReadPmc (\r | |
| 2376 | IN UINT32 Index\r | |
| 2377 | )\r | |
| 2378 | {\r | |
| 2379 | return gUnitTestHostBaseLib.X86->AsmReadPmc (Index);\r | |
| 2380 | }\r | |
| 2381 | \r | |
| 2382 | /**\r | |
| 2383 | Sets up a monitor buffer that is used by AsmMwait().\r | |
| 2384 | \r | |
| 2385 | Executes a MONITOR instruction with the register state specified by Eax, Ecx\r | |
| 2386 | and Edx. Returns Eax. This function is only available on IA-32 and x64.\r | |
| 2387 | \r | |
| 2388 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
| 2389 | instruction.\r | |
| 2390 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
| 2391 | instruction.\r | |
| 2392 | @param Edx The value to load into EDX or RDX before executing the MONITOR\r | |
| 2393 | instruction.\r | |
| 2394 | \r | |
| 2395 | @return Eax\r | |
| 2396 | \r | |
| 2397 | **/\r | |
| 2398 | UINTN\r | |
| 2399 | EFIAPI\r | |
| 2400 | AsmMonitor (\r | |
| 2401 | IN UINTN Eax,\r | |
| 2402 | IN UINTN Ecx,\r | |
| 2403 | IN UINTN Edx\r | |
| 2404 | )\r | |
| 2405 | {\r | |
| 2406 | return gUnitTestHostBaseLib.X86->AsmMonitor (Eax, Ecx, Edx);\r | |
| 2407 | }\r | |
| 2408 | \r | |
| 2409 | /**\r | |
| 2410 | Executes an MWAIT instruction.\r | |
| 2411 | \r | |
| 2412 | Executes an MWAIT instruction with the register state specified by Eax and\r | |
| 2413 | Ecx. Returns Eax. This function is only available on IA-32 and x64.\r | |
| 2414 | \r | |
| 2415 | @param Eax The value to load into EAX or RAX before executing the MONITOR\r | |
| 2416 | instruction.\r | |
| 2417 | @param Ecx The value to load into ECX or RCX before executing the MONITOR\r | |
| 2418 | instruction.\r | |
| 2419 | \r | |
| 2420 | @return Eax\r | |
| 2421 | \r | |
| 2422 | **/\r | |
| 2423 | UINTN\r | |
| 2424 | EFIAPI\r | |
| 2425 | AsmMwait (\r | |
| 2426 | IN UINTN Eax,\r | |
| 2427 | IN UINTN Ecx\r | |
| 2428 | )\r | |
| 2429 | {\r | |
| 2430 | return gUnitTestHostBaseLib.X86->AsmMwait (Eax, Ecx);\r | |
| 2431 | }\r | |
| 2432 | \r | |
| 2433 | /**\r | |
| 2434 | Executes a WBINVD instruction.\r | |
| 2435 | \r | |
| 2436 | Executes a WBINVD instruction. This function is only available on IA-32 and\r | |
| 2437 | x64.\r | |
| 2438 | \r | |
| 2439 | **/\r | |
| 2440 | VOID\r | |
| 2441 | EFIAPI\r | |
| 2442 | AsmWbinvd (\r | |
| 2443 | VOID\r | |
| 2444 | )\r | |
| 2445 | {\r | |
| 2446 | gUnitTestHostBaseLib.X86->AsmWbinvd ();\r | |
| 2447 | }\r | |
| 2448 | \r | |
| 2449 | /**\r | |
| 2450 | Executes a INVD instruction.\r | |
| 2451 | \r | |
| 2452 | Executes a INVD instruction. This function is only available on IA-32 and\r | |
| 2453 | x64.\r | |
| 2454 | \r | |
| 2455 | **/\r | |
| 2456 | VOID\r | |
| 2457 | EFIAPI\r | |
| 2458 | AsmInvd (\r | |
| 2459 | VOID\r | |
| 2460 | )\r | |
| 2461 | {\r | |
| 2462 | gUnitTestHostBaseLib.X86->AsmInvd ();\r | |
| 2463 | }\r | |
| 2464 | \r | |
| 2465 | /**\r | |
| 2466 | Flushes a cache line from all the instruction and data caches within the\r | |
| 2467 | coherency domain of the CPU.\r | |
| 2468 | \r | |
| 2469 | Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r | |
| 2470 | This function is only available on IA-32 and x64.\r | |
| 2471 | \r | |
| 2472 | @param LinearAddress The address of the cache line to flush. If the CPU is\r | |
| 2473 | in a physical addressing mode, then LinearAddress is a\r | |
| 2474 | physical address. If the CPU is in a virtual\r | |
| 2475 | addressing mode, then LinearAddress is a virtual\r | |
| 2476 | address.\r | |
| 2477 | \r | |
| 2478 | @return LinearAddress.\r | |
| 2479 | **/\r | |
| 2480 | VOID *\r | |
| 2481 | EFIAPI\r | |
| 2482 | AsmFlushCacheLine (\r | |
| 2483 | IN VOID *LinearAddress\r | |
| 2484 | )\r | |
| 2485 | {\r | |
| 2486 | return gUnitTestHostBaseLib.X86->AsmFlushCacheLine (LinearAddress);\r | |
| 2487 | }\r | |
| 2488 | \r | |
| 2489 | /**\r | |
| 2490 | Enables the 32-bit paging mode on the CPU.\r | |
| 2491 | \r | |
| 2492 | Enables the 32-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
| 2493 | must be properly initialized prior to calling this service. This function\r | |
| 2494 | assumes the current execution mode is 32-bit protected mode. This function is\r | |
| 2495 | only available on IA-32. After the 32-bit paging mode is enabled, control is\r | |
| 2496 | transferred to the function specified by EntryPoint using the new stack\r | |
| 2497 | specified by NewStack and passing in the parameters specified by Context1 and\r | |
| 2498 | Context2. Context1 and Context2 are optional and may be NULL. The function\r | |
| 2499 | EntryPoint must never return.\r | |
| 2500 | \r | |
| 2501 | If the current execution mode is not 32-bit protected mode, then ASSERT().\r | |
| 2502 | If EntryPoint is NULL, then ASSERT().\r | |
| 2503 | If NewStack is NULL, then ASSERT().\r | |
| 2504 | \r | |
| 2505 | There are a number of constraints that must be followed before calling this\r | |
| 2506 | function:\r | |
| 2507 | 1) Interrupts must be disabled.\r | |
| 2508 | 2) The caller must be in 32-bit protected mode with flat descriptors. This\r | |
| 2509 | means all descriptors must have a base of 0 and a limit of 4GB.\r | |
| 2510 | 3) CR0 and CR4 must be compatible with 32-bit protected mode with flat\r | |
| 2511 | descriptors.\r | |
| 2512 | 4) CR3 must point to valid page tables that will be used once the transition\r | |
| 2513 | is complete, and those page tables must guarantee that the pages for this\r | |
| 2514 | function and the stack are identity mapped.\r | |
| 2515 | \r | |
| 2516 | @param EntryPoint A pointer to function to call with the new stack after\r | |
| 2517 | paging is enabled.\r | |
| 2518 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
| 2519 | function as the first parameter after paging is enabled.\r | |
| 2520 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
| 2521 | function as the second parameter after paging is enabled.\r | |
| 2522 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
| 2523 | function after paging is enabled.\r | |
| 2524 | \r | |
| 2525 | **/\r | |
| 2526 | VOID\r | |
| 2527 | EFIAPI\r | |
| 2528 | AsmEnablePaging32 (\r | |
| 2529 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
| d0e2f823 MK |
2530 | IN VOID *Context1 OPTIONAL,\r |
| 2531 | IN VOID *Context2 OPTIONAL,\r | |
| 540fd45f MK |
2532 | IN VOID *NewStack\r |
| 2533 | )\r | |
| 2534 | {\r | |
| 2535 | gUnitTestHostBaseLib.X86->AsmEnablePaging32 (EntryPoint, Context1, Context2, NewStack);\r | |
| 2536 | }\r | |
| 2537 | \r | |
| 2538 | /**\r | |
| 2539 | Disables the 32-bit paging mode on the CPU.\r | |
| 2540 | \r | |
| 2541 | Disables the 32-bit paging mode on the CPU and returns to 32-bit protected\r | |
| 2542 | mode. This function assumes the current execution mode is 32-paged protected\r | |
| 2543 | mode. This function is only available on IA-32. After the 32-bit paging mode\r | |
| 2544 | is disabled, control is transferred to the function specified by EntryPoint\r | |
| 2545 | using the new stack specified by NewStack and passing in the parameters\r | |
| 2546 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
| 2547 | may be NULL. The function EntryPoint must never return.\r | |
| 2548 | \r | |
| 2549 | If the current execution mode is not 32-bit paged mode, then ASSERT().\r | |
| 2550 | If EntryPoint is NULL, then ASSERT().\r | |
| 2551 | If NewStack is NULL, then ASSERT().\r | |
| 2552 | \r | |
| 2553 | There are a number of constraints that must be followed before calling this\r | |
| 2554 | function:\r | |
| 2555 | 1) Interrupts must be disabled.\r | |
| 2556 | 2) The caller must be in 32-bit paged mode.\r | |
| 2557 | 3) CR0, CR3, and CR4 must be compatible with 32-bit paged mode.\r | |
| 2558 | 4) CR3 must point to valid page tables that guarantee that the pages for\r | |
| 2559 | this function and the stack are identity mapped.\r | |
| 2560 | \r | |
| 2561 | @param EntryPoint A pointer to function to call with the new stack after\r | |
| 2562 | paging is disabled.\r | |
| 2563 | @param Context1 A pointer to the context to pass into the EntryPoint\r | |
| 2564 | function as the first parameter after paging is disabled.\r | |
| 2565 | @param Context2 A pointer to the context to pass into the EntryPoint\r | |
| 2566 | function as the second parameter after paging is\r | |
| 2567 | disabled.\r | |
| 2568 | @param NewStack A pointer to the new stack to use for the EntryPoint\r | |
| 2569 | function after paging is disabled.\r | |
| 2570 | \r | |
| 2571 | **/\r | |
| 2572 | VOID\r | |
| 2573 | EFIAPI\r | |
| 2574 | AsmDisablePaging32 (\r | |
| 2575 | IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r | |
| d0e2f823 MK |
2576 | IN VOID *Context1 OPTIONAL,\r |
| 2577 | IN VOID *Context2 OPTIONAL,\r | |
| 540fd45f MK |
2578 | IN VOID *NewStack\r |
| 2579 | )\r | |
| 2580 | {\r | |
| 2581 | gUnitTestHostBaseLib.X86->AsmDisablePaging32 (EntryPoint, Context1, Context2, NewStack);\r | |
| 2582 | }\r | |
| 2583 | \r | |
| 2584 | /**\r | |
| 2585 | Enables the 64-bit paging mode on the CPU.\r | |
| 2586 | \r | |
| 2587 | Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r | |
| 2588 | must be properly initialized prior to calling this service. This function\r | |
| 2589 | assumes the current execution mode is 32-bit protected mode with flat\r | |
| 2590 | descriptors. This function is only available on IA-32. After the 64-bit\r | |
| 2591 | paging mode is enabled, control is transferred to the function specified by\r | |
| 2592 | EntryPoint using the new stack specified by NewStack and passing in the\r | |
| 2593 | parameters specified by Context1 and Context2. Context1 and Context2 are\r | |
| 2594 | optional and may be 0. The function EntryPoint must never return.\r | |
| 2595 | \r | |
| 2596 | If the current execution mode is not 32-bit protected mode with flat\r | |
| 2597 | descriptors, then ASSERT().\r | |
| 2598 | If EntryPoint is 0, then ASSERT().\r | |
| 2599 | If NewStack is 0, then ASSERT().\r | |
| 2600 | \r | |
| 2601 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
| 2602 | is called. The descriptor in the GDT that this selector\r | |
| 2603 | references must be setup for long mode.\r | |
| 2604 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
| 2605 | the new stack after paging is enabled.\r | |
| 2606 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
| 2607 | the EntryPoint function as the first parameter after\r | |
| 2608 | paging is enabled.\r | |
| 2609 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
| 2610 | the EntryPoint function as the second parameter after\r | |
| 2611 | paging is enabled.\r | |
| 2612 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
| 2613 | the EntryPoint function after paging is enabled.\r | |
| 2614 | \r | |
| 2615 | **/\r | |
| 2616 | VOID\r | |
| 2617 | EFIAPI\r | |
| 2618 | AsmEnablePaging64 (\r | |
| 2619 | IN UINT16 Cs,\r | |
| 2620 | IN UINT64 EntryPoint,\r | |
| d0e2f823 MK |
2621 | IN UINT64 Context1 OPTIONAL,\r |
| 2622 | IN UINT64 Context2 OPTIONAL,\r | |
| 540fd45f MK |
2623 | IN UINT64 NewStack\r |
| 2624 | )\r | |
| 2625 | {\r | |
| 2626 | gUnitTestHostBaseLib.X86->AsmEnablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r | |
| 2627 | }\r | |
| 2628 | \r | |
| 2629 | /**\r | |
| 2630 | Disables the 64-bit paging mode on the CPU.\r | |
| 2631 | \r | |
| 2632 | Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r | |
| 2633 | mode. This function assumes the current execution mode is 64-paging mode.\r | |
| 2634 | This function is only available on x64. After the 64-bit paging mode is\r | |
| 2635 | disabled, control is transferred to the function specified by EntryPoint\r | |
| 2636 | using the new stack specified by NewStack and passing in the parameters\r | |
| 2637 | specified by Context1 and Context2. Context1 and Context2 are optional and\r | |
| 2638 | may be 0. The function EntryPoint must never return.\r | |
| 2639 | \r | |
| 2640 | If the current execution mode is not 64-bit paged mode, then ASSERT().\r | |
| 2641 | If EntryPoint is 0, then ASSERT().\r | |
| 2642 | If NewStack is 0, then ASSERT().\r | |
| 2643 | \r | |
| 2644 | @param Cs The 16-bit selector to load in the CS before EntryPoint\r | |
| 2645 | is called. The descriptor in the GDT that this selector\r | |
| 2646 | references must be setup for 32-bit protected mode.\r | |
| 2647 | @param EntryPoint The 64-bit virtual address of the function to call with\r | |
| 2648 | the new stack after paging is disabled.\r | |
| 2649 | @param Context1 The 64-bit virtual address of the context to pass into\r | |
| 2650 | the EntryPoint function as the first parameter after\r | |
| 2651 | paging is disabled.\r | |
| 2652 | @param Context2 The 64-bit virtual address of the context to pass into\r | |
| 2653 | the EntryPoint function as the second parameter after\r | |
| 2654 | paging is disabled.\r | |
| 2655 | @param NewStack The 64-bit virtual address of the new stack to use for\r | |
| 2656 | the EntryPoint function after paging is disabled.\r | |
| 2657 | \r | |
| 2658 | **/\r | |
| 2659 | VOID\r | |
| 2660 | EFIAPI\r | |
| 2661 | AsmDisablePaging64 (\r | |
| 2662 | IN UINT16 Cs,\r | |
| 2663 | IN UINT32 EntryPoint,\r | |
| d0e2f823 MK |
2664 | IN UINT32 Context1 OPTIONAL,\r |
| 2665 | IN UINT32 Context2 OPTIONAL,\r | |
| 540fd45f MK |
2666 | IN UINT32 NewStack\r |
| 2667 | )\r | |
| 2668 | {\r | |
| 2669 | gUnitTestHostBaseLib.X86->AsmDisablePaging64 (Cs, EntryPoint, Context1, Context2, NewStack);\r | |
| 2670 | }\r | |
| 2671 | \r | |
| 2672 | /**\r | |
| 2673 | Retrieves the properties for 16-bit thunk functions.\r | |
| 2674 | \r | |
| 2675 | Computes the size of the buffer and stack below 1MB required to use the\r | |
| 2676 | AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r | |
| 2677 | buffer size is returned in RealModeBufferSize, and the stack size is returned\r | |
| 2678 | in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r | |
| 2679 | then the actual minimum stack size is ExtraStackSize plus the maximum number\r | |
| 2680 | of bytes that need to be passed to the 16-bit real mode code.\r | |
| 2681 | \r | |
| 2682 | If RealModeBufferSize is NULL, then ASSERT().\r | |
| 2683 | If ExtraStackSize is NULL, then ASSERT().\r | |
| 2684 | \r | |
| 2685 | @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r | |
| 2686 | required to use the 16-bit thunk functions.\r | |
| 2687 | @param ExtraStackSize A pointer to the extra size of stack below 1MB\r | |
| 2688 | that the 16-bit thunk functions require for\r | |
| 2689 | temporary storage in the transition to and from\r | |
| 2690 | 16-bit real mode.\r | |
| 2691 | \r | |
| 2692 | **/\r | |
| 2693 | VOID\r | |
| 2694 | EFIAPI\r | |
| 2695 | AsmGetThunk16Properties (\r | |
| 2696 | OUT UINT32 *RealModeBufferSize,\r | |
| 2697 | OUT UINT32 *ExtraStackSize\r | |
| 2698 | )\r | |
| 2699 | {\r | |
| 2700 | gUnitTestHostBaseLib.X86->AsmGetThunk16Properties (RealModeBufferSize, ExtraStackSize);\r | |
| 2701 | }\r | |
| 2702 | \r | |
| 2703 | /**\r | |
| 2704 | Prepares all structures a code required to use AsmThunk16().\r | |
| 2705 | \r | |
| 2706 | Prepares all structures and code required to use AsmThunk16().\r | |
| 2707 | \r | |
| 2708 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 2709 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
| 2710 | \r | |
| 2711 | If ThunkContext is NULL, then ASSERT().\r | |
| 2712 | \r | |
| 2713 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 2714 | 16-bit real mode code to call.\r | |
| 2715 | \r | |
| 2716 | **/\r | |
| 2717 | VOID\r | |
| 2718 | EFIAPI\r | |
| 2719 | AsmPrepareThunk16 (\r | |
| 2720 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 2721 | )\r | |
| 2722 | {\r | |
| 2723 | gUnitTestHostBaseLib.X86->AsmPrepareThunk16 (ThunkContext);\r | |
| 2724 | }\r | |
| 2725 | \r | |
| 2726 | /**\r | |
| 2727 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
| 2728 | \r | |
| 2729 | Transfers control to a 16-bit real mode entry point and returns the results.\r | |
| 2730 | AsmPrepareThunk16() must be called with ThunkContext before this function is used.\r | |
| 2731 | This function must be called with interrupts disabled.\r | |
| 2732 | \r | |
| 2733 | The register state from the RealModeState field of ThunkContext is restored just prior\r | |
| 2734 | to calling the 16-bit real mode entry point. This includes the EFLAGS field of RealModeState,\r | |
| 2735 | which is used to set the interrupt state when a 16-bit real mode entry point is called.\r | |
| 2736 | Control is transferred to the 16-bit real mode entry point specified by the CS and Eip fields of RealModeState.\r | |
| 2737 | The stack is initialized to the SS and ESP fields of RealModeState. Any parameters passed to\r | |
| 2738 | the 16-bit real mode code must be populated by the caller at SS:ESP prior to calling this function.\r | |
| 2739 | The 16-bit real mode entry point is invoked with a 16-bit CALL FAR instruction,\r | |
| 2740 | so when accessing stack contents, the 16-bit real mode code must account for the 16-bit segment\r | |
| 2741 | and 16-bit offset of the return address that were pushed onto the stack. The 16-bit real mode entry\r | |
| 2742 | point must exit with a RETF instruction. The register state is captured into RealModeState immediately\r | |
| 2743 | after the RETF instruction is executed.\r | |
| 2744 | \r | |
| 2745 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
| 2746 | or any of the 16-bit real mode code makes a SW interrupt, then the caller is responsible for making sure\r | |
| 2747 | the IDT at address 0 is initialized to handle any HW or SW interrupts that may occur while in 16-bit real mode.\r | |
| 2748 | \r | |
| 2749 | If EFLAGS specifies interrupts enabled, or any of the 16-bit real mode code enables interrupts,\r | |
| 2750 | then the caller is responsible for making sure the 8259 PIC is in a state compatible with 16-bit real mode.\r | |
| 2751 | This includes the base vectors, the interrupt masks, and the edge/level trigger mode.\r | |
| 2752 | \r | |
| 2753 | If THUNK_ATTRIBUTE_BIG_REAL_MODE is set in the ThunkAttributes field of ThunkContext, then the user code\r | |
| 2754 | is invoked in big real mode. Otherwise, the user code is invoked in 16-bit real mode with 64KB segment limits.\r | |
| 2755 | \r | |
| 2756 | If neither THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 nor THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
| 2757 | ThunkAttributes, then it is assumed that the user code did not enable the A20 mask, and no attempt is made to\r | |
| 2758 | disable the A20 mask.\r | |
| 2759 | \r | |
| 2760 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is set and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is clear in\r | |
| 2761 | ThunkAttributes, then attempt to use the INT 15 service to disable the A20 mask. If this INT 15 call fails,\r | |
| 2762 | then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
| 2763 | \r | |
| 2764 | If THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 is clear and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL is set in\r | |
| 2765 | ThunkAttributes, then attempt to disable the A20 mask by directly accessing the 8042 keyboard controller I/O ports.\r | |
| 2766 | \r | |
| 2767 | If ThunkContext is NULL, then ASSERT().\r | |
| 2768 | If AsmPrepareThunk16() was not previously called with ThunkContext, then ASSERT().\r | |
| 2769 | If both THUNK_ATTRIBUTE_DISABLE_A20_MASK_INT_15 and THUNK_ATTRIBUTE_DISABLE_A20_MASK_KBD_CTRL are set in\r | |
| 2770 | ThunkAttributes, then ASSERT().\r | |
| 2771 | \r | |
| 2772 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 2773 | virtual to physical mappings for ThunkContext.RealModeBuffer are mapped 1:1.\r | |
| 2774 | \r | |
| 2775 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 2776 | 16-bit real mode code to call.\r | |
| 2777 | \r | |
| 2778 | **/\r | |
| 2779 | VOID\r | |
| 2780 | EFIAPI\r | |
| 2781 | AsmThunk16 (\r | |
| 2782 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 2783 | )\r | |
| 2784 | {\r | |
| 2785 | gUnitTestHostBaseLib.X86->AsmThunk16 (ThunkContext);\r | |
| 2786 | }\r | |
| 2787 | \r | |
| 2788 | /**\r | |
| 2789 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
| 2790 | control to a 16-bit real mode entry point, and returns the results.\r | |
| 2791 | \r | |
| 2792 | Prepares all structures and code for a 16-bit real mode thunk, transfers\r | |
| 2793 | control to a 16-bit real mode entry point, and returns the results. If the\r | |
| 2794 | caller only need to perform a single 16-bit real mode thunk, then this\r | |
| 2795 | service should be used. If the caller intends to make more than one 16-bit\r | |
| 2796 | real mode thunk, then it is more efficient if AsmPrepareThunk16() is called\r | |
| 2797 | once and AsmThunk16() can be called for each 16-bit real mode thunk.\r | |
| 2798 | \r | |
| 2799 | This interface is limited to be used in either physical mode or virtual modes with paging enabled where the\r | |
| 2800 | virtual to physical mappings for ThunkContext.RealModeBuffer is mapped 1:1.\r | |
| 2801 | \r | |
| 2802 | See AsmPrepareThunk16() and AsmThunk16() for the detailed description and ASSERT() conditions.\r | |
| 2803 | \r | |
| 2804 | @param ThunkContext A pointer to the context structure that describes the\r | |
| 2805 | 16-bit real mode code to call.\r | |
| 2806 | \r | |
| 2807 | **/\r | |
| 2808 | VOID\r | |
| 2809 | EFIAPI\r | |
| 2810 | AsmPrepareAndThunk16 (\r | |
| 2811 | IN OUT THUNK_CONTEXT *ThunkContext\r | |
| 2812 | )\r | |
| 2813 | {\r | |
| 2814 | gUnitTestHostBaseLib.X86->AsmPrepareAndThunk16 (ThunkContext);\r | |
| 2815 | }\r | |
| 2816 | \r | |
| 2817 | /**\r | |
| 2818 | Load given selector into TR register.\r | |
| 2819 | \r | |
| 2820 | @param[in] Selector Task segment selector\r | |
| 2821 | **/\r | |
| 2822 | VOID\r | |
| 2823 | EFIAPI\r | |
| 2824 | AsmWriteTr (\r | |
| 2825 | IN UINT16 Selector\r | |
| 2826 | )\r | |
| 2827 | {\r | |
| 2828 | gUnitTestHostBaseLib.X86->AsmWriteTr (Selector);\r | |
| 2829 | }\r | |
| 2830 | \r | |
| 2831 | /**\r | |
| 2832 | Performs a serializing operation on all load-from-memory instructions that\r | |
| 2833 | were issued prior the AsmLfence function.\r | |
| 2834 | \r | |
| 2835 | Executes a LFENCE instruction. This function is only available on IA-32 and x64.\r | |
| 2836 | \r | |
| 2837 | **/\r | |
| 2838 | VOID\r | |
| 2839 | EFIAPI\r | |
| 2840 | AsmLfence (\r | |
| 2841 | VOID\r | |
| 2842 | )\r | |
| 2843 | {\r | |
| 2844 | gUnitTestHostBaseLib.X86->AsmLfence ();\r | |
| 2845 | }\r | |
| 2846 | \r | |
| 2847 | /**\r | |
| 2848 | Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r | |
| 2849 | word, dword or qword operand is encoded at the end of the instruction's\r | |
| 2850 | binary representation.\r | |
| 2851 | \r | |
| 2852 | This function should be used to update object code that was compiled with\r | |
| 2853 | NASM from assembly source code. Example:\r | |
| 2854 | \r | |
| 2855 | NASM source code:\r | |
| 2856 | \r | |
| 2857 | mov eax, strict dword 0 ; the imm32 zero operand will be patched\r | |
| 2858 | ASM_PFX(gPatchCr3):\r | |
| 2859 | mov cr3, eax\r | |
| 2860 | \r | |
| 2861 | C source code:\r | |
| 2862 | \r | |
| 2863 | X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r | |
| 2864 | PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r | |
| 2865 | \r | |
| 2866 | @param[out] InstructionEnd Pointer right past the instruction to patch. The\r | |
| 2867 | immediate operand to patch is expected to\r | |
| 2868 | comprise the trailing bytes of the instruction.\r | |
| 2869 | If InstructionEnd is closer to address 0 than\r | |
| 2870 | ValueSize permits, then ASSERT().\r | |
| 2871 | \r | |
| 2872 | @param[in] PatchValue The constant to write to the immediate operand.\r | |
| 2873 | The caller is responsible for ensuring that\r | |
| 2874 | PatchValue can be represented in the byte, word,\r | |
| 2875 | dword or qword operand (as indicated through\r | |
| 2876 | ValueSize); otherwise ASSERT().\r | |
| 2877 | \r | |
| 2878 | @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r | |
| 2879 | 4, or 8. ASSERT() otherwise.\r | |
| 2880 | **/\r | |
| 2881 | VOID\r | |
| 2882 | EFIAPI\r | |
| 2883 | PatchInstructionX86 (\r | |
| 2884 | OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r | |
| 2885 | IN UINT64 PatchValue,\r | |
| 2886 | IN UINTN ValueSize\r | |
| 2887 | )\r | |
| 2888 | {\r | |
| 2889 | gUnitTestHostBaseLib.X86->PatchInstructionX86 (InstructionEnd, PatchValue, ValueSize);\r | |
| 2890 | }\r | |
| 2891 | \r | |
| 2892 | ///\r | |
| 2893 | /// Common services\r | |
| 2894 | ///\r | |
| 2895 | STATIC UNIT_TEST_HOST_BASE_LIB_COMMON mUnitTestHostBaseLibCommon = {\r | |
| 2896 | UnitTestHostBaseLibEnableInterrupts,\r | |
| 2897 | UnitTestHostBaseLibDisableInterrupts,\r | |
| 2898 | UnitTestHostBaseLibEnableDisableInterrupts,\r | |
| 2899 | UnitTestHostBaseLibGetInterruptState,\r | |
| 2900 | };\r | |
| 2901 | \r | |
| 2902 | ///\r | |
| 2903 | /// IA32/X64 services\r | |
| 2904 | ///\r | |
| 2905 | STATIC UNIT_TEST_HOST_BASE_LIB_X86 mUnitTestHostBaseLibX86 = {\r | |
| 2906 | UnitTestHostBaseLibAsmCpuid,\r | |
| 2907 | UnitTestHostBaseLibAsmCpuidEx,\r | |
| 2908 | UnitTestHostBaseLibAsmDisableCache,\r | |
| 2909 | UnitTestHostBaseLibAsmEnableCache,\r | |
| 2910 | UnitTestHostBaseLibAsmReadMsr64,\r | |
| 2911 | UnitTestHostBaseLibAsmWriteMsr64,\r | |
| 2912 | UnitTestHostBaseLibAsmReadCr0,\r | |
| 2913 | UnitTestHostBaseLibAsmReadCr2,\r | |
| 2914 | UnitTestHostBaseLibAsmReadCr3,\r | |
| 2915 | UnitTestHostBaseLibAsmReadCr4,\r | |
| 2916 | UnitTestHostBaseLibAsmWriteCr0,\r | |
| 2917 | UnitTestHostBaseLibAsmWriteCr2,\r | |
| 2918 | UnitTestHostBaseLibAsmWriteCr3,\r | |
| 2919 | UnitTestHostBaseLibAsmWriteCr4,\r | |
| 2920 | UnitTestHostBaseLibAsmReadDr0,\r | |
| 2921 | UnitTestHostBaseLibAsmReadDr1,\r | |
| 2922 | UnitTestHostBaseLibAsmReadDr2,\r | |
| 2923 | UnitTestHostBaseLibAsmReadDr3,\r | |
| 2924 | UnitTestHostBaseLibAsmReadDr4,\r | |
| 2925 | UnitTestHostBaseLibAsmReadDr5,\r | |
| 2926 | UnitTestHostBaseLibAsmReadDr6,\r | |
| 2927 | UnitTestHostBaseLibAsmReadDr7,\r | |
| 2928 | UnitTestHostBaseLibAsmWriteDr0,\r | |
| 2929 | UnitTestHostBaseLibAsmWriteDr1,\r | |
| 2930 | UnitTestHostBaseLibAsmWriteDr2,\r | |
| 2931 | UnitTestHostBaseLibAsmWriteDr3,\r | |
| 2932 | UnitTestHostBaseLibAsmWriteDr4,\r | |
| 2933 | UnitTestHostBaseLibAsmWriteDr5,\r | |
| 2934 | UnitTestHostBaseLibAsmWriteDr6,\r | |
| 2935 | UnitTestHostBaseLibAsmWriteDr7,\r | |
| 2936 | UnitTestHostBaseLibAsmReadCs,\r | |
| 2937 | UnitTestHostBaseLibAsmReadDs,\r | |
| 2938 | UnitTestHostBaseLibAsmReadEs,\r | |
| 2939 | UnitTestHostBaseLibAsmReadFs,\r | |
| 2940 | UnitTestHostBaseLibAsmReadGs,\r | |
| 2941 | UnitTestHostBaseLibAsmReadSs,\r | |
| 2942 | UnitTestHostBaseLibAsmReadTr,\r | |
| 2943 | UnitTestHostBaseLibAsmReadGdtr,\r | |
| 2944 | UnitTestHostBaseLibAsmWriteGdtr,\r | |
| 2945 | UnitTestHostBaseLibAsmReadIdtr,\r | |
| 2946 | UnitTestHostBaseLibAsmWriteIdtr,\r | |
| 2947 | UnitTestHostBaseLibAsmReadLdtr,\r | |
| 2948 | UnitTestHostBaseLibAsmWriteLdtr,\r | |
| 2949 | UnitTestHostBaseLibAsmReadPmc,\r | |
| 2950 | UnitTestHostBaseLibAsmMonitor,\r | |
| 2951 | UnitTestHostBaseLibAsmMwait,\r | |
| 2952 | UnitTestHostBaseLibAsmWbinvd,\r | |
| 2953 | UnitTestHostBaseLibAsmInvd,\r | |
| 2954 | UnitTestHostBaseLibAsmFlushCacheLine,\r | |
| 2955 | UnitTestHostBaseLibAsmEnablePaging32,\r | |
| 2956 | UnitTestHostBaseLibAsmDisablePaging32,\r | |
| 2957 | UnitTestHostBaseLibAsmEnablePaging64,\r | |
| 2958 | UnitTestHostBaseLibAsmDisablePaging64,\r | |
| 2959 | UnitTestHostBaseLibAsmGetThunk16Properties,\r | |
| 2960 | UnitTestHostBaseLibAsmPrepareThunk16,\r | |
| 2961 | UnitTestHostBaseLibAsmThunk16,\r | |
| 2962 | UnitTestHostBaseLibAsmPrepareAndThunk16,\r | |
| 2963 | UnitTestHostBaseLibAsmWriteTr,\r | |
| 2964 | UnitTestHostBaseLibAsmLfence,\r | |
| 2965 | UnitTestHostBaseLibPatchInstructionX86\r | |
| 2966 | };\r | |
| 2967 | \r | |
| 2968 | ///\r | |
| 2969 | /// Structure of hook functions for BaseLib functions that can not be used from\r | |
| 2970 | /// a host application. A simple emulation of these function is provided by\r | |
| 2971 | /// default. A specific unit test can provide its own implementation for any\r | |
| 2972 | /// of these functions.\r | |
| 2973 | ///\r | |
| 2974 | UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib = {\r | |
| 2975 | &mUnitTestHostBaseLibCommon,\r | |
| 2976 | &mUnitTestHostBaseLibX86\r | |
| 2977 | };\r |