| e1f414b6 |
1 | /** @file\r |
| 2 | PCI Library.\r |
| 3 | \r |
| 4 | Copyright (c) 2006, Intel Corporation<BR>\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| e1f414b6 |
13 | **/\r |
| 14 | \r |
| 15 | //\r |
| c7d265a9 |
16 | // The package level header files this module uses\r |
| e1f414b6 |
17 | //\r |
| c7d265a9 |
18 | #include <Base.h>\r |
| 19 | //\r |
| 20 | // The protocols, PPI and GUID defintions for this module\r |
| 21 | //\r |
| 22 | //\r |
| 23 | // The Library classes this module consumes\r |
| 24 | //\r |
| 25 | #include <Library/PciCf8Lib.h>\r |
| 26 | #include <Library/IoLib.h>\r |
| 27 | #include <Library/DebugLib.h>\r |
| e1f414b6 |
28 | \r |
| 29 | //\r |
| 30 | // Declare I/O Ports used to perform PCI Confguration Cycles\r |
| 31 | //\r |
| 32 | #define PCI_CONFIGURATION_ADDRESS_PORT 0xCF8\r |
| 33 | #define PCI_CONFIGURATION_DATA_PORT 0xCFC\r |
| 34 | \r |
| 35 | //\r |
| 36 | // Declare macro to convert PCI Library formatted address to CF8 formatted address\r |
| 37 | //\r |
| 38 | // PCI Library formatted address CF8 Formatted Address\r |
| 39 | // ============================= ======================\r |
| 40 | // Bits 00..11 Register Bits 00..07 Register\r |
| 41 | // Bits 12..14 Function Bits 08..10 Function\r |
| 42 | // Bits 15..19 Device Bits 11..15 Device\r |
| 43 | // Bits 20..27 Bus Bits 16..23 Bus\r |
| 44 | // Bits 28..31 Reserved(MBZ) Bits 24..30 Reserved(MBZ)\r |
| 45 | // Bits 31..31 Must be 1\r |
| 46 | //\r |
| 47 | \r |
| 48 | /**\r |
| 49 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r |
| 50 | only in the low 28 bits.\r |
| 51 | \r |
| 52 | @param A The address to validate.\r |
| 53 | @param M Additional bits to assert to be zero.\r |
| 54 | \r |
| 55 | **/\r |
| 56 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r |
| 57 | ASSERT (((A) & (~0xffff0ff | (M))) == 0)\r |
| 58 | \r |
| 59 | /**\r |
| 60 | Convert a PCI Express address to PCI CF8 address.\r |
| 61 | \r |
| 62 | @param A The address to convert.\r |
| 63 | \r |
| 64 | @retval The coverted address.\r |
| 65 | \r |
| 66 | **/\r |
| 67 | #define PCI_TO_CF8_ADDRESS(A) \\r |
| 68 | ((UINT32) ((((A) >> 4) & 0x00ffff00) | ((A) & 0xfc) | 0x80000000))\r |
| 69 | \r |
| 70 | /**\r |
| 71 | Reads an 8-bit PCI configuration register.\r |
| 72 | \r |
| 73 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 74 | This function must guarantee that all PCI read and write operations are\r |
| 75 | serialized.\r |
| 76 | \r |
| 77 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 78 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 79 | \r |
| 80 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 81 | Register.\r |
| 82 | \r |
| 83 | @return The read value from the PCI configuration register.\r |
| 84 | \r |
| 85 | **/\r |
| 86 | UINT8\r |
| 87 | EFIAPI\r |
| 88 | PciCf8Read8 (\r |
| 89 | IN UINTN Address\r |
| 90 | )\r |
| 91 | {\r |
| 92 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 93 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 94 | return IoRead8 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3));\r |
| 95 | }\r |
| 96 | \r |
| 97 | /**\r |
| 98 | Writes an 8-bit PCI configuration register.\r |
| 99 | \r |
| 100 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 101 | value specified by Value. Value is returned. This function must guarantee\r |
| 102 | that all PCI read and write operations are serialized.\r |
| 103 | \r |
| 104 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 105 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 106 | \r |
| 107 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 108 | Register.\r |
| 109 | @param Value The value to write.\r |
| 110 | \r |
| 111 | @return The value written to the PCI configuration register.\r |
| 112 | \r |
| 113 | **/\r |
| 114 | UINT8\r |
| 115 | EFIAPI\r |
| 116 | PciCf8Write8 (\r |
| 117 | IN UINTN Address,\r |
| 118 | IN UINT8 Value\r |
| 119 | )\r |
| 120 | {\r |
| 121 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 122 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 123 | return IoWrite8 (\r |
| 124 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 125 | Value\r |
| 126 | );\r |
| 127 | }\r |
| 128 | \r |
| 129 | /**\r |
| 130 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 131 | an 8-bit value.\r |
| 132 | \r |
| 133 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 134 | bitwise inclusive OR between the read result and the value specified by\r |
| 135 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 136 | specified by Address. The value written to the PCI configuration register is\r |
| 137 | returned. This function must guarantee that all PCI read and write operations\r |
| 138 | are serialized.\r |
| 139 | \r |
| 140 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 141 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 142 | \r |
| 143 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 144 | Register.\r |
| 145 | @param OrData The value to OR with the PCI configuration register.\r |
| 146 | \r |
| 147 | @return The value written back to the PCI configuration register.\r |
| 148 | \r |
| 149 | **/\r |
| 150 | UINT8\r |
| 151 | EFIAPI\r |
| 152 | PciCf8Or8 (\r |
| 153 | IN UINTN Address,\r |
| 154 | IN UINT8 OrData\r |
| 155 | )\r |
| 156 | {\r |
| 157 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 158 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 159 | return IoOr8 (\r |
| 160 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 161 | OrData\r |
| 162 | );\r |
| 163 | }\r |
| 164 | \r |
| 165 | /**\r |
| 166 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 167 | value.\r |
| 168 | \r |
| 169 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 170 | bitwise AND between the read result and the value specified by AndData, and\r |
| 171 | writes the result to the 8-bit PCI configuration register specified by\r |
| 172 | Address. The value written to the PCI configuration register is returned.\r |
| 173 | This function must guarantee that all PCI read and write operations are\r |
| 174 | serialized.\r |
| 175 | \r |
| 176 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 177 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 178 | \r |
| 179 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 180 | Register.\r |
| 181 | @param AndData The value to AND with the PCI configuration register.\r |
| 182 | \r |
| 183 | @return The value written back to the PCI configuration register.\r |
| 184 | \r |
| 185 | **/\r |
| 186 | UINT8\r |
| 187 | EFIAPI\r |
| 188 | PciCf8And8 (\r |
| 189 | IN UINTN Address,\r |
| 190 | IN UINT8 AndData\r |
| 191 | )\r |
| 192 | {\r |
| 193 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 194 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 195 | return IoAnd8 (\r |
| 196 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 197 | AndData\r |
| 198 | );\r |
| 199 | }\r |
| 200 | \r |
| 201 | /**\r |
| 202 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 203 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 204 | \r |
| 205 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 206 | bitwise AND between the read result and the value specified by AndData,\r |
| 207 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 208 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 209 | configuration register specified by Address. The value written to the PCI\r |
| 210 | configuration register is returned. This function must guarantee that all PCI\r |
| 211 | read and write operations are serialized.\r |
| 212 | \r |
| 213 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 214 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 215 | \r |
| 216 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 217 | Register.\r |
| 218 | @param AndData The value to AND with the PCI configuration register.\r |
| 219 | @param OrData The value to OR with the result of the AND operation.\r |
| 220 | \r |
| 221 | @return The value written back to the PCI configuration register.\r |
| 222 | \r |
| 223 | **/\r |
| 224 | UINT8\r |
| 225 | EFIAPI\r |
| 226 | PciCf8AndThenOr8 (\r |
| 227 | IN UINTN Address,\r |
| 228 | IN UINT8 AndData,\r |
| 229 | IN UINT8 OrData\r |
| 230 | )\r |
| 231 | {\r |
| 232 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 233 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 234 | return IoAndThenOr8 (\r |
| 235 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 236 | AndData,\r |
| 237 | OrData\r |
| 238 | );\r |
| 239 | }\r |
| 240 | \r |
| 241 | /**\r |
| 242 | Reads a bit field of a PCI configuration register.\r |
| 243 | \r |
| 244 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 245 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 246 | returned.\r |
| 247 | \r |
| 248 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 249 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 250 | If StartBit is greater than 7, then ASSERT().\r |
| 251 | If EndBit is greater than 7, then ASSERT().\r |
| 252 | If EndBit is less than StartBit, then ASSERT().\r |
| 253 | \r |
| 254 | @param Address PCI configuration register to read.\r |
| 255 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 256 | Range 0..7.\r |
| 257 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 258 | Range 0..7.\r |
| 259 | \r |
| 260 | @return The value of the bit field read from the PCI configuration register.\r |
| 261 | \r |
| 262 | **/\r |
| 263 | UINT8\r |
| 264 | EFIAPI\r |
| 265 | PciCf8BitFieldRead8 (\r |
| 266 | IN UINTN Address,\r |
| 267 | IN UINTN StartBit,\r |
| 268 | IN UINTN EndBit\r |
| 269 | )\r |
| 270 | {\r |
| 271 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 272 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 273 | return IoBitFieldRead8 (\r |
| 274 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 275 | StartBit,\r |
| 276 | EndBit\r |
| 277 | );\r |
| 278 | }\r |
| 279 | \r |
| 280 | /**\r |
| 281 | Writes a bit field to a PCI configuration register.\r |
| 282 | \r |
| 283 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 284 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 285 | destination PCI configuration register are preserved. The new value of the\r |
| 286 | 8-bit register is returned.\r |
| 287 | \r |
| 288 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 289 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 290 | If StartBit is greater than 7, then ASSERT().\r |
| 291 | If EndBit is greater than 7, then ASSERT().\r |
| 292 | If EndBit is less than StartBit, then ASSERT().\r |
| 293 | \r |
| 294 | @param Address PCI configuration register to write.\r |
| 295 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 296 | Range 0..7.\r |
| 297 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 298 | Range 0..7.\r |
| 299 | @param Value New value of the bit field.\r |
| 300 | \r |
| 301 | @return The value written back to the PCI configuration register.\r |
| 302 | \r |
| 303 | **/\r |
| 304 | UINT8\r |
| 305 | EFIAPI\r |
| 306 | PciCf8BitFieldWrite8 (\r |
| 307 | IN UINTN Address,\r |
| 308 | IN UINTN StartBit,\r |
| 309 | IN UINTN EndBit,\r |
| 310 | IN UINT8 Value\r |
| 311 | )\r |
| 312 | {\r |
| 313 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 314 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 315 | return IoBitFieldWrite8 (\r |
| 316 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 317 | StartBit,\r |
| 318 | EndBit,\r |
| 319 | Value\r |
| 320 | );\r |
| 321 | }\r |
| 322 | \r |
| 323 | /**\r |
| 324 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 325 | writes the result back to the bit field in the 8-bit port.\r |
| 326 | \r |
| 327 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 328 | bitwise inclusive OR between the read result and the value specified by\r |
| 329 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 330 | specified by Address. The value written to the PCI configuration register is\r |
| 331 | returned. This function must guarantee that all PCI read and write operations\r |
| 332 | are serialized. Extra left bits in OrData are stripped.\r |
| 333 | \r |
| 334 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 335 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 336 | If StartBit is greater than 7, then ASSERT().\r |
| 337 | If EndBit is greater than 7, then ASSERT().\r |
| 338 | If EndBit is less than StartBit, then ASSERT().\r |
| 339 | \r |
| 340 | @param Address PCI configuration register to write.\r |
| 341 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 342 | Range 0..7.\r |
| 343 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 344 | Range 0..7.\r |
| 345 | @param OrData The value to OR with the PCI configuration register.\r |
| 346 | \r |
| 347 | @return The value written back to the PCI configuration register.\r |
| 348 | \r |
| 349 | **/\r |
| 350 | UINT8\r |
| 351 | EFIAPI\r |
| 352 | PciCf8BitFieldOr8 (\r |
| 353 | IN UINTN Address,\r |
| 354 | IN UINTN StartBit,\r |
| 355 | IN UINTN EndBit,\r |
| 356 | IN UINT8 OrData\r |
| 357 | )\r |
| 358 | {\r |
| 359 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 360 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 361 | return IoBitFieldOr8 (\r |
| 362 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 363 | StartBit,\r |
| 364 | EndBit,\r |
| 365 | OrData\r |
| 366 | );\r |
| 367 | }\r |
| 368 | \r |
| 369 | /**\r |
| 370 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 371 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 372 | \r |
| 373 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 374 | bitwise AND between the read result and the value specified by AndData, and\r |
| 375 | writes the result to the 8-bit PCI configuration register specified by\r |
| 376 | Address. The value written to the PCI configuration register is returned.\r |
| 377 | This function must guarantee that all PCI read and write operations are\r |
| 378 | serialized. Extra left bits in AndData are stripped.\r |
| 379 | \r |
| 380 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 381 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 382 | If StartBit is greater than 7, then ASSERT().\r |
| 383 | If EndBit is greater than 7, then ASSERT().\r |
| 384 | If EndBit is less than StartBit, then ASSERT().\r |
| 385 | \r |
| 386 | @param Address PCI configuration register to write.\r |
| 387 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 388 | Range 0..7.\r |
| 389 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 390 | Range 0..7.\r |
| 391 | @param AndData The value to AND with the PCI configuration register.\r |
| 392 | \r |
| 393 | @return The value written back to the PCI configuration register.\r |
| 394 | \r |
| 395 | **/\r |
| 396 | UINT8\r |
| 397 | EFIAPI\r |
| 398 | PciCf8BitFieldAnd8 (\r |
| 399 | IN UINTN Address,\r |
| 400 | IN UINTN StartBit,\r |
| 401 | IN UINTN EndBit,\r |
| 402 | IN UINT8 AndData\r |
| 403 | )\r |
| 404 | {\r |
| 405 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 406 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 407 | return IoBitFieldAnd8 (\r |
| 408 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 409 | StartBit,\r |
| 410 | EndBit,\r |
| 411 | AndData\r |
| 412 | );\r |
| 413 | }\r |
| 414 | \r |
| 415 | /**\r |
| 416 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 417 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 418 | 8-bit port.\r |
| 419 | \r |
| 420 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 421 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 422 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 423 | configuration register specified by Address. The value written to the PCI\r |
| 424 | configuration register is returned. This function must guarantee that all PCI\r |
| 425 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 426 | OrData are stripped.\r |
| 427 | \r |
| 428 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 429 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 430 | If StartBit is greater than 7, then ASSERT().\r |
| 431 | If EndBit is greater than 7, then ASSERT().\r |
| 432 | If EndBit is less than StartBit, then ASSERT().\r |
| 433 | \r |
| 434 | @param Address PCI configuration register to write.\r |
| 435 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 436 | Range 0..7.\r |
| 437 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 438 | Range 0..7.\r |
| 439 | @param AndData The value to AND with the PCI configuration register.\r |
| 440 | @param OrData The value to OR with the result of the AND operation.\r |
| 441 | \r |
| 442 | @return The value written back to the PCI configuration register.\r |
| 443 | \r |
| 444 | **/\r |
| 445 | UINT8\r |
| 446 | EFIAPI\r |
| 447 | PciCf8BitFieldAndThenOr8(\r |
| 448 | IN UINTN Address,\r |
| 449 | IN UINTN StartBit,\r |
| 450 | IN UINTN EndBit,\r |
| 451 | IN UINT8 AndData,\r |
| 452 | IN UINT8 OrData\r |
| 453 | )\r |
| 454 | {\r |
| 455 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 456 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 457 | return IoBitFieldAndThenOr8 (\r |
| 458 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 3),\r |
| 459 | StartBit,\r |
| 460 | EndBit,\r |
| 461 | AndData,\r |
| 462 | OrData\r |
| 463 | );\r |
| 464 | }\r |
| 465 | \r |
| 466 | /**\r |
| 467 | Reads a 16-bit PCI configuration register.\r |
| 468 | \r |
| 469 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 470 | This function must guarantee that all PCI read and write operations are\r |
| 471 | serialized.\r |
| 472 | \r |
| 473 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 474 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 475 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 476 | \r |
| 477 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 478 | Register.\r |
| 479 | \r |
| 480 | @return The read value from the PCI configuration register.\r |
| 481 | \r |
| 482 | **/\r |
| 483 | UINT16\r |
| 484 | EFIAPI\r |
| 485 | PciCf8Read16 (\r |
| 486 | IN UINTN Address\r |
| 487 | )\r |
| 488 | {\r |
| 489 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 490 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 491 | return IoRead16 (PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2));\r |
| 492 | }\r |
| 493 | \r |
| 494 | /**\r |
| 495 | Writes a 16-bit PCI configuration register.\r |
| 496 | \r |
| 497 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 498 | value specified by Value. Value is returned. This function must guarantee\r |
| 499 | that all PCI read and write operations are serialized.\r |
| 500 | \r |
| 501 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 502 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 503 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 504 | \r |
| 505 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 506 | Register.\r |
| 507 | @param Value The value to write.\r |
| 508 | \r |
| 509 | @return The value written to the PCI configuration register.\r |
| 510 | \r |
| 511 | **/\r |
| 512 | UINT16\r |
| 513 | EFIAPI\r |
| 514 | PciCf8Write16 (\r |
| 515 | IN UINTN Address,\r |
| 516 | IN UINT16 Value\r |
| 517 | )\r |
| 518 | {\r |
| 519 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 520 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 521 | return IoWrite16 (\r |
| 522 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 523 | Value\r |
| 524 | );\r |
| 525 | }\r |
| 526 | \r |
| 527 | /**\r |
| 528 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 529 | a 16-bit value.\r |
| 530 | \r |
| 531 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 532 | bitwise inclusive OR between the read result and the value specified by\r |
| 533 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 534 | specified by Address. The value written to the PCI configuration register is\r |
| 535 | returned. This function must guarantee that all PCI read and write operations\r |
| 536 | are serialized.\r |
| 537 | \r |
| 538 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 539 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 540 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 541 | \r |
| 542 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 543 | Register.\r |
| 544 | @param OrData The value to OR with the PCI configuration register.\r |
| 545 | \r |
| 546 | @return The value written back to the PCI configuration register.\r |
| 547 | \r |
| 548 | **/\r |
| 549 | UINT16\r |
| 550 | EFIAPI\r |
| 551 | PciCf8Or16 (\r |
| 552 | IN UINTN Address,\r |
| 553 | IN UINT16 OrData\r |
| 554 | )\r |
| 555 | {\r |
| 556 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 557 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 558 | return IoOr16 (\r |
| 559 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 560 | OrData\r |
| 561 | );\r |
| 562 | }\r |
| 563 | \r |
| 564 | /**\r |
| 565 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 566 | value.\r |
| 567 | \r |
| 568 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 569 | bitwise AND between the read result and the value specified by AndData, and\r |
| 570 | writes the result to the 16-bit PCI configuration register specified by\r |
| 571 | Address. The value written to the PCI configuration register is returned.\r |
| 572 | This function must guarantee that all PCI read and write operations are\r |
| 573 | serialized.\r |
| 574 | \r |
| 575 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 576 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 577 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 578 | \r |
| 579 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 580 | Register.\r |
| 581 | @param AndData The value to AND with the PCI configuration register.\r |
| 582 | \r |
| 583 | @return The value written back to the PCI configuration register.\r |
| 584 | \r |
| 585 | **/\r |
| 586 | UINT16\r |
| 587 | EFIAPI\r |
| 588 | PciCf8And16 (\r |
| 589 | IN UINTN Address,\r |
| 590 | IN UINT16 AndData\r |
| 591 | )\r |
| 592 | {\r |
| 593 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 594 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 595 | return IoAnd16 (\r |
| 596 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 597 | AndData\r |
| 598 | );\r |
| 599 | }\r |
| 600 | \r |
| 601 | /**\r |
| 602 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 603 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 604 | \r |
| 605 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 606 | bitwise AND between the read result and the value specified by AndData,\r |
| 607 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 608 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 609 | configuration register specified by Address. The value written to the PCI\r |
| 610 | configuration register is returned. This function must guarantee that all PCI\r |
| 611 | read and write operations are serialized.\r |
| 612 | \r |
| 613 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 614 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 615 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 616 | \r |
| 617 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 618 | Register.\r |
| 619 | @param AndData The value to AND with the PCI configuration register.\r |
| 620 | @param OrData The value to OR with the result of the AND operation.\r |
| 621 | \r |
| 622 | @return The value written back to the PCI configuration register.\r |
| 623 | \r |
| 624 | **/\r |
| 625 | UINT16\r |
| 626 | EFIAPI\r |
| 627 | PciCf8AndThenOr16 (\r |
| 628 | IN UINTN Address,\r |
| 629 | IN UINT16 AndData,\r |
| 630 | IN UINT16 OrData\r |
| 631 | )\r |
| 632 | {\r |
| 633 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 634 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 635 | return IoAndThenOr16 (\r |
| 636 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 637 | AndData,\r |
| 638 | OrData\r |
| 639 | );\r |
| 640 | }\r |
| 641 | \r |
| 642 | /**\r |
| 643 | Reads a bit field of a PCI configuration register.\r |
| 644 | \r |
| 645 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 646 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 647 | returned.\r |
| 648 | \r |
| 649 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 650 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 651 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 652 | If StartBit is greater than 15, then ASSERT().\r |
| 653 | If EndBit is greater than 15, then ASSERT().\r |
| 654 | If EndBit is less than StartBit, then ASSERT().\r |
| 655 | \r |
| 656 | @param Address PCI configuration register to read.\r |
| 657 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 658 | Range 0..15.\r |
| 659 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 660 | Range 0..15.\r |
| 661 | \r |
| 662 | @return The value of the bit field read from the PCI configuration register.\r |
| 663 | \r |
| 664 | **/\r |
| 665 | UINT16\r |
| 666 | EFIAPI\r |
| 667 | PciCf8BitFieldRead16 (\r |
| 668 | IN UINTN Address,\r |
| 669 | IN UINTN StartBit,\r |
| 670 | IN UINTN EndBit\r |
| 671 | )\r |
| 672 | {\r |
| 673 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 674 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 675 | return IoBitFieldRead16 (\r |
| 676 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 677 | StartBit,\r |
| 678 | EndBit\r |
| 679 | );\r |
| 680 | }\r |
| 681 | \r |
| 682 | /**\r |
| 683 | Writes a bit field to a PCI configuration register.\r |
| 684 | \r |
| 685 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 686 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 687 | destination PCI configuration register are preserved. The new value of the\r |
| 688 | 16-bit register is returned.\r |
| 689 | \r |
| 690 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 691 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 692 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 693 | If StartBit is greater than 15, then ASSERT().\r |
| 694 | If EndBit is greater than 15, then ASSERT().\r |
| 695 | If EndBit is less than StartBit, then ASSERT().\r |
| 696 | \r |
| 697 | @param Address PCI configuration register to write.\r |
| 698 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 699 | Range 0..15.\r |
| 700 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 701 | Range 0..15.\r |
| 702 | @param Value New value of the bit field.\r |
| 703 | \r |
| 704 | @return The value written back to the PCI configuration register.\r |
| 705 | \r |
| 706 | **/\r |
| 707 | UINT16\r |
| 708 | EFIAPI\r |
| 709 | PciCf8BitFieldWrite16 (\r |
| 710 | IN UINTN Address,\r |
| 711 | IN UINTN StartBit,\r |
| 712 | IN UINTN EndBit,\r |
| 713 | IN UINT16 Value\r |
| 714 | )\r |
| 715 | {\r |
| 716 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 717 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 718 | return IoBitFieldWrite16 (\r |
| 719 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 720 | StartBit,\r |
| 721 | EndBit,\r |
| 722 | Value\r |
| 723 | );\r |
| 724 | }\r |
| 725 | \r |
| 726 | /**\r |
| 727 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 728 | writes the result back to the bit field in the 16-bit port.\r |
| 729 | \r |
| 730 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 731 | bitwise inclusive OR between the read result and the value specified by\r |
| 732 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 733 | specified by Address. The value written to the PCI configuration register is\r |
| 734 | returned. This function must guarantee that all PCI read and write operations\r |
| 735 | are serialized. Extra left bits in OrData are stripped.\r |
| 736 | \r |
| 737 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 738 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 739 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 740 | If StartBit is greater than 15, then ASSERT().\r |
| 741 | If EndBit is greater than 15, then ASSERT().\r |
| 742 | If EndBit is less than StartBit, then ASSERT().\r |
| 743 | \r |
| 744 | @param Address PCI configuration register to write.\r |
| 745 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 746 | Range 0..15.\r |
| 747 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 748 | Range 0..15.\r |
| 749 | @param OrData The value to OR with the PCI configuration register.\r |
| 750 | \r |
| 751 | @return The value written back to the PCI configuration register.\r |
| 752 | \r |
| 753 | **/\r |
| 754 | UINT16\r |
| 755 | EFIAPI\r |
| 756 | PciCf8BitFieldOr16 (\r |
| 757 | IN UINTN Address,\r |
| 758 | IN UINTN StartBit,\r |
| 759 | IN UINTN EndBit,\r |
| 760 | IN UINT16 OrData\r |
| 761 | )\r |
| 762 | {\r |
| 763 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 764 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 765 | return IoBitFieldOr16 (\r |
| 766 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 767 | StartBit,\r |
| 768 | EndBit,\r |
| 769 | OrData\r |
| 770 | );\r |
| 771 | }\r |
| 772 | \r |
| 773 | /**\r |
| 774 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 775 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 776 | \r |
| 777 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 778 | bitwise AND between the read result and the value specified by AndData, and\r |
| 779 | writes the result to the 16-bit PCI configuration register specified by\r |
| 780 | Address. The value written to the PCI configuration register is returned.\r |
| 781 | This function must guarantee that all PCI read and write operations are\r |
| 782 | serialized. Extra left bits in AndData are stripped.\r |
| 783 | \r |
| 784 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 785 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 786 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 787 | If StartBit is greater than 15, then ASSERT().\r |
| 788 | If EndBit is greater than 15, then ASSERT().\r |
| 789 | If EndBit is less than StartBit, then ASSERT().\r |
| 790 | \r |
| 791 | @param Address PCI configuration register to write.\r |
| 792 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 793 | Range 0..15.\r |
| 794 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 795 | Range 0..15.\r |
| 796 | @param AndData The value to AND with the PCI configuration register.\r |
| 797 | \r |
| 798 | @return The value written back to the PCI configuration register.\r |
| 799 | \r |
| 800 | **/\r |
| 801 | UINT16\r |
| 802 | EFIAPI\r |
| 803 | PciCf8BitFieldAnd16 (\r |
| 804 | IN UINTN Address,\r |
| 805 | IN UINTN StartBit,\r |
| 806 | IN UINTN EndBit,\r |
| 807 | IN UINT16 AndData\r |
| 808 | )\r |
| 809 | {\r |
| 810 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 811 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 812 | return IoBitFieldAnd16 (\r |
| 813 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 814 | StartBit,\r |
| 815 | EndBit,\r |
| 816 | AndData\r |
| 817 | );\r |
| 818 | }\r |
| 819 | \r |
| 820 | /**\r |
| 821 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 822 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 823 | 16-bit port.\r |
| 824 | \r |
| 825 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 826 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 827 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 828 | configuration register specified by Address. The value written to the PCI\r |
| 829 | configuration register is returned. This function must guarantee that all PCI\r |
| 830 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 831 | OrData are stripped.\r |
| 832 | \r |
| 833 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 834 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 835 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 836 | If StartBit is greater than 15, then ASSERT().\r |
| 837 | If EndBit is greater than 15, then ASSERT().\r |
| 838 | If EndBit is less than StartBit, then ASSERT().\r |
| 839 | \r |
| 840 | @param Address PCI configuration register to write.\r |
| 841 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 842 | Range 0..15.\r |
| 843 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 844 | Range 0..15.\r |
| 845 | @param AndData The value to AND with the PCI configuration register.\r |
| 846 | @param OrData The value to OR with the result of the AND operation.\r |
| 847 | \r |
| 848 | @return The value written back to the PCI configuration register.\r |
| 849 | \r |
| 850 | **/\r |
| 851 | UINT16\r |
| 852 | EFIAPI\r |
| 853 | PciCf8BitFieldAndThenOr16(\r |
| 854 | IN UINTN Address,\r |
| 855 | IN UINTN StartBit,\r |
| 856 | IN UINTN EndBit,\r |
| 857 | IN UINT16 AndData,\r |
| 858 | IN UINT16 OrData\r |
| 859 | )\r |
| 860 | {\r |
| 861 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 862 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 863 | return IoBitFieldAndThenOr16 (\r |
| 864 | PCI_CONFIGURATION_DATA_PORT + (UINT16)(Address & 2),\r |
| 865 | StartBit,\r |
| 866 | EndBit,\r |
| 867 | AndData,\r |
| 868 | OrData\r |
| 869 | );\r |
| 870 | }\r |
| 871 | \r |
| 872 | /**\r |
| 873 | Reads a 32-bit PCI configuration register.\r |
| 874 | \r |
| 875 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 876 | This function must guarantee that all PCI read and write operations are\r |
| 877 | serialized.\r |
| 878 | \r |
| 879 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 880 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 881 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 882 | \r |
| 883 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 884 | Register.\r |
| 885 | \r |
| 886 | @return The read value from the PCI configuration register.\r |
| 887 | \r |
| 888 | **/\r |
| 889 | UINT32\r |
| 890 | EFIAPI\r |
| 891 | PciCf8Read32 (\r |
| 892 | IN UINTN Address\r |
| 893 | )\r |
| 894 | {\r |
| 895 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 896 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 897 | return IoRead32 (PCI_CONFIGURATION_DATA_PORT);\r |
| 898 | }\r |
| 899 | \r |
| 900 | /**\r |
| 901 | Writes a 32-bit PCI configuration register.\r |
| 902 | \r |
| 903 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 904 | value specified by Value. Value is returned. This function must guarantee\r |
| 905 | that all PCI read and write operations are serialized.\r |
| 906 | \r |
| 907 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 908 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 909 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 910 | \r |
| 911 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 912 | Register.\r |
| 913 | @param Value The value to write.\r |
| 914 | \r |
| 915 | @return The value written to the PCI configuration register.\r |
| 916 | \r |
| 917 | **/\r |
| 918 | UINT32\r |
| 919 | EFIAPI\r |
| 920 | PciCf8Write32 (\r |
| 921 | IN UINTN Address,\r |
| 922 | IN UINT32 Value\r |
| 923 | )\r |
| 924 | {\r |
| 925 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 926 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 927 | return IoWrite32 (\r |
| 928 | PCI_CONFIGURATION_DATA_PORT,\r |
| 929 | Value\r |
| 930 | );\r |
| 931 | }\r |
| 932 | \r |
| 933 | /**\r |
| 934 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 935 | a 32-bit value.\r |
| 936 | \r |
| 937 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 938 | bitwise inclusive OR between the read result and the value specified by\r |
| 939 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 940 | specified by Address. The value written to the PCI configuration register is\r |
| 941 | returned. This function must guarantee that all PCI read and write operations\r |
| 942 | are serialized.\r |
| 943 | \r |
| 944 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 945 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 946 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 947 | \r |
| 948 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 949 | Register.\r |
| 950 | @param OrData The value to OR with the PCI configuration register.\r |
| 951 | \r |
| 952 | @return The value written back to the PCI configuration register.\r |
| 953 | \r |
| 954 | **/\r |
| 955 | UINT32\r |
| 956 | EFIAPI\r |
| 957 | PciCf8Or32 (\r |
| 958 | IN UINTN Address,\r |
| 959 | IN UINT32 OrData\r |
| 960 | )\r |
| 961 | {\r |
| 962 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 963 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 964 | return IoOr32 (\r |
| 965 | PCI_CONFIGURATION_DATA_PORT,\r |
| 966 | OrData\r |
| 967 | );\r |
| 968 | }\r |
| 969 | \r |
| 970 | /**\r |
| 971 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 972 | value.\r |
| 973 | \r |
| 974 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 975 | bitwise AND between the read result and the value specified by AndData, and\r |
| 976 | writes the result to the 32-bit PCI configuration register specified by\r |
| 977 | Address. The value written to the PCI configuration register is returned.\r |
| 978 | This function must guarantee that all PCI read and write operations are\r |
| 979 | serialized.\r |
| 980 | \r |
| 981 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 982 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 983 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 984 | \r |
| 985 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 986 | Register.\r |
| 987 | @param AndData The value to AND with the PCI configuration register.\r |
| 988 | \r |
| 989 | @return The value written back to the PCI configuration register.\r |
| 990 | \r |
| 991 | **/\r |
| 992 | UINT32\r |
| 993 | EFIAPI\r |
| 994 | PciCf8And32 (\r |
| 995 | IN UINTN Address,\r |
| 996 | IN UINT32 AndData\r |
| 997 | )\r |
| 998 | {\r |
| 999 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1000 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1001 | return IoAnd32 (\r |
| 1002 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1003 | AndData\r |
| 1004 | );\r |
| 1005 | }\r |
| 1006 | \r |
| 1007 | /**\r |
| 1008 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 1009 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 1010 | \r |
| 1011 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1012 | bitwise AND between the read result and the value specified by AndData,\r |
| 1013 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 1014 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 1015 | configuration register specified by Address. The value written to the PCI\r |
| 1016 | configuration register is returned. This function must guarantee that all PCI\r |
| 1017 | read and write operations are serialized.\r |
| 1018 | \r |
| 1019 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1020 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1021 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1022 | \r |
| 1023 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1024 | Register.\r |
| 1025 | @param AndData The value to AND with the PCI configuration register.\r |
| 1026 | @param OrData The value to OR with the result of the AND operation.\r |
| 1027 | \r |
| 1028 | @return The value written back to the PCI configuration register.\r |
| 1029 | \r |
| 1030 | **/\r |
| 1031 | UINT32\r |
| 1032 | EFIAPI\r |
| 1033 | PciCf8AndThenOr32 (\r |
| 1034 | IN UINTN Address,\r |
| 1035 | IN UINT32 AndData,\r |
| 1036 | IN UINT32 OrData\r |
| 1037 | )\r |
| 1038 | {\r |
| 1039 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1040 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1041 | return IoAndThenOr32 (\r |
| 1042 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1043 | AndData,\r |
| 1044 | OrData\r |
| 1045 | );\r |
| 1046 | }\r |
| 1047 | \r |
| 1048 | /**\r |
| 1049 | Reads a bit field of a PCI configuration register.\r |
| 1050 | \r |
| 1051 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 1052 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 1053 | returned.\r |
| 1054 | \r |
| 1055 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1056 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1057 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1058 | If StartBit is greater than 31, then ASSERT().\r |
| 1059 | If EndBit is greater than 31, then ASSERT().\r |
| 1060 | If EndBit is less than StartBit, then ASSERT().\r |
| 1061 | \r |
| 1062 | @param Address PCI configuration register to read.\r |
| 1063 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1064 | Range 0..31.\r |
| 1065 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1066 | Range 0..31.\r |
| 1067 | \r |
| 1068 | @return The value of the bit field read from the PCI configuration register.\r |
| 1069 | \r |
| 1070 | **/\r |
| 1071 | UINT32\r |
| 1072 | EFIAPI\r |
| 1073 | PciCf8BitFieldRead32 (\r |
| 1074 | IN UINTN Address,\r |
| 1075 | IN UINTN StartBit,\r |
| 1076 | IN UINTN EndBit\r |
| 1077 | )\r |
| 1078 | {\r |
| 1079 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1080 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1081 | return IoBitFieldRead32 (\r |
| 1082 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1083 | StartBit,\r |
| 1084 | EndBit\r |
| 1085 | );\r |
| 1086 | }\r |
| 1087 | \r |
| 1088 | /**\r |
| 1089 | Writes a bit field to a PCI configuration register.\r |
| 1090 | \r |
| 1091 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 1092 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 1093 | destination PCI configuration register are preserved. The new value of the\r |
| 1094 | 32-bit register is returned.\r |
| 1095 | \r |
| 1096 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1097 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1098 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1099 | If StartBit is greater than 31, then ASSERT().\r |
| 1100 | If EndBit is greater than 31, then ASSERT().\r |
| 1101 | If EndBit is less than StartBit, then ASSERT().\r |
| 1102 | \r |
| 1103 | @param Address PCI configuration register to write.\r |
| 1104 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1105 | Range 0..31.\r |
| 1106 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1107 | Range 0..31.\r |
| 1108 | @param Value New value of the bit field.\r |
| 1109 | \r |
| 1110 | @return The value written back to the PCI configuration register.\r |
| 1111 | \r |
| 1112 | **/\r |
| 1113 | UINT32\r |
| 1114 | EFIAPI\r |
| 1115 | PciCf8BitFieldWrite32 (\r |
| 1116 | IN UINTN Address,\r |
| 1117 | IN UINTN StartBit,\r |
| 1118 | IN UINTN EndBit,\r |
| 1119 | IN UINT32 Value\r |
| 1120 | )\r |
| 1121 | {\r |
| 1122 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1123 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1124 | return IoBitFieldWrite32 (\r |
| 1125 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1126 | StartBit,\r |
| 1127 | EndBit,\r |
| 1128 | Value\r |
| 1129 | );\r |
| 1130 | }\r |
| 1131 | \r |
| 1132 | /**\r |
| 1133 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 1134 | writes the result back to the bit field in the 32-bit port.\r |
| 1135 | \r |
| 1136 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1137 | bitwise inclusive OR between the read result and the value specified by\r |
| 1138 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 1139 | specified by Address. The value written to the PCI configuration register is\r |
| 1140 | returned. This function must guarantee that all PCI read and write operations\r |
| 1141 | are serialized. Extra left bits in OrData are stripped.\r |
| 1142 | \r |
| 1143 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1144 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1145 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1146 | If StartBit is greater than 31, then ASSERT().\r |
| 1147 | If EndBit is greater than 31, then ASSERT().\r |
| 1148 | If EndBit is less than StartBit, then ASSERT().\r |
| 1149 | \r |
| 1150 | @param Address PCI configuration register to write.\r |
| 1151 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1152 | Range 0..31.\r |
| 1153 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1154 | Range 0..31.\r |
| 1155 | @param OrData The value to OR with the PCI configuration register.\r |
| 1156 | \r |
| 1157 | @return The value written back to the PCI configuration register.\r |
| 1158 | \r |
| 1159 | **/\r |
| 1160 | UINT32\r |
| 1161 | EFIAPI\r |
| 1162 | PciCf8BitFieldOr32 (\r |
| 1163 | IN UINTN Address,\r |
| 1164 | IN UINTN StartBit,\r |
| 1165 | IN UINTN EndBit,\r |
| 1166 | IN UINT32 OrData\r |
| 1167 | )\r |
| 1168 | {\r |
| 1169 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1170 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1171 | return IoBitFieldOr32 (\r |
| 1172 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1173 | StartBit,\r |
| 1174 | EndBit,\r |
| 1175 | OrData\r |
| 1176 | );\r |
| 1177 | }\r |
| 1178 | \r |
| 1179 | /**\r |
| 1180 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 1181 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 1182 | \r |
| 1183 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1184 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1185 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1186 | Address. The value written to the PCI configuration register is returned.\r |
| 1187 | This function must guarantee that all PCI read and write operations are\r |
| 1188 | serialized. Extra left bits in AndData are stripped.\r |
| 1189 | \r |
| 1190 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1191 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1192 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1193 | If StartBit is greater than 31, then ASSERT().\r |
| 1194 | If EndBit is greater than 31, then ASSERT().\r |
| 1195 | If EndBit is less than StartBit, then ASSERT().\r |
| 1196 | \r |
| 1197 | @param Address PCI configuration register to write.\r |
| 1198 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1199 | Range 0..31.\r |
| 1200 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1201 | Range 0..31.\r |
| 1202 | @param AndData The value to AND with the PCI configuration register.\r |
| 1203 | \r |
| 1204 | @return The value written back to the PCI configuration register.\r |
| 1205 | \r |
| 1206 | **/\r |
| 1207 | UINT32\r |
| 1208 | EFIAPI\r |
| 1209 | PciCf8BitFieldAnd32 (\r |
| 1210 | IN UINTN Address,\r |
| 1211 | IN UINTN StartBit,\r |
| 1212 | IN UINTN EndBit,\r |
| 1213 | IN UINT32 AndData\r |
| 1214 | )\r |
| 1215 | {\r |
| 1216 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1217 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1218 | return IoBitFieldAnd32 (\r |
| 1219 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1220 | StartBit,\r |
| 1221 | EndBit,\r |
| 1222 | AndData\r |
| 1223 | );\r |
| 1224 | }\r |
| 1225 | \r |
| 1226 | /**\r |
| 1227 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 1228 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 1229 | 32-bit port.\r |
| 1230 | \r |
| 1231 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1232 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 1233 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 1234 | configuration register specified by Address. The value written to the PCI\r |
| 1235 | configuration register is returned. This function must guarantee that all PCI\r |
| 1236 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1237 | OrData are stripped.\r |
| 1238 | \r |
| 1239 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1240 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1241 | If the register specified by Address >= 0x100, then ASSERT().\r |
| 1242 | If StartBit is greater than 31, then ASSERT().\r |
| 1243 | If EndBit is greater than 31, then ASSERT().\r |
| 1244 | If EndBit is less than StartBit, then ASSERT().\r |
| 1245 | \r |
| 1246 | @param Address PCI configuration register to write.\r |
| 1247 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1248 | Range 0..31.\r |
| 1249 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1250 | Range 0..31.\r |
| 1251 | @param AndData The value to AND with the PCI configuration register.\r |
| 1252 | @param OrData The value to OR with the result of the AND operation.\r |
| 1253 | \r |
| 1254 | @return The value written back to the PCI configuration register.\r |
| 1255 | \r |
| 1256 | **/\r |
| 1257 | UINT32\r |
| 1258 | EFIAPI\r |
| 1259 | PciCf8BitFieldAndThenOr32(\r |
| 1260 | IN UINTN Address,\r |
| 1261 | IN UINTN StartBit,\r |
| 1262 | IN UINTN EndBit,\r |
| 1263 | IN UINT32 AndData,\r |
| 1264 | IN UINT32 OrData\r |
| 1265 | )\r |
| 1266 | {\r |
| 1267 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 1268 | IoWrite32 (PCI_CONFIGURATION_ADDRESS_PORT, PCI_TO_CF8_ADDRESS (Address));\r |
| 1269 | return IoBitFieldAndThenOr32 (\r |
| 1270 | PCI_CONFIGURATION_DATA_PORT,\r |
| 1271 | StartBit,\r |
| 1272 | EndBit,\r |
| 1273 | AndData,\r |
| 1274 | OrData\r |
| 1275 | );\r |
| 1276 | }\r |
| 1277 | \r |
| 1278 | /**\r |
| 1279 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1280 | \r |
| 1281 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1282 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1283 | configuration registers from a single PCI function to be read. Size is\r |
| 1284 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1285 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1286 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1287 | end of the range.\r |
| 1288 | \r |
| 1289 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1290 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1291 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1292 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1293 | \r |
| 1294 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1295 | Function and Register.\r |
| 1296 | @param Size Size in bytes of the transfer.\r |
| 1297 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1298 | \r |
| 1299 | @return Size\r |
| 1300 | \r |
| 1301 | **/\r |
| 1302 | UINTN\r |
| 1303 | EFIAPI\r |
| 1304 | PciCf8ReadBuffer (\r |
| 1305 | IN UINTN StartAddress,\r |
| 1306 | IN UINTN Size,\r |
| 1307 | OUT VOID *Buffer\r |
| 1308 | )\r |
| 1309 | {\r |
| 1310 | UINTN ReturnValue;\r |
| 1311 | \r |
| 1312 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r |
| 1313 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r |
| 1314 | \r |
| 1315 | if (Size == 0) {\r |
| 1316 | return Size;\r |
| 1317 | }\r |
| 1318 | \r |
| 1319 | ASSERT (Buffer != NULL);\r |
| 1320 | \r |
| 1321 | //\r |
| 1322 | // Save Size for return\r |
| 1323 | //\r |
| 1324 | ReturnValue = Size;\r |
| 1325 | \r |
| 1326 | if ((StartAddress & 1) != 0) {\r |
| 1327 | //\r |
| 1328 | // Read a byte if StartAddress is byte aligned\r |
| 1329 | //\r |
| 1330 | *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);\r |
| 1331 | StartAddress += sizeof (UINT8);\r |
| 1332 | Size -= sizeof (UINT8);\r |
| 1333 | Buffer = (UINT8*)Buffer + 1;\r |
| 1334 | }\r |
| 1335 | \r |
| 1336 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1337 | //\r |
| 1338 | // Read a word if StartAddress is word aligned\r |
| 1339 | //\r |
| 1340 | *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);\r |
| 1341 | StartAddress += sizeof (UINT16);\r |
| 1342 | Size -= sizeof (UINT16);\r |
| 1343 | Buffer = (UINT16*)Buffer + 1;\r |
| 1344 | }\r |
| 1345 | \r |
| 1346 | while (Size >= sizeof (UINT32)) {\r |
| 1347 | //\r |
| 1348 | // Read as many double words as possible\r |
| 1349 | //\r |
| 1350 | *(volatile UINT32 *)Buffer = PciCf8Read32 (StartAddress);\r |
| 1351 | StartAddress += sizeof (UINT32);\r |
| 1352 | Size -= sizeof (UINT32);\r |
| 1353 | Buffer = (UINT32*)Buffer + 1;\r |
| 1354 | }\r |
| 1355 | \r |
| 1356 | if (Size >= sizeof (UINT16)) {\r |
| 1357 | //\r |
| 1358 | // Read the last remaining word if exist\r |
| 1359 | //\r |
| 1360 | *(volatile UINT16 *)Buffer = PciCf8Read16 (StartAddress);\r |
| 1361 | StartAddress += sizeof (UINT16);\r |
| 1362 | Size -= sizeof (UINT16);\r |
| 1363 | Buffer = (UINT16*)Buffer + 1;\r |
| 1364 | }\r |
| 1365 | \r |
| 1366 | if (Size >= sizeof (UINT8)) {\r |
| 1367 | //\r |
| 1368 | // Read the last remaining byte if exist\r |
| 1369 | //\r |
| 1370 | *(volatile UINT8 *)Buffer = PciCf8Read8 (StartAddress);\r |
| 1371 | }\r |
| 1372 | \r |
| 1373 | return ReturnValue;\r |
| 1374 | }\r |
| 1375 | \r |
| 1376 | /**\r |
| 1377 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1378 | configuration space.\r |
| 1379 | \r |
| 1380 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1381 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1382 | configuration registers from a single PCI function to be written. Size is\r |
| 1383 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1384 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1385 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1386 | and the end of the range.\r |
| 1387 | \r |
| 1388 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1389 | If the register specified by StartAddress >= 0x100, then ASSERT().\r |
| 1390 | If ((StartAddress & 0xFFF) + Size) > 0x100, then ASSERT().\r |
| 1391 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1392 | \r |
| 1393 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1394 | Function and Register.\r |
| 1395 | @param Size Size in bytes of the transfer.\r |
| 1396 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1397 | \r |
| 1398 | @return Size\r |
| 1399 | \r |
| 1400 | **/\r |
| 1401 | UINTN\r |
| 1402 | EFIAPI\r |
| 1403 | PciCf8WriteBuffer (\r |
| 1404 | IN UINTN StartAddress,\r |
| 1405 | IN UINTN Size,\r |
| 1406 | IN VOID *Buffer\r |
| 1407 | )\r |
| 1408 | {\r |
| 1409 | UINTN ReturnValue;\r |
| 1410 | \r |
| 1411 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r |
| 1412 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x100);\r |
| 1413 | \r |
| 1414 | if (Size == 0) {\r |
| 1415 | return 0;\r |
| 1416 | }\r |
| 1417 | \r |
| 1418 | ASSERT (Buffer != NULL);\r |
| 1419 | \r |
| 1420 | //\r |
| 1421 | // Save Size for return\r |
| 1422 | //\r |
| 1423 | ReturnValue = Size;\r |
| 1424 | \r |
| 1425 | if ((StartAddress & 1) != 0) {\r |
| 1426 | //\r |
| 1427 | // Write a byte if StartAddress is byte aligned\r |
| 1428 | //\r |
| 1429 | PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r |
| 1430 | StartAddress += sizeof (UINT8);\r |
| 1431 | Size -= sizeof (UINT8);\r |
| 1432 | Buffer = (UINT8*)Buffer + 1;\r |
| 1433 | }\r |
| 1434 | \r |
| 1435 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1436 | //\r |
| 1437 | // Write a word if StartAddress is word aligned\r |
| 1438 | //\r |
| 1439 | PciCf8Write16 (StartAddress, *(UINT16*)Buffer);\r |
| 1440 | StartAddress += sizeof (UINT16);\r |
| 1441 | Size -= sizeof (UINT16);\r |
| 1442 | Buffer = (UINT16*)Buffer + 1;\r |
| 1443 | }\r |
| 1444 | \r |
| 1445 | while (Size >= sizeof (UINT32)) {\r |
| 1446 | //\r |
| 1447 | // Write as many double words as possible\r |
| 1448 | //\r |
| 1449 | PciCf8Write32 (StartAddress, *(UINT32*)Buffer);\r |
| 1450 | StartAddress += sizeof (UINT32);\r |
| 1451 | Size -= sizeof (UINT32);\r |
| 1452 | Buffer = (UINT32*)Buffer + 1;\r |
| 1453 | }\r |
| 1454 | \r |
| 1455 | if (Size >= sizeof (UINT16)) {\r |
| 1456 | //\r |
| 1457 | // Write the last remaining word if exist\r |
| 1458 | //\r |
| 1459 | PciCf8Write16 (StartAddress, *(UINT16*)Buffer);\r |
| 1460 | StartAddress += sizeof (UINT16);\r |
| 1461 | Size -= sizeof (UINT16);\r |
| 1462 | Buffer = (UINT16*)Buffer + 1;\r |
| 1463 | }\r |
| 1464 | \r |
| 1465 | if (Size >= sizeof (UINT8)) {\r |
| 1466 | //\r |
| 1467 | // Write the last remaining byte if exist\r |
| 1468 | //\r |
| 1469 | PciCf8Write8 (StartAddress, *(UINT8*)Buffer);\r |
| 1470 | }\r |
| 1471 | \r |
| 1472 | return ReturnValue;\r |
| 1473 | }\r |
projects / mirror_edk2.git / blame