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32fa5588 RN |
1 | /** @file\r |
2 | PCI Segment Library that layers on top of the PCI Library which only\r | |
3 | supports segment 0 PCI configuration access.\r | |
4 | \r | |
ebdde8ff | 5 | Copyright (c) 2016 - 2017, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 6 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
32fa5588 RN |
7 | \r |
8 | **/\r | |
9 | \r | |
10 | #include <Base.h>\r | |
11 | #include <Library/BaseLib.h>\r | |
12 | #include <Library/DebugLib.h>\r | |
13 | #include <Library/PciLib.h>\r | |
14 | #include <Library/PciSegmentLib.h>\r | |
15 | \r | |
16 | /**\r | |
17 | Assert the validity of a PCI Segment address.\r | |
18 | A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r | |
19 | and the segment should be 0.\r | |
20 | \r | |
21 | @param A The address to validate.\r | |
22 | @param M Additional bits to assert to be zero.\r | |
23 | \r | |
24 | **/\r | |
2f88bd3a | 25 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A, M) \\r |
32fa5588 RN |
26 | ASSERT (((A) & (0xfffffffff0000000ULL | (M))) == 0)\r |
27 | \r | |
28 | /**\r | |
29 | Convert the PCI Segment library address to PCI library address.\r | |
30 | \r | |
31 | @param A The address to convert.\r | |
32 | **/\r | |
2f88bd3a | 33 | #define PCI_SEGMENT_TO_PCI_ADDRESS(A) ((UINTN) (UINT32) A)\r |
32fa5588 RN |
34 | \r |
35 | /**\r | |
36 | Register a PCI device so PCI configuration registers may be accessed after\r | |
37 | SetVirtualAddressMap().\r | |
38 | \r | |
39 | If any reserved bits in Address are set, then ASSERT().\r | |
40 | \r | |
41 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
42 | Register.\r | |
43 | \r | |
44 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
45 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r | |
46 | after ExitBootServices().\r | |
47 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
48 | at runtime could not be mapped.\r | |
49 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
50 | complete the registration.\r | |
51 | \r | |
52 | **/\r | |
53 | RETURN_STATUS\r | |
54 | EFIAPI\r | |
55 | PciSegmentRegisterForRuntimeAccess (\r | |
56 | IN UINTN Address\r | |
57 | )\r | |
58 | {\r | |
59 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
60 | return PciRegisterForRuntimeAccess (PCI_SEGMENT_TO_PCI_ADDRESS (Address));\r | |
61 | }\r | |
62 | \r | |
63 | /**\r | |
64 | Reads an 8-bit PCI configuration register.\r | |
65 | \r | |
66 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
67 | This function must guarantee that all PCI read and write operations are serialized.\r | |
68 | \r | |
69 | If any reserved bits in Address are set, then ASSERT().\r | |
70 | \r | |
ebdde8ff | 71 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
72 | \r |
73 | @return The 8-bit PCI configuration register specified by Address.\r | |
74 | \r | |
75 | **/\r | |
76 | UINT8\r | |
77 | EFIAPI\r | |
78 | PciSegmentRead8 (\r | |
2f88bd3a | 79 | IN UINT64 Address\r |
32fa5588 RN |
80 | )\r |
81 | {\r | |
82 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
83 | \r | |
84 | return PciRead8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));\r | |
85 | }\r | |
86 | \r | |
87 | /**\r | |
88 | Writes an 8-bit PCI configuration register.\r | |
89 | \r | |
90 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
91 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
92 | \r | |
93 | If any reserved bits in Address are set, then ASSERT().\r | |
94 | \r | |
ebdde8ff | 95 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
96 | @param Value The value to write.\r |
97 | \r | |
98 | @return The value written to the PCI configuration register.\r | |
99 | \r | |
100 | **/\r | |
101 | UINT8\r | |
102 | EFIAPI\r | |
103 | PciSegmentWrite8 (\r | |
2f88bd3a MK |
104 | IN UINT64 Address,\r |
105 | IN UINT8 Value\r | |
32fa5588 RN |
106 | )\r |
107 | {\r | |
108 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
109 | \r | |
110 | return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);\r | |
111 | }\r | |
112 | \r | |
113 | /**\r | |
114 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value.\r | |
115 | \r | |
116 | Reads the 8-bit PCI configuration register specified by Address,\r | |
117 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
118 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
119 | The value written to the PCI configuration register is returned.\r | |
120 | This function must guarantee that all PCI read and write operations are serialized.\r | |
121 | \r | |
122 | If any reserved bits in Address are set, then ASSERT().\r | |
123 | \r | |
ebdde8ff | 124 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
125 | @param OrData The value to OR with the PCI configuration register.\r |
126 | \r | |
127 | @return The value written to the PCI configuration register.\r | |
128 | \r | |
129 | **/\r | |
130 | UINT8\r | |
131 | EFIAPI\r | |
132 | PciSegmentOr8 (\r | |
2f88bd3a MK |
133 | IN UINT64 Address,\r |
134 | IN UINT8 OrData\r | |
32fa5588 RN |
135 | )\r |
136 | {\r | |
2f88bd3a | 137 | return PciWrite8 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), (UINT8)(PciSegmentRead8 (Address) | OrData));\r |
32fa5588 RN |
138 | }\r |
139 | \r | |
140 | /**\r | |
141 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r | |
142 | \r | |
143 | Reads the 8-bit PCI configuration register specified by Address,\r | |
144 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
145 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
146 | The value written to the PCI configuration register is returned.\r | |
147 | This function must guarantee that all PCI read and write operations are serialized.\r | |
148 | If any reserved bits in Address are set, then ASSERT().\r | |
149 | \r | |
ebdde8ff | 150 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
151 | @param AndData The value to AND with the PCI configuration register.\r |
152 | \r | |
153 | @return The value written to the PCI configuration register.\r | |
154 | \r | |
155 | **/\r | |
156 | UINT8\r | |
157 | EFIAPI\r | |
158 | PciSegmentAnd8 (\r | |
2f88bd3a MK |
159 | IN UINT64 Address,\r |
160 | IN UINT8 AndData\r | |
32fa5588 RN |
161 | )\r |
162 | {\r | |
2f88bd3a | 163 | return PciSegmentWrite8 (Address, (UINT8)(PciSegmentRead8 (Address) & AndData));\r |
32fa5588 RN |
164 | }\r |
165 | \r | |
166 | /**\r | |
167 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
168 | followed a bitwise OR with another 8-bit value.\r | |
169 | \r | |
170 | Reads the 8-bit PCI configuration register specified by Address,\r | |
171 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
172 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
173 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
174 | The value written to the PCI configuration register is returned.\r | |
175 | This function must guarantee that all PCI read and write operations are serialized.\r | |
176 | \r | |
177 | If any reserved bits in Address are set, then ASSERT().\r | |
178 | \r | |
ebdde8ff RN |
179 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
180 | @param AndData The value to AND with the PCI configuration register.\r | |
32fa5588 RN |
181 | @param OrData The value to OR with the PCI configuration register.\r |
182 | \r | |
183 | @return The value written to the PCI configuration register.\r | |
184 | \r | |
185 | **/\r | |
186 | UINT8\r | |
187 | EFIAPI\r | |
188 | PciSegmentAndThenOr8 (\r | |
2f88bd3a MK |
189 | IN UINT64 Address,\r |
190 | IN UINT8 AndData,\r | |
191 | IN UINT8 OrData\r | |
32fa5588 RN |
192 | )\r |
193 | {\r | |
2f88bd3a | 194 | return PciSegmentWrite8 (Address, (UINT8)((PciSegmentRead8 (Address) & AndData) | OrData));\r |
32fa5588 RN |
195 | }\r |
196 | \r | |
197 | /**\r | |
198 | Reads a bit field of a PCI configuration register.\r | |
199 | \r | |
200 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
201 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
202 | returned.\r | |
203 | \r | |
204 | If any reserved bits in Address are set, then ASSERT().\r | |
205 | If StartBit is greater than 7, then ASSERT().\r | |
206 | If EndBit is greater than 7, then ASSERT().\r | |
207 | If EndBit is less than StartBit, then ASSERT().\r | |
208 | \r | |
ebdde8ff | 209 | @param Address PCI configuration register to read.\r |
32fa5588 RN |
210 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
211 | Range 0..7.\r | |
212 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
213 | Range 0..7.\r | |
214 | \r | |
215 | @return The value of the bit field read from the PCI configuration register.\r | |
216 | \r | |
217 | **/\r | |
218 | UINT8\r | |
219 | EFIAPI\r | |
220 | PciSegmentBitFieldRead8 (\r | |
2f88bd3a MK |
221 | IN UINT64 Address,\r |
222 | IN UINTN StartBit,\r | |
223 | IN UINTN EndBit\r | |
32fa5588 RN |
224 | )\r |
225 | {\r | |
226 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r | |
227 | }\r | |
228 | \r | |
229 | /**\r | |
230 | Writes a bit field to a PCI configuration register.\r | |
231 | \r | |
232 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
233 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
234 | destination PCI configuration register are preserved. The new value of the\r | |
235 | 8-bit register is returned.\r | |
236 | \r | |
237 | If any reserved bits in Address are set, then ASSERT().\r | |
238 | If StartBit is greater than 7, then ASSERT().\r | |
239 | If EndBit is greater than 7, then ASSERT().\r | |
240 | If EndBit is less than StartBit, then ASSERT().\r | |
241 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
242 | \r | |
ebdde8ff | 243 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
244 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
245 | Range 0..7.\r | |
246 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
247 | Range 0..7.\r | |
ebdde8ff | 248 | @param Value New value of the bit field.\r |
32fa5588 RN |
249 | \r |
250 | @return The value written back to the PCI configuration register.\r | |
251 | \r | |
252 | **/\r | |
253 | UINT8\r | |
254 | EFIAPI\r | |
255 | PciSegmentBitFieldWrite8 (\r | |
2f88bd3a MK |
256 | IN UINT64 Address,\r |
257 | IN UINTN StartBit,\r | |
258 | IN UINTN EndBit,\r | |
259 | IN UINT8 Value\r | |
32fa5588 RN |
260 | )\r |
261 | {\r | |
262 | return PciSegmentWrite8 (\r | |
263 | Address,\r | |
264 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r | |
265 | );\r | |
266 | }\r | |
267 | \r | |
268 | /**\r | |
269 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
270 | writes the result back to the bit field in the 8-bit port.\r | |
271 | \r | |
272 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
273 | bitwise OR between the read result and the value specified by\r | |
274 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
275 | specified by Address. The value written to the PCI configuration register is\r | |
276 | returned. This function must guarantee that all PCI read and write operations\r | |
277 | are serialized. Extra left bits in OrData are stripped.\r | |
278 | \r | |
279 | If any reserved bits in Address are set, then ASSERT().\r | |
280 | If StartBit is greater than 7, then ASSERT().\r | |
281 | If EndBit is greater than 7, then ASSERT().\r | |
282 | If EndBit is less than StartBit, then ASSERT().\r | |
283 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
284 | \r | |
ebdde8ff | 285 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
286 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
287 | Range 0..7.\r | |
288 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
289 | Range 0..7.\r | |
290 | @param OrData The value to OR with the PCI configuration register.\r | |
291 | \r | |
292 | @return The value written back to the PCI configuration register.\r | |
293 | \r | |
294 | **/\r | |
295 | UINT8\r | |
296 | EFIAPI\r | |
297 | PciSegmentBitFieldOr8 (\r | |
2f88bd3a MK |
298 | IN UINT64 Address,\r |
299 | IN UINTN StartBit,\r | |
300 | IN UINTN EndBit,\r | |
301 | IN UINT8 OrData\r | |
32fa5588 RN |
302 | )\r |
303 | {\r | |
304 | return PciSegmentWrite8 (\r | |
305 | Address,\r | |
306 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r | |
307 | );\r | |
308 | }\r | |
309 | \r | |
310 | /**\r | |
311 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
312 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
313 | \r | |
314 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
315 | bitwise AND between the read result and the value specified by AndData, and\r | |
316 | writes the result to the 8-bit PCI configuration register specified by\r | |
317 | Address. The value written to the PCI configuration register is returned.\r | |
318 | This function must guarantee that all PCI read and write operations are\r | |
319 | serialized. Extra left bits in AndData are stripped.\r | |
320 | \r | |
321 | If any reserved bits in Address are set, then ASSERT().\r | |
322 | If StartBit is greater than 7, then ASSERT().\r | |
323 | If EndBit is greater than 7, then ASSERT().\r | |
324 | If EndBit is less than StartBit, then ASSERT().\r | |
325 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
326 | \r | |
ebdde8ff | 327 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
328 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
329 | Range 0..7.\r | |
330 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
331 | Range 0..7.\r | |
332 | @param AndData The value to AND with the PCI configuration register.\r | |
333 | \r | |
334 | @return The value written back to the PCI configuration register.\r | |
335 | \r | |
336 | **/\r | |
337 | UINT8\r | |
338 | EFIAPI\r | |
339 | PciSegmentBitFieldAnd8 (\r | |
2f88bd3a MK |
340 | IN UINT64 Address,\r |
341 | IN UINTN StartBit,\r | |
342 | IN UINTN EndBit,\r | |
343 | IN UINT8 AndData\r | |
32fa5588 RN |
344 | )\r |
345 | {\r | |
346 | return PciSegmentWrite8 (\r | |
347 | Address,\r | |
348 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r | |
349 | );\r | |
350 | }\r | |
351 | \r | |
352 | /**\r | |
353 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
ebdde8ff | 354 | bitwise OR, and writes the result back to the bit field in the 8-bit port.\r |
32fa5588 RN |
355 | \r |
356 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
357 | bitwise AND followed by a bitwise OR between the read result and\r | |
358 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
359 | configuration register specified by Address. The value written to the PCI\r | |
360 | configuration register is returned. This function must guarantee that all PCI\r | |
361 | read and write operations are serialized. Extra left bits in both AndData and\r | |
362 | OrData are stripped.\r | |
363 | \r | |
364 | If any reserved bits in Address are set, then ASSERT().\r | |
365 | If StartBit is greater than 7, then ASSERT().\r | |
366 | If EndBit is greater than 7, then ASSERT().\r | |
367 | If EndBit is less than StartBit, then ASSERT().\r | |
368 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
369 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
370 | \r | |
ebdde8ff | 371 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
372 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
373 | Range 0..7.\r | |
374 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
375 | Range 0..7.\r | |
376 | @param AndData The value to AND with the PCI configuration register.\r | |
377 | @param OrData The value to OR with the result of the AND operation.\r | |
378 | \r | |
379 | @return The value written back to the PCI configuration register.\r | |
380 | \r | |
381 | **/\r | |
382 | UINT8\r | |
383 | EFIAPI\r | |
384 | PciSegmentBitFieldAndThenOr8 (\r | |
2f88bd3a MK |
385 | IN UINT64 Address,\r |
386 | IN UINTN StartBit,\r | |
387 | IN UINTN EndBit,\r | |
388 | IN UINT8 AndData,\r | |
389 | IN UINT8 OrData\r | |
32fa5588 RN |
390 | )\r |
391 | {\r | |
392 | return PciSegmentWrite8 (\r | |
393 | Address,\r | |
394 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
395 | );\r | |
396 | }\r | |
397 | \r | |
398 | /**\r | |
399 | Reads a 16-bit PCI configuration register.\r | |
400 | \r | |
401 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
402 | This function must guarantee that all PCI read and write operations are serialized.\r | |
403 | \r | |
404 | If any reserved bits in Address are set, then ASSERT().\r | |
405 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
406 | \r | |
ebdde8ff | 407 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
408 | \r |
409 | @return The 16-bit PCI configuration register specified by Address.\r | |
410 | \r | |
411 | **/\r | |
412 | UINT16\r | |
413 | EFIAPI\r | |
414 | PciSegmentRead16 (\r | |
2f88bd3a | 415 | IN UINT64 Address\r |
32fa5588 RN |
416 | )\r |
417 | {\r | |
418 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
419 | \r | |
420 | return PciRead16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));\r | |
421 | }\r | |
422 | \r | |
423 | /**\r | |
424 | Writes a 16-bit PCI configuration register.\r | |
425 | \r | |
426 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
427 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
428 | \r | |
429 | If any reserved bits in Address are set, then ASSERT().\r | |
430 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
431 | \r | |
ebdde8ff | 432 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
433 | @param Value The value to write.\r |
434 | \r | |
435 | @return The parameter of Value.\r | |
436 | \r | |
437 | **/\r | |
438 | UINT16\r | |
439 | EFIAPI\r | |
440 | PciSegmentWrite16 (\r | |
2f88bd3a MK |
441 | IN UINT64 Address,\r |
442 | IN UINT16 Value\r | |
32fa5588 RN |
443 | )\r |
444 | {\r | |
445 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
446 | \r | |
447 | return PciWrite16 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);\r | |
448 | }\r | |
449 | \r | |
450 | /**\r | |
451 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
452 | a 16-bit value.\r | |
453 | \r | |
454 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
ebdde8ff RN |
455 | bitwise OR between the read result and the value specified by OrData, and\r |
456 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
457 | The value written to the PCI configuration register is returned. This function\r | |
458 | must guarantee that all PCI read and write operations are serialized.\r | |
32fa5588 RN |
459 | \r |
460 | If any reserved bits in Address are set, then ASSERT().\r | |
461 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
462 | \r | |
ebdde8ff | 463 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
32fa5588 RN |
464 | Register.\r |
465 | @param OrData The value to OR with the PCI configuration register.\r | |
466 | \r | |
467 | @return The value written back to the PCI configuration register.\r | |
468 | \r | |
469 | **/\r | |
470 | UINT16\r | |
471 | EFIAPI\r | |
472 | PciSegmentOr16 (\r | |
2f88bd3a MK |
473 | IN UINT64 Address,\r |
474 | IN UINT16 OrData\r | |
32fa5588 RN |
475 | )\r |
476 | {\r | |
2f88bd3a | 477 | return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) | OrData));\r |
32fa5588 RN |
478 | }\r |
479 | \r | |
480 | /**\r | |
481 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r | |
482 | \r | |
483 | Reads the 16-bit PCI configuration register specified by Address,\r | |
484 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
485 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
486 | The value written to the PCI configuration register is returned.\r | |
487 | This function must guarantee that all PCI read and write operations are serialized.\r | |
488 | \r | |
489 | If any reserved bits in Address are set, then ASSERT().\r | |
490 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
491 | \r | |
ebdde8ff | 492 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
493 | @param AndData The value to AND with the PCI configuration register.\r |
494 | \r | |
495 | @return The value written to the PCI configuration register.\r | |
496 | \r | |
497 | **/\r | |
498 | UINT16\r | |
499 | EFIAPI\r | |
500 | PciSegmentAnd16 (\r | |
2f88bd3a MK |
501 | IN UINT64 Address,\r |
502 | IN UINT16 AndData\r | |
32fa5588 RN |
503 | )\r |
504 | {\r | |
2f88bd3a | 505 | return PciSegmentWrite16 (Address, (UINT16)(PciSegmentRead16 (Address) & AndData));\r |
32fa5588 RN |
506 | }\r |
507 | \r | |
508 | /**\r | |
509 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
510 | followed a bitwise OR with another 16-bit value.\r | |
511 | \r | |
512 | Reads the 16-bit PCI configuration register specified by Address,\r | |
513 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
514 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
515 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
516 | The value written to the PCI configuration register is returned.\r | |
517 | This function must guarantee that all PCI read and write operations are serialized.\r | |
518 | \r | |
519 | If any reserved bits in Address are set, then ASSERT().\r | |
520 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
521 | \r | |
ebdde8ff RN |
522 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
523 | @param AndData The value to AND with the PCI configuration register.\r | |
32fa5588 RN |
524 | @param OrData The value to OR with the PCI configuration register.\r |
525 | \r | |
526 | @return The value written to the PCI configuration register.\r | |
527 | \r | |
528 | **/\r | |
529 | UINT16\r | |
530 | EFIAPI\r | |
531 | PciSegmentAndThenOr16 (\r | |
2f88bd3a MK |
532 | IN UINT64 Address,\r |
533 | IN UINT16 AndData,\r | |
534 | IN UINT16 OrData\r | |
32fa5588 RN |
535 | )\r |
536 | {\r | |
2f88bd3a | 537 | return PciSegmentWrite16 (Address, (UINT16)((PciSegmentRead16 (Address) & AndData) | OrData));\r |
32fa5588 RN |
538 | }\r |
539 | \r | |
540 | /**\r | |
541 | Reads a bit field of a PCI configuration register.\r | |
542 | \r | |
543 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
544 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
545 | returned.\r | |
546 | \r | |
547 | If any reserved bits in Address are set, then ASSERT().\r | |
548 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
549 | If StartBit is greater than 15, then ASSERT().\r | |
550 | If EndBit is greater than 15, then ASSERT().\r | |
551 | If EndBit is less than StartBit, then ASSERT().\r | |
552 | \r | |
ebdde8ff | 553 | @param Address PCI configuration register to read.\r |
32fa5588 RN |
554 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
555 | Range 0..15.\r | |
556 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
557 | Range 0..15.\r | |
558 | \r | |
559 | @return The value of the bit field read from the PCI configuration register.\r | |
560 | \r | |
561 | **/\r | |
562 | UINT16\r | |
563 | EFIAPI\r | |
564 | PciSegmentBitFieldRead16 (\r | |
2f88bd3a MK |
565 | IN UINT64 Address,\r |
566 | IN UINTN StartBit,\r | |
567 | IN UINTN EndBit\r | |
32fa5588 RN |
568 | )\r |
569 | {\r | |
570 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r | |
571 | }\r | |
572 | \r | |
573 | /**\r | |
574 | Writes a bit field to a PCI configuration register.\r | |
575 | \r | |
576 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
577 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
578 | destination PCI configuration register are preserved. The new value of the\r | |
579 | 16-bit register is returned.\r | |
580 | \r | |
581 | If any reserved bits in Address are set, then ASSERT().\r | |
582 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
583 | If StartBit is greater than 15, then ASSERT().\r | |
584 | If EndBit is greater than 15, then ASSERT().\r | |
585 | If EndBit is less than StartBit, then ASSERT().\r | |
586 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
587 | \r | |
ebdde8ff | 588 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
589 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
590 | Range 0..15.\r | |
591 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
592 | Range 0..15.\r | |
ebdde8ff | 593 | @param Value New value of the bit field.\r |
32fa5588 RN |
594 | \r |
595 | @return The value written back to the PCI configuration register.\r | |
596 | \r | |
597 | **/\r | |
598 | UINT16\r | |
599 | EFIAPI\r | |
600 | PciSegmentBitFieldWrite16 (\r | |
2f88bd3a MK |
601 | IN UINT64 Address,\r |
602 | IN UINTN StartBit,\r | |
603 | IN UINTN EndBit,\r | |
604 | IN UINT16 Value\r | |
32fa5588 RN |
605 | )\r |
606 | {\r | |
607 | return PciSegmentWrite16 (\r | |
608 | Address,\r | |
609 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r | |
610 | );\r | |
611 | }\r | |
612 | \r | |
613 | /**\r | |
ebdde8ff RN |
614 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r |
615 | the result back to the bit field in the 16-bit port.\r | |
616 | \r | |
617 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
618 | bitwise OR between the read result and the value specified by\r | |
619 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
620 | specified by Address. The value written to the PCI configuration register is\r | |
621 | returned. This function must guarantee that all PCI read and write operations\r | |
622 | are serialized. Extra left bits in OrData are stripped.\r | |
32fa5588 RN |
623 | \r |
624 | If any reserved bits in Address are set, then ASSERT().\r | |
625 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
626 | If StartBit is greater than 15, then ASSERT().\r | |
627 | If EndBit is greater than 15, then ASSERT().\r | |
628 | If EndBit is less than StartBit, then ASSERT().\r | |
629 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
630 | \r | |
ebdde8ff | 631 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
632 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
633 | Range 0..15.\r | |
634 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
635 | Range 0..15.\r | |
636 | @param OrData The value to OR with the PCI configuration register.\r | |
637 | \r | |
638 | @return The value written back to the PCI configuration register.\r | |
639 | \r | |
640 | **/\r | |
641 | UINT16\r | |
642 | EFIAPI\r | |
643 | PciSegmentBitFieldOr16 (\r | |
2f88bd3a MK |
644 | IN UINT64 Address,\r |
645 | IN UINTN StartBit,\r | |
646 | IN UINTN EndBit,\r | |
647 | IN UINT16 OrData\r | |
32fa5588 RN |
648 | )\r |
649 | {\r | |
650 | return PciSegmentWrite16 (\r | |
651 | Address,\r | |
652 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r | |
653 | );\r | |
654 | }\r | |
655 | \r | |
656 | /**\r | |
ebdde8ff RN |
657 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
658 | AND, writes the result back to the bit field in the 16-bit register.\r | |
32fa5588 | 659 | \r |
ebdde8ff RN |
660 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
661 | bitwise AND between the read result and the value specified by AndData, and\r | |
662 | writes the result to the 16-bit PCI configuration register specified by\r | |
663 | Address. The value written to the PCI configuration register is returned.\r | |
664 | This function must guarantee that all PCI read and write operations are\r | |
665 | serialized. Extra left bits in AndData are stripped.\r | |
32fa5588 RN |
666 | \r |
667 | If any reserved bits in Address are set, then ASSERT().\r | |
668 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
ebdde8ff RN |
669 | If StartBit is greater than 15, then ASSERT().\r |
670 | If EndBit is greater than 15, then ASSERT().\r | |
32fa5588 RN |
671 | If EndBit is less than StartBit, then ASSERT().\r |
672 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
673 | \r | |
ebdde8ff | 674 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 | 675 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
ebdde8ff | 676 | Range 0..15.\r |
32fa5588 | 677 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
ebdde8ff RN |
678 | Range 0..15.\r |
679 | @param AndData The value to AND with the PCI configuration register.\r | |
32fa5588 | 680 | \r |
ebdde8ff | 681 | @return The value written back to the PCI configuration register.\r |
32fa5588 RN |
682 | \r |
683 | **/\r | |
684 | UINT16\r | |
685 | EFIAPI\r | |
686 | PciSegmentBitFieldAnd16 (\r | |
2f88bd3a MK |
687 | IN UINT64 Address,\r |
688 | IN UINTN StartBit,\r | |
689 | IN UINTN EndBit,\r | |
690 | IN UINT16 AndData\r | |
32fa5588 RN |
691 | )\r |
692 | {\r | |
693 | return PciSegmentWrite16 (\r | |
694 | Address,\r | |
695 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r | |
696 | );\r | |
697 | }\r | |
698 | \r | |
699 | /**\r | |
700 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
701 | bitwise OR, and writes the result back to the bit field in the\r | |
702 | 16-bit port.\r | |
703 | \r | |
704 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
705 | bitwise AND followed by a bitwise OR between the read result and\r | |
706 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
707 | configuration register specified by Address. The value written to the PCI\r | |
708 | configuration register is returned. This function must guarantee that all PCI\r | |
709 | read and write operations are serialized. Extra left bits in both AndData and\r | |
710 | OrData are stripped.\r | |
711 | \r | |
712 | If any reserved bits in Address are set, then ASSERT().\r | |
713 | If StartBit is greater than 15, then ASSERT().\r | |
714 | If EndBit is greater than 15, then ASSERT().\r | |
715 | If EndBit is less than StartBit, then ASSERT().\r | |
716 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
717 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
718 | \r | |
ebdde8ff | 719 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
720 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
721 | Range 0..15.\r | |
722 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
723 | Range 0..15.\r | |
724 | @param AndData The value to AND with the PCI configuration register.\r | |
725 | @param OrData The value to OR with the result of the AND operation.\r | |
726 | \r | |
727 | @return The value written back to the PCI configuration register.\r | |
728 | \r | |
729 | **/\r | |
730 | UINT16\r | |
731 | EFIAPI\r | |
732 | PciSegmentBitFieldAndThenOr16 (\r | |
2f88bd3a MK |
733 | IN UINT64 Address,\r |
734 | IN UINTN StartBit,\r | |
735 | IN UINTN EndBit,\r | |
736 | IN UINT16 AndData,\r | |
737 | IN UINT16 OrData\r | |
32fa5588 RN |
738 | )\r |
739 | {\r | |
740 | return PciSegmentWrite16 (\r | |
741 | Address,\r | |
742 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
743 | );\r | |
744 | }\r | |
745 | \r | |
746 | /**\r | |
747 | Reads a 32-bit PCI configuration register.\r | |
748 | \r | |
749 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
750 | This function must guarantee that all PCI read and write operations are serialized.\r | |
751 | \r | |
752 | If any reserved bits in Address are set, then ASSERT().\r | |
753 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
754 | \r | |
ebdde8ff | 755 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
756 | \r |
757 | @return The 32-bit PCI configuration register specified by Address.\r | |
758 | \r | |
759 | **/\r | |
760 | UINT32\r | |
761 | EFIAPI\r | |
762 | PciSegmentRead32 (\r | |
2f88bd3a | 763 | IN UINT64 Address\r |
32fa5588 RN |
764 | )\r |
765 | {\r | |
766 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
767 | \r | |
768 | return PciRead32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address));\r | |
769 | }\r | |
770 | \r | |
771 | /**\r | |
772 | Writes a 32-bit PCI configuration register.\r | |
773 | \r | |
774 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
775 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
776 | \r | |
777 | If any reserved bits in Address are set, then ASSERT().\r | |
778 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
779 | \r | |
ebdde8ff | 780 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
781 | @param Value The value to write.\r |
782 | \r | |
783 | @return The parameter of Value.\r | |
784 | \r | |
785 | **/\r | |
786 | UINT32\r | |
787 | EFIAPI\r | |
788 | PciSegmentWrite32 (\r | |
2f88bd3a MK |
789 | IN UINT64 Address,\r |
790 | IN UINT32 Value\r | |
32fa5588 RN |
791 | )\r |
792 | {\r | |
793 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
794 | \r | |
795 | return PciWrite32 (PCI_SEGMENT_TO_PCI_ADDRESS (Address), Value);\r | |
796 | }\r | |
797 | \r | |
798 | /**\r | |
799 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit value.\r | |
800 | \r | |
801 | Reads the 32-bit PCI configuration register specified by Address,\r | |
802 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
803 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
804 | The value written to the PCI configuration register is returned.\r | |
805 | This function must guarantee that all PCI read and write operations are serialized.\r | |
806 | \r | |
807 | If any reserved bits in Address are set, then ASSERT().\r | |
808 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
809 | \r | |
ebdde8ff | 810 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
811 | @param OrData The value to OR with the PCI configuration register.\r |
812 | \r | |
813 | @return The value written to the PCI configuration register.\r | |
814 | \r | |
815 | **/\r | |
816 | UINT32\r | |
817 | EFIAPI\r | |
818 | PciSegmentOr32 (\r | |
2f88bd3a MK |
819 | IN UINT64 Address,\r |
820 | IN UINT32 OrData\r | |
32fa5588 RN |
821 | )\r |
822 | {\r | |
823 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r | |
824 | }\r | |
825 | \r | |
826 | /**\r | |
827 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r | |
828 | \r | |
829 | Reads the 32-bit PCI configuration register specified by Address,\r | |
830 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
831 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
832 | The value written to the PCI configuration register is returned.\r | |
833 | This function must guarantee that all PCI read and write operations are serialized.\r | |
834 | \r | |
835 | If any reserved bits in Address are set, then ASSERT().\r | |
836 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
837 | \r | |
ebdde8ff | 838 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
839 | @param AndData The value to AND with the PCI configuration register.\r |
840 | \r | |
841 | @return The value written to the PCI configuration register.\r | |
842 | \r | |
843 | **/\r | |
844 | UINT32\r | |
845 | EFIAPI\r | |
846 | PciSegmentAnd32 (\r | |
2f88bd3a MK |
847 | IN UINT64 Address,\r |
848 | IN UINT32 AndData\r | |
32fa5588 RN |
849 | )\r |
850 | {\r | |
851 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r | |
852 | }\r | |
853 | \r | |
854 | /**\r | |
855 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
856 | followed a bitwise OR with another 32-bit value.\r | |
857 | \r | |
858 | Reads the 32-bit PCI configuration register specified by Address,\r | |
859 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
860 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
861 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
862 | The value written to the PCI configuration register is returned.\r | |
863 | This function must guarantee that all PCI read and write operations are serialized.\r | |
864 | \r | |
865 | If any reserved bits in Address are set, then ASSERT().\r | |
866 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
867 | \r | |
ebdde8ff | 868 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
869 | @param AndData The value to AND with the PCI configuration register.\r |
870 | @param OrData The value to OR with the PCI configuration register.\r | |
871 | \r | |
872 | @return The value written to the PCI configuration register.\r | |
873 | \r | |
874 | **/\r | |
875 | UINT32\r | |
876 | EFIAPI\r | |
877 | PciSegmentAndThenOr32 (\r | |
2f88bd3a MK |
878 | IN UINT64 Address,\r |
879 | IN UINT32 AndData,\r | |
880 | IN UINT32 OrData\r | |
32fa5588 RN |
881 | )\r |
882 | {\r | |
883 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r | |
884 | }\r | |
885 | \r | |
886 | /**\r | |
887 | Reads a bit field of a PCI configuration register.\r | |
888 | \r | |
889 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
890 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
891 | returned.\r | |
892 | \r | |
893 | If any reserved bits in Address are set, then ASSERT().\r | |
894 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
895 | If StartBit is greater than 31, then ASSERT().\r | |
896 | If EndBit is greater than 31, then ASSERT().\r | |
897 | If EndBit is less than StartBit, then ASSERT().\r | |
898 | \r | |
ebdde8ff | 899 | @param Address PCI configuration register to read.\r |
32fa5588 RN |
900 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
901 | Range 0..31.\r | |
902 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
903 | Range 0..31.\r | |
904 | \r | |
905 | @return The value of the bit field read from the PCI configuration register.\r | |
906 | \r | |
907 | **/\r | |
908 | UINT32\r | |
909 | EFIAPI\r | |
910 | PciSegmentBitFieldRead32 (\r | |
2f88bd3a MK |
911 | IN UINT64 Address,\r |
912 | IN UINTN StartBit,\r | |
913 | IN UINTN EndBit\r | |
32fa5588 RN |
914 | )\r |
915 | {\r | |
916 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r | |
917 | }\r | |
918 | \r | |
919 | /**\r | |
920 | Writes a bit field to a PCI configuration register.\r | |
921 | \r | |
922 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
923 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
924 | destination PCI configuration register are preserved. The new value of the\r | |
925 | 32-bit register is returned.\r | |
926 | \r | |
927 | If any reserved bits in Address are set, then ASSERT().\r | |
928 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
929 | If StartBit is greater than 31, then ASSERT().\r | |
930 | If EndBit is greater than 31, then ASSERT().\r | |
931 | If EndBit is less than StartBit, then ASSERT().\r | |
932 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
933 | \r | |
ebdde8ff | 934 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
935 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
936 | Range 0..31.\r | |
937 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
938 | Range 0..31.\r | |
ebdde8ff | 939 | @param Value New value of the bit field.\r |
32fa5588 RN |
940 | \r |
941 | @return The value written back to the PCI configuration register.\r | |
942 | \r | |
943 | **/\r | |
944 | UINT32\r | |
945 | EFIAPI\r | |
946 | PciSegmentBitFieldWrite32 (\r | |
2f88bd3a MK |
947 | IN UINT64 Address,\r |
948 | IN UINTN StartBit,\r | |
949 | IN UINTN EndBit,\r | |
950 | IN UINT32 Value\r | |
32fa5588 RN |
951 | )\r |
952 | {\r | |
953 | return PciSegmentWrite32 (\r | |
954 | Address,\r | |
955 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r | |
956 | );\r | |
957 | }\r | |
958 | \r | |
959 | /**\r | |
960 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
961 | writes the result back to the bit field in the 32-bit port.\r | |
962 | \r | |
963 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
964 | bitwise OR between the read result and the value specified by\r | |
965 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
966 | specified by Address. The value written to the PCI configuration register is\r | |
967 | returned. This function must guarantee that all PCI read and write operations\r | |
968 | are serialized. Extra left bits in OrData are stripped.\r | |
969 | \r | |
970 | If any reserved bits in Address are set, then ASSERT().\r | |
971 | If StartBit is greater than 31, then ASSERT().\r | |
972 | If EndBit is greater than 31, then ASSERT().\r | |
973 | If EndBit is less than StartBit, then ASSERT().\r | |
974 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
975 | \r | |
ebdde8ff | 976 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
977 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
978 | Range 0..31.\r | |
979 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
980 | Range 0..31.\r | |
981 | @param OrData The value to OR with the PCI configuration register.\r | |
982 | \r | |
983 | @return The value written back to the PCI configuration register.\r | |
984 | \r | |
985 | **/\r | |
986 | UINT32\r | |
987 | EFIAPI\r | |
988 | PciSegmentBitFieldOr32 (\r | |
2f88bd3a MK |
989 | IN UINT64 Address,\r |
990 | IN UINTN StartBit,\r | |
991 | IN UINTN EndBit,\r | |
992 | IN UINT32 OrData\r | |
32fa5588 RN |
993 | )\r |
994 | {\r | |
995 | return PciSegmentWrite32 (\r | |
996 | Address,\r | |
997 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r | |
998 | );\r | |
999 | }\r | |
1000 | \r | |
1001 | /**\r | |
1002 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1003 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1004 | \r | |
1005 | \r | |
1006 | Reads the 32-bit PCI configuration register specified by Address, performs a bitwise\r | |
1007 | AND between the read result and the value specified by AndData, and writes the result\r | |
1008 | to the 32-bit PCI configuration register specified by Address. The value written to\r | |
1009 | the PCI configuration register is returned. This function must guarantee that all PCI\r | |
1010 | read and write operations are serialized. Extra left bits in AndData are stripped.\r | |
1011 | If any reserved bits in Address are set, then ASSERT().\r | |
1012 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1013 | If StartBit is greater than 31, then ASSERT().\r | |
1014 | If EndBit is greater than 31, then ASSERT().\r | |
1015 | If EndBit is less than StartBit, then ASSERT().\r | |
1016 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1017 | \r | |
ebdde8ff | 1018 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
32fa5588 RN |
1019 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1020 | Range 0..31.\r | |
1021 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1022 | Range 0..31.\r | |
1023 | @param AndData The value to AND with the PCI configuration register.\r | |
1024 | \r | |
1025 | @return The value written back to the PCI configuration register.\r | |
1026 | \r | |
1027 | **/\r | |
1028 | UINT32\r | |
1029 | EFIAPI\r | |
1030 | PciSegmentBitFieldAnd32 (\r | |
2f88bd3a MK |
1031 | IN UINT64 Address,\r |
1032 | IN UINTN StartBit,\r | |
1033 | IN UINTN EndBit,\r | |
1034 | IN UINT32 AndData\r | |
32fa5588 RN |
1035 | )\r |
1036 | {\r | |
1037 | return PciSegmentWrite32 (\r | |
1038 | Address,\r | |
1039 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r | |
1040 | );\r | |
1041 | }\r | |
1042 | \r | |
1043 | /**\r | |
1044 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1045 | bitwise OR, and writes the result back to the bit field in the\r | |
1046 | 32-bit port.\r | |
1047 | \r | |
1048 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1049 | bitwise AND followed by a bitwise OR between the read result and\r | |
1050 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1051 | configuration register specified by Address. The value written to the PCI\r | |
1052 | configuration register is returned. This function must guarantee that all PCI\r | |
1053 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1054 | OrData are stripped.\r | |
1055 | \r | |
1056 | If any reserved bits in Address are set, then ASSERT().\r | |
1057 | If StartBit is greater than 31, then ASSERT().\r | |
1058 | If EndBit is greater than 31, then ASSERT().\r | |
1059 | If EndBit is less than StartBit, then ASSERT().\r | |
1060 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1061 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1062 | \r | |
ebdde8ff | 1063 | @param Address PCI configuration register to write.\r |
32fa5588 RN |
1064 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1065 | Range 0..31.\r | |
1066 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1067 | Range 0..31.\r | |
1068 | @param AndData The value to AND with the PCI configuration register.\r | |
1069 | @param OrData The value to OR with the result of the AND operation.\r | |
1070 | \r | |
1071 | @return The value written back to the PCI configuration register.\r | |
1072 | \r | |
1073 | **/\r | |
1074 | UINT32\r | |
1075 | EFIAPI\r | |
1076 | PciSegmentBitFieldAndThenOr32 (\r | |
2f88bd3a MK |
1077 | IN UINT64 Address,\r |
1078 | IN UINTN StartBit,\r | |
1079 | IN UINTN EndBit,\r | |
1080 | IN UINT32 AndData,\r | |
1081 | IN UINT32 OrData\r | |
32fa5588 RN |
1082 | )\r |
1083 | {\r | |
1084 | return PciSegmentWrite32 (\r | |
1085 | Address,\r | |
1086 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1087 | );\r | |
1088 | }\r | |
1089 | \r | |
1090 | /**\r | |
1091 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1092 | \r | |
1093 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1094 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1095 | configuration registers from a single PCI function to be read. Size is\r | |
1096 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1097 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1098 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1099 | end of the range.\r | |
1100 | \r | |
1101 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1102 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1103 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1104 | \r | |
ebdde8ff | 1105 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
32fa5588 | 1106 | Function and Register.\r |
ebdde8ff RN |
1107 | @param Size Size in bytes of the transfer.\r |
1108 | @param Buffer Pointer to a buffer receiving the data read.\r | |
32fa5588 RN |
1109 | \r |
1110 | @return Size\r | |
1111 | \r | |
1112 | **/\r | |
1113 | UINTN\r | |
1114 | EFIAPI\r | |
1115 | PciSegmentReadBuffer (\r | |
2f88bd3a MK |
1116 | IN UINT64 StartAddress,\r |
1117 | IN UINTN Size,\r | |
1118 | OUT VOID *Buffer\r | |
32fa5588 RN |
1119 | )\r |
1120 | {\r | |
2f88bd3a | 1121 | UINTN ReturnValue;\r |
32fa5588 RN |
1122 | \r |
1123 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1124 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1125 | \r | |
1126 | if (Size == 0) {\r | |
1127 | return Size;\r | |
1128 | }\r | |
1129 | \r | |
1130 | ASSERT (Buffer != NULL);\r | |
1131 | \r | |
1132 | //\r | |
1133 | // Save Size for return\r | |
1134 | //\r | |
1135 | ReturnValue = Size;\r | |
1136 | \r | |
1137 | if ((StartAddress & BIT0) != 0) {\r | |
1138 | //\r | |
1139 | // Read a byte if StartAddress is byte aligned\r | |
1140 | //\r | |
1141 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
2f88bd3a MK |
1142 | StartAddress += sizeof (UINT8);\r |
1143 | Size -= sizeof (UINT8);\r | |
1144 | Buffer = (UINT8 *)Buffer + 1;\r | |
32fa5588 RN |
1145 | }\r |
1146 | \r | |
2f88bd3a | 1147 | if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r |
32fa5588 RN |
1148 | //\r |
1149 | // Read a word if StartAddress is word aligned\r | |
1150 | //\r | |
1151 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r | |
1152 | StartAddress += sizeof (UINT16);\r | |
2f88bd3a MK |
1153 | Size -= sizeof (UINT16);\r |
1154 | Buffer = (UINT16 *)Buffer + 1;\r | |
32fa5588 RN |
1155 | }\r |
1156 | \r | |
1157 | while (Size >= sizeof (UINT32)) {\r | |
1158 | //\r | |
1159 | // Read as many double words as possible\r | |
1160 | //\r | |
1161 | WriteUnaligned32 (Buffer, PciSegmentRead32 (StartAddress));\r | |
1162 | StartAddress += sizeof (UINT32);\r | |
2f88bd3a MK |
1163 | Size -= sizeof (UINT32);\r |
1164 | Buffer = (UINT32 *)Buffer + 1;\r | |
32fa5588 RN |
1165 | }\r |
1166 | \r | |
1167 | if (Size >= sizeof (UINT16)) {\r | |
1168 | //\r | |
1169 | // Read the last remaining word if exist\r | |
1170 | //\r | |
1171 | WriteUnaligned16 (Buffer, PciSegmentRead16 (StartAddress));\r | |
1172 | StartAddress += sizeof (UINT16);\r | |
2f88bd3a MK |
1173 | Size -= sizeof (UINT16);\r |
1174 | Buffer = (UINT16 *)Buffer + 1;\r | |
32fa5588 RN |
1175 | }\r |
1176 | \r | |
1177 | if (Size >= sizeof (UINT8)) {\r | |
1178 | //\r | |
1179 | // Read the last remaining byte if exist\r | |
1180 | //\r | |
1181 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1182 | }\r | |
1183 | \r | |
1184 | return ReturnValue;\r | |
1185 | }\r | |
1186 | \r | |
1187 | /**\r | |
1188 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1189 | configuration space.\r | |
1190 | \r | |
1191 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1192 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1193 | configuration registers from a single PCI function to be written. Size is\r | |
1194 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1195 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1196 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1197 | and the end of the range.\r | |
1198 | \r | |
1199 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1200 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1201 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1202 | \r | |
ebdde8ff | 1203 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
32fa5588 | 1204 | Function and Register.\r |
ebdde8ff RN |
1205 | @param Size Size in bytes of the transfer.\r |
1206 | @param Buffer Pointer to a buffer containing the data to write.\r | |
32fa5588 RN |
1207 | \r |
1208 | @return The parameter of Size.\r | |
1209 | \r | |
1210 | **/\r | |
1211 | UINTN\r | |
1212 | EFIAPI\r | |
1213 | PciSegmentWriteBuffer (\r | |
2f88bd3a MK |
1214 | IN UINT64 StartAddress,\r |
1215 | IN UINTN Size,\r | |
1216 | IN VOID *Buffer\r | |
32fa5588 RN |
1217 | )\r |
1218 | {\r | |
2f88bd3a | 1219 | UINTN ReturnValue;\r |
32fa5588 RN |
1220 | \r |
1221 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1222 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1223 | \r | |
1224 | if (Size == 0) {\r | |
1225 | return 0;\r | |
1226 | }\r | |
1227 | \r | |
1228 | ASSERT (Buffer != NULL);\r | |
1229 | \r | |
1230 | //\r | |
1231 | // Save Size for return\r | |
1232 | //\r | |
1233 | ReturnValue = Size;\r | |
1234 | \r | |
1235 | if ((StartAddress & BIT0) != 0) {\r | |
1236 | //\r | |
1237 | // Write a byte if StartAddress is byte aligned\r | |
1238 | //\r | |
2f88bd3a | 1239 | PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r |
32fa5588 | 1240 | StartAddress += sizeof (UINT8);\r |
2f88bd3a MK |
1241 | Size -= sizeof (UINT8);\r |
1242 | Buffer = (UINT8 *)Buffer + 1;\r | |
32fa5588 RN |
1243 | }\r |
1244 | \r | |
2f88bd3a | 1245 | if ((Size >= sizeof (UINT16)) && ((StartAddress & BIT1) != 0)) {\r |
32fa5588 RN |
1246 | //\r |
1247 | // Write a word if StartAddress is word aligned\r | |
1248 | //\r | |
1249 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r | |
1250 | StartAddress += sizeof (UINT16);\r | |
2f88bd3a MK |
1251 | Size -= sizeof (UINT16);\r |
1252 | Buffer = (UINT16 *)Buffer + 1;\r | |
32fa5588 RN |
1253 | }\r |
1254 | \r | |
1255 | while (Size >= sizeof (UINT32)) {\r | |
1256 | //\r | |
1257 | // Write as many double words as possible\r | |
1258 | //\r | |
1259 | PciSegmentWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r | |
1260 | StartAddress += sizeof (UINT32);\r | |
2f88bd3a MK |
1261 | Size -= sizeof (UINT32);\r |
1262 | Buffer = (UINT32 *)Buffer + 1;\r | |
32fa5588 RN |
1263 | }\r |
1264 | \r | |
1265 | if (Size >= sizeof (UINT16)) {\r | |
1266 | //\r | |
1267 | // Write the last remaining word if exist\r | |
1268 | //\r | |
1269 | PciSegmentWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r | |
1270 | StartAddress += sizeof (UINT16);\r | |
2f88bd3a MK |
1271 | Size -= sizeof (UINT16);\r |
1272 | Buffer = (UINT16 *)Buffer + 1;\r | |
32fa5588 RN |
1273 | }\r |
1274 | \r | |
1275 | if (Size >= sizeof (UINT8)) {\r | |
1276 | //\r | |
1277 | // Write the last remaining byte if exist\r | |
1278 | //\r | |
2f88bd3a | 1279 | PciSegmentWrite8 (StartAddress, *(UINT8 *)Buffer);\r |
32fa5588 RN |
1280 | }\r |
1281 | \r | |
1282 | return ReturnValue;\r | |
1283 | }\r |