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1 | /** @file\r |
2 | The multiple segments PCI configuration Library Services that carry out\r | |
3 | PCI configuration and enable the PCI operations to be replayed during an\r | |
4 | S3 resume. This library class maps directly on top of the PciSegmentLib class.\r | |
5 | \r | |
6 | Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r | |
7 | This program and the accompanying materials\r | |
8 | are licensed and made available under the terms and conditions of the BSD License\r | |
9 | which accompanies this distribution. The full text of the license may be found at\r | |
10 | http://opensource.org/licenses/bsd-license.php\r | |
11 | \r | |
12 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
13 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
14 | \r | |
15 | **/\r | |
16 | \r | |
17 | \r | |
18 | #include <Base.h>\r | |
19 | \r | |
20 | #include <Library/DebugLib.h>\r | |
21 | #include <Library/S3BootScriptLib.h>\r | |
22 | #include <Library/PciSegmentLib.h>\r | |
23 | \r | |
24 | /**\r | |
25 | Macro that converts address in PciSegmentLib format to the new address that can be pass\r | |
26 | to the S3 Boot Script Library functions. The Segment is dropped.\r | |
27 | \r | |
28 | @param Address Address in PciSegmentLib format.\r | |
29 | \r | |
30 | @retval New address that can be pass to the S3 Boot Script Library functions.\r | |
31 | **/\r | |
32 | #define PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS(Address) \\r | |
33 | ((((UINT32)(Address) >> 20) & 0xff) << 24) | \\r | |
34 | ((((UINT32)(Address) >> 15) & 0x1f) << 16) | \\r | |
35 | ((((UINT32)(Address) >> 12) & 0x07) << 8) | \\r | |
36 | LShiftU64 ((Address) & 0xfff, 32) // Always put Register in high four bytes.\r | |
37 | \r | |
38 | /**\r | |
39 | Saves a PCI configuration value to the boot script.\r | |
40 | \r | |
41 | This internal worker function saves a PCI configuration value in\r | |
42 | the S3 script to be replayed on S3 resume.\r | |
43 | \r | |
44 | If the saving process fails, then ASSERT().\r | |
45 | \r | |
46 | @param Width The width of PCI configuration.\r | |
47 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
48 | Register.\r | |
49 | @param Buffer The buffer containing value.\r | |
50 | \r | |
51 | **/\r | |
52 | VOID\r | |
53 | InternalSavePciSegmentWriteValueToBootScript (\r | |
54 | IN S3_BOOT_SCRIPT_LIB_WIDTH Width,\r | |
55 | IN UINT64 Address,\r | |
56 | IN VOID *Buffer\r | |
57 | )\r | |
58 | {\r | |
59 | RETURN_STATUS Status;\r | |
60 | \r | |
61 | Status = S3BootScriptSavePciCfg2Write (\r | |
62 | Width,\r | |
63 | RShiftU64 ((Address), 32) & 0xffff,\r | |
64 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (Address),\r | |
65 | 1,\r | |
66 | Buffer\r | |
67 | );\r | |
68 | ASSERT_RETURN_ERROR (Status);\r | |
69 | }\r | |
70 | \r | |
71 | /**\r | |
72 | Saves an 8-bit PCI configuration value to the boot script.\r | |
73 | \r | |
74 | This internal worker function saves an 8-bit PCI configuration value in\r | |
75 | the S3 script to be replayed on S3 resume.\r | |
76 | \r | |
77 | If the saving process fails, then ASSERT().\r | |
78 | \r | |
79 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
80 | Register.\r | |
81 | @param Value The value saved to boot script.\r | |
82 | \r | |
83 | @return Value.\r | |
84 | \r | |
85 | **/\r | |
86 | UINT8\r | |
87 | InternalSavePciSegmentWrite8ValueToBootScript (\r | |
88 | IN UINT64 Address,\r | |
89 | IN UINT8 Value\r | |
90 | )\r | |
91 | {\r | |
92 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r | |
93 | \r | |
94 | return Value;\r | |
95 | }\r | |
96 | \r | |
97 | /**\r | |
98 | Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
99 | be replayed on S3 resume.\r | |
100 | \r | |
101 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
102 | This function must guarantee that all PCI read and write operations are serialized.\r | |
103 | \r | |
104 | If any reserved bits in Address are set, then ASSERT().\r | |
105 | \r | |
106 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
107 | \r | |
108 | @return The 8-bit PCI configuration register specified by Address.\r | |
109 | \r | |
110 | **/\r | |
111 | UINT8\r | |
112 | EFIAPI\r | |
113 | S3PciSegmentRead8 (\r | |
114 | IN UINT64 Address\r | |
115 | )\r | |
116 | {\r | |
117 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));\r | |
118 | }\r | |
119 | \r | |
120 | /**\r | |
121 | Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r | |
122 | be replayed on S3 resume.\r | |
123 | \r | |
124 | Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r | |
125 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
126 | \r | |
127 | If any reserved bits in Address are set, then ASSERT().\r | |
128 | \r | |
129 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
130 | @param Value The value to write.\r | |
131 | \r | |
132 | @return The value written to the PCI configuration register.\r | |
133 | \r | |
134 | **/\r | |
135 | UINT8\r | |
136 | EFIAPI\r | |
137 | S3PciSegmentWrite8 (\r | |
138 | IN UINT64 Address,\r | |
139 | IN UINT8 Value\r | |
140 | )\r | |
141 | {\r | |
142 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));\r | |
143 | }\r | |
144 | \r | |
145 | /**\r | |
146 | Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r | |
147 | the value in the S3 script to be replayed on S3 resume.\r | |
148 | \r | |
149 | Reads the 8-bit PCI configuration register specified by Address,\r | |
150 | performs a bitwise OR between the read result and the value specified by OrData,\r | |
151 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
152 | The value written to the PCI configuration register is returned.\r | |
153 | This function must guarantee that all PCI read and write operations are serialized.\r | |
154 | \r | |
155 | If any reserved bits in Address are set, then ASSERT().\r | |
156 | \r | |
157 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
158 | @param OrData The value to OR with the PCI configuration register.\r | |
159 | \r | |
160 | @return The value written to the PCI configuration register.\r | |
161 | \r | |
162 | **/\r | |
163 | UINT8\r | |
164 | EFIAPI\r | |
165 | S3PciSegmentOr8 (\r | |
166 | IN UINT64 Address,\r | |
167 | IN UINT8 OrData\r | |
168 | )\r | |
169 | {\r | |
170 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));\r | |
171 | }\r | |
172 | \r | |
173 | /**\r | |
174 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r | |
175 | saves the value in the S3 script to be replayed on S3 resume.\r | |
176 | \r | |
177 | Reads the 8-bit PCI configuration register specified by Address,\r | |
178 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
179 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
180 | The value written to the PCI configuration register is returned.\r | |
181 | This function must guarantee that all PCI read and write operations are serialized.\r | |
182 | If any reserved bits in Address are set, then ASSERT().\r | |
183 | \r | |
184 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
185 | @param AndData The value to AND with the PCI configuration register.\r | |
186 | \r | |
187 | @return The value written to the PCI configuration register.\r | |
188 | \r | |
189 | **/\r | |
190 | UINT8\r | |
191 | EFIAPI\r | |
192 | S3PciSegmentAnd8 (\r | |
193 | IN UINT64 Address,\r | |
194 | IN UINT8 AndData\r | |
195 | )\r | |
196 | {\r | |
197 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));\r | |
198 | }\r | |
199 | \r | |
200 | /**\r | |
201 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r | |
202 | followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r | |
203 | be replayed on S3 resume.\r | |
204 | \r | |
205 | Reads the 8-bit PCI configuration register specified by Address,\r | |
206 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
207 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
208 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
209 | The value written to the PCI configuration register is returned.\r | |
210 | This function must guarantee that all PCI read and write operations are serialized.\r | |
211 | \r | |
212 | If any reserved bits in Address are set, then ASSERT().\r | |
213 | \r | |
214 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
215 | @param AndData The value to AND with the PCI configuration register.\r | |
216 | @param OrData The value to OR with the PCI configuration register.\r | |
217 | \r | |
218 | @return The value written to the PCI configuration register.\r | |
219 | \r | |
220 | **/\r | |
221 | UINT8\r | |
222 | EFIAPI\r | |
223 | S3PciSegmentAndThenOr8 (\r | |
224 | IN UINT64 Address,\r | |
225 | IN UINT8 AndData,\r | |
226 | IN UINT8 OrData\r | |
227 | )\r | |
228 | {\r | |
229 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));\r | |
230 | }\r | |
231 | \r | |
232 | /**\r | |
233 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
234 | S3 script to be replayed on S3 resume.\r | |
235 | \r | |
236 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
237 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
238 | returned.\r | |
239 | \r | |
240 | If any reserved bits in Address are set, then ASSERT().\r | |
241 | If StartBit is greater than 7, then ASSERT().\r | |
242 | If EndBit is greater than 7, then ASSERT().\r | |
243 | If EndBit is less than StartBit, then ASSERT().\r | |
244 | \r | |
245 | @param Address PCI configuration register to read.\r | |
246 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
247 | Range 0..7.\r | |
248 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
249 | Range 0..7.\r | |
250 | \r | |
251 | @return The value of the bit field read from the PCI configuration register.\r | |
252 | \r | |
253 | **/\r | |
254 | UINT8\r | |
255 | EFIAPI\r | |
256 | S3PciSegmentBitFieldRead8 (\r | |
257 | IN UINT64 Address,\r | |
258 | IN UINTN StartBit,\r | |
259 | IN UINTN EndBit\r | |
260 | )\r | |
261 | {\r | |
262 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));\r | |
263 | }\r | |
264 | \r | |
265 | /**\r | |
266 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
267 | the S3 script to be replayed on S3 resume.\r | |
268 | \r | |
269 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
270 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
271 | destination PCI configuration register are preserved. The new value of the\r | |
272 | 8-bit register is returned.\r | |
273 | \r | |
274 | If any reserved bits in Address are set, then ASSERT().\r | |
275 | If StartBit is greater than 7, then ASSERT().\r | |
276 | If EndBit is greater than 7, then ASSERT().\r | |
277 | If EndBit is less than StartBit, then ASSERT().\r | |
278 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
279 | \r | |
280 | @param Address PCI configuration register to write.\r | |
281 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
282 | Range 0..7.\r | |
283 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
284 | Range 0..7.\r | |
285 | @param Value New value of the bit field.\r | |
286 | \r | |
287 | @return The value written back to the PCI configuration register.\r | |
288 | \r | |
289 | **/\r | |
290 | UINT8\r | |
291 | EFIAPI\r | |
292 | S3PciSegmentBitFieldWrite8 (\r | |
293 | IN UINT64 Address,\r | |
294 | IN UINTN StartBit,\r | |
295 | IN UINTN EndBit,\r | |
296 | IN UINT8 Value\r | |
297 | )\r | |
298 | {\r | |
299 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));\r | |
300 | }\r | |
301 | \r | |
302 | /**\r | |
303 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r | |
304 | the result back to the bit field in the 8-bit port, and saves the value in the\r | |
305 | S3 script to be replayed on S3 resume.\r | |
306 | \r | |
307 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
308 | bitwise OR between the read result and the value specified by\r | |
309 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
310 | specified by Address. The value written to the PCI configuration register is\r | |
311 | returned. This function must guarantee that all PCI read and write operations\r | |
312 | are serialized. Extra left bits in OrData are stripped.\r | |
313 | \r | |
314 | If any reserved bits in Address are set, then ASSERT().\r | |
315 | If StartBit is greater than 7, then ASSERT().\r | |
316 | If EndBit is greater than 7, then ASSERT().\r | |
317 | If EndBit is less than StartBit, then ASSERT().\r | |
318 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
319 | \r | |
320 | @param Address PCI configuration register to write.\r | |
321 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
322 | Range 0..7.\r | |
323 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
324 | Range 0..7.\r | |
325 | @param OrData The value to OR with the PCI configuration register.\r | |
326 | \r | |
327 | @return The value written back to the PCI configuration register.\r | |
328 | \r | |
329 | **/\r | |
330 | UINT8\r | |
331 | EFIAPI\r | |
332 | S3PciSegmentBitFieldOr8 (\r | |
333 | IN UINT64 Address,\r | |
334 | IN UINTN StartBit,\r | |
335 | IN UINTN EndBit,\r | |
336 | IN UINT8 OrData\r | |
337 | )\r | |
338 | {\r | |
339 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));\r | |
340 | }\r | |
341 | \r | |
342 | /**\r | |
343 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
344 | AND, writes the result back to the bit field in the 8-bit register, and\r | |
345 | saves the value in the S3 script to be replayed on S3 resume.\r | |
346 | \r | |
347 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
348 | bitwise AND between the read result and the value specified by AndData, and\r | |
349 | writes the result to the 8-bit PCI configuration register specified by\r | |
350 | Address. The value written to the PCI configuration register is returned.\r | |
351 | This function must guarantee that all PCI read and write operations are\r | |
352 | serialized. Extra left bits in AndData are stripped.\r | |
353 | \r | |
354 | If any reserved bits in Address are set, then ASSERT().\r | |
355 | If StartBit is greater than 7, then ASSERT().\r | |
356 | If EndBit is greater than 7, then ASSERT().\r | |
357 | If EndBit is less than StartBit, then ASSERT().\r | |
358 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
359 | \r | |
360 | @param Address PCI configuration register to write.\r | |
361 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
362 | Range 0..7.\r | |
363 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
364 | Range 0..7.\r | |
365 | @param AndData The value to AND with the PCI configuration register.\r | |
366 | \r | |
367 | @return The value written back to the PCI configuration register.\r | |
368 | \r | |
369 | **/\r | |
370 | UINT8\r | |
371 | EFIAPI\r | |
372 | S3PciSegmentBitFieldAnd8 (\r | |
373 | IN UINT64 Address,\r | |
374 | IN UINTN StartBit,\r | |
375 | IN UINTN EndBit,\r | |
376 | IN UINT8 AndData\r | |
377 | )\r | |
378 | {\r | |
379 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r | |
380 | }\r | |
381 | \r | |
382 | /**\r | |
383 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
384 | bitwise OR, writes the result back to the bit field in the 8-bit port,\r | |
385 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
386 | \r | |
387 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
388 | bitwise AND followed by a bitwise OR between the read result and\r | |
389 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
390 | configuration register specified by Address. The value written to the PCI\r | |
391 | configuration register is returned. This function must guarantee that all PCI\r | |
392 | read and write operations are serialized. Extra left bits in both AndData and\r | |
393 | OrData are stripped.\r | |
394 | \r | |
395 | If any reserved bits in Address are set, then ASSERT().\r | |
396 | If StartBit is greater than 7, then ASSERT().\r | |
397 | If EndBit is greater than 7, then ASSERT().\r | |
398 | If EndBit is less than StartBit, then ASSERT().\r | |
399 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
400 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
401 | \r | |
402 | @param Address PCI configuration register to write.\r | |
403 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
404 | Range 0..7.\r | |
405 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
406 | Range 0..7.\r | |
407 | @param AndData The value to AND with the PCI configuration register.\r | |
408 | @param OrData The value to OR with the result of the AND operation.\r | |
409 | \r | |
410 | @return The value written back to the PCI configuration register.\r | |
411 | \r | |
412 | **/\r | |
413 | UINT8\r | |
414 | EFIAPI\r | |
415 | S3PciSegmentBitFieldAndThenOr8 (\r | |
416 | IN UINT64 Address,\r | |
417 | IN UINTN StartBit,\r | |
418 | IN UINTN EndBit,\r | |
419 | IN UINT8 AndData,\r | |
420 | IN UINT8 OrData\r | |
421 | )\r | |
422 | {\r | |
423 | return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r | |
424 | }\r | |
425 | \r | |
426 | /**\r | |
427 | Saves a 16-bit PCI configuration value to the boot script.\r | |
428 | \r | |
429 | This internal worker function saves a 16-bit PCI configuration value in\r | |
430 | the S3 script to be replayed on S3 resume.\r | |
431 | \r | |
432 | If the saving process fails, then ASSERT().\r | |
433 | \r | |
434 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
435 | Register.\r | |
436 | @param Value The value saved to boot script.\r | |
437 | \r | |
438 | @return Value.\r | |
439 | \r | |
440 | **/\r | |
441 | UINT16\r | |
442 | InternalSavePciSegmentWrite16ValueToBootScript (\r | |
443 | IN UINT64 Address,\r | |
444 | IN UINT16 Value\r | |
445 | )\r | |
446 | {\r | |
447 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r | |
448 | \r | |
449 | return Value;\r | |
450 | }\r | |
451 | \r | |
452 | /**\r | |
453 | Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r | |
454 | to be replayed on S3 resume.\r | |
455 | \r | |
456 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
457 | This function must guarantee that all PCI read and write operations are serialized.\r | |
458 | \r | |
459 | If any reserved bits in Address are set, then ASSERT().\r | |
460 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
461 | \r | |
462 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
463 | \r | |
464 | @return The 16-bit PCI configuration register specified by Address.\r | |
465 | \r | |
466 | **/\r | |
467 | UINT16\r | |
468 | EFIAPI\r | |
469 | S3PciSegmentRead16 (\r | |
470 | IN UINT64 Address\r | |
471 | )\r | |
472 | {\r | |
473 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));\r | |
474 | }\r | |
475 | \r | |
476 | /**\r | |
477 | Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r | |
478 | be replayed on S3 resume.\r | |
479 | \r | |
480 | Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r | |
481 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
482 | \r | |
483 | If any reserved bits in Address are set, then ASSERT().\r | |
484 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
485 | \r | |
486 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
487 | @param Value The value to write.\r | |
488 | \r | |
489 | @return The parameter of Value.\r | |
490 | \r | |
491 | **/\r | |
492 | UINT16\r | |
493 | EFIAPI\r | |
494 | S3PciSegmentWrite16 (\r | |
495 | IN UINT64 Address,\r | |
496 | IN UINT16 Value\r | |
497 | )\r | |
498 | {\r | |
499 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));\r | |
500 | }\r | |
501 | \r | |
502 | /**\r | |
503 | Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r | |
504 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
505 | \r | |
506 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
507 | bitwise OR between the read result and the value specified by OrData, and\r | |
508 | writes the result to the 16-bit PCI configuration register specified by Address.\r | |
509 | The value written to the PCI configuration register is returned. This function\r | |
510 | must guarantee that all PCI read and write operations are serialized.\r | |
511 | \r | |
512 | If any reserved bits in Address are set, then ASSERT().\r | |
513 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
514 | \r | |
515 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
516 | Register.\r | |
517 | @param OrData The value to OR with the PCI configuration register.\r | |
518 | \r | |
519 | @return The value written back to the PCI configuration register.\r | |
520 | \r | |
521 | **/\r | |
522 | UINT16\r | |
523 | EFIAPI\r | |
524 | S3PciSegmentOr16 (\r | |
525 | IN UINT64 Address,\r | |
526 | IN UINT16 OrData\r | |
527 | )\r | |
528 | {\r | |
529 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));\r | |
530 | }\r | |
531 | \r | |
532 | /**\r | |
533 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r | |
534 | saves the value in the S3 script to be replayed on S3 resume.\r | |
535 | \r | |
536 | Reads the 16-bit PCI configuration register specified by Address,\r | |
537 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
538 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
539 | The value written to the PCI configuration register is returned.\r | |
540 | This function must guarantee that all PCI read and write operations are serialized.\r | |
541 | \r | |
542 | If any reserved bits in Address are set, then ASSERT().\r | |
543 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
544 | \r | |
545 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
546 | @param AndData The value to AND with the PCI configuration register.\r | |
547 | \r | |
548 | @return The value written to the PCI configuration register.\r | |
549 | \r | |
550 | **/\r | |
551 | UINT16\r | |
552 | EFIAPI\r | |
553 | S3PciSegmentAnd16 (\r | |
554 | IN UINT64 Address,\r | |
555 | IN UINT16 AndData\r | |
556 | )\r | |
557 | {\r | |
558 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));\r | |
559 | }\r | |
560 | \r | |
561 | /**\r | |
562 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r | |
563 | followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r | |
564 | be replayed on S3 resume.\r | |
565 | \r | |
566 | Reads the 16-bit PCI configuration register specified by Address,\r | |
567 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
568 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
569 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
570 | The value written to the PCI configuration register is returned.\r | |
571 | This function must guarantee that all PCI read and write operations are serialized.\r | |
572 | \r | |
573 | If any reserved bits in Address are set, then ASSERT().\r | |
574 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
575 | \r | |
576 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
577 | @param AndData The value to AND with the PCI configuration register.\r | |
578 | @param OrData The value to OR with the PCI configuration register.\r | |
579 | \r | |
580 | @return The value written to the PCI configuration register.\r | |
581 | \r | |
582 | **/\r | |
583 | UINT16\r | |
584 | EFIAPI\r | |
585 | S3PciSegmentAndThenOr16 (\r | |
586 | IN UINT64 Address,\r | |
587 | IN UINT16 AndData,\r | |
588 | IN UINT16 OrData\r | |
589 | )\r | |
590 | {\r | |
591 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));\r | |
592 | }\r | |
593 | \r | |
594 | /**\r | |
595 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
596 | S3 script to be replayed on S3 resume.\r | |
597 | \r | |
598 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
599 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
600 | returned.\r | |
601 | \r | |
602 | If any reserved bits in Address are set, then ASSERT().\r | |
603 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
604 | If StartBit is greater than 15, then ASSERT().\r | |
605 | If EndBit is greater than 15, then ASSERT().\r | |
606 | If EndBit is less than StartBit, then ASSERT().\r | |
607 | \r | |
608 | @param Address PCI configuration register to read.\r | |
609 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
610 | Range 0..15.\r | |
611 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
612 | Range 0..15.\r | |
613 | \r | |
614 | @return The value of the bit field read from the PCI configuration register.\r | |
615 | \r | |
616 | **/\r | |
617 | UINT16\r | |
618 | EFIAPI\r | |
619 | S3PciSegmentBitFieldRead16 (\r | |
620 | IN UINT64 Address,\r | |
621 | IN UINTN StartBit,\r | |
622 | IN UINTN EndBit\r | |
623 | )\r | |
624 | {\r | |
625 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));\r | |
626 | }\r | |
627 | \r | |
628 | /**\r | |
629 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
630 | the S3 script to be replayed on S3 resume.\r | |
631 | \r | |
632 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
633 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
634 | destination PCI configuration register are preserved. The new value of the\r | |
635 | 16-bit register is returned.\r | |
636 | \r | |
637 | If any reserved bits in Address are set, then ASSERT().\r | |
638 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
639 | If StartBit is greater than 15, then ASSERT().\r | |
640 | If EndBit is greater than 15, then ASSERT().\r | |
641 | If EndBit is less than StartBit, then ASSERT().\r | |
642 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
643 | \r | |
644 | @param Address PCI configuration register to write.\r | |
645 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
646 | Range 0..15.\r | |
647 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
648 | Range 0..15.\r | |
649 | @param Value New value of the bit field.\r | |
650 | \r | |
651 | @return The value written back to the PCI configuration register.\r | |
652 | \r | |
653 | **/\r | |
654 | UINT16\r | |
655 | EFIAPI\r | |
656 | S3PciSegmentBitFieldWrite16 (\r | |
657 | IN UINT64 Address,\r | |
658 | IN UINTN StartBit,\r | |
659 | IN UINTN EndBit,\r | |
660 | IN UINT16 Value\r | |
661 | )\r | |
662 | {\r | |
663 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));\r | |
664 | }\r | |
665 | \r | |
666 | /**\r | |
667 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r | |
668 | the result back to the bit field in the 16-bit port, and saves the value in the\r | |
669 | S3 script to be replayed on S3 resume.\r | |
670 | \r | |
671 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
672 | bitwise OR between the read result and the value specified by\r | |
673 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
674 | specified by Address. The value written to the PCI configuration register is\r | |
675 | returned. This function must guarantee that all PCI read and write operations\r | |
676 | are serialized. Extra left bits in OrData are stripped.\r | |
677 | \r | |
678 | If any reserved bits in Address are set, then ASSERT().\r | |
679 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
680 | If StartBit is greater than 15, then ASSERT().\r | |
681 | If EndBit is greater than 15, then ASSERT().\r | |
682 | If EndBit is less than StartBit, then ASSERT().\r | |
683 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
684 | \r | |
685 | @param Address PCI configuration register to write.\r | |
686 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
687 | Range 0..15.\r | |
688 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
689 | Range 0..15.\r | |
690 | @param OrData The value to OR with the PCI configuration register.\r | |
691 | \r | |
692 | @return The value written back to the PCI configuration register.\r | |
693 | \r | |
694 | **/\r | |
695 | UINT16\r | |
696 | EFIAPI\r | |
697 | S3PciSegmentBitFieldOr16 (\r | |
698 | IN UINT64 Address,\r | |
699 | IN UINTN StartBit,\r | |
700 | IN UINTN EndBit,\r | |
701 | IN UINT16 OrData\r | |
702 | )\r | |
703 | {\r | |
704 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));\r | |
705 | }\r | |
706 | \r | |
707 | /**\r | |
708 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
709 | AND, writes the result back to the bit field in the 16-bit register, and\r | |
710 | saves the value in the S3 script to be replayed on S3 resume.\r | |
711 | \r | |
712 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
713 | bitwise AND between the read result and the value specified by AndData, and\r | |
714 | writes the result to the 16-bit PCI configuration register specified by\r | |
715 | Address. The value written to the PCI configuration register is returned.\r | |
716 | This function must guarantee that all PCI read and write operations are\r | |
717 | serialized. Extra left bits in AndData are stripped.\r | |
718 | \r | |
719 | If any reserved bits in Address are set, then ASSERT().\r | |
720 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
721 | If StartBit is greater than 15, then ASSERT().\r | |
722 | If EndBit is greater than 15, then ASSERT().\r | |
723 | If EndBit is less than StartBit, then ASSERT().\r | |
724 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
725 | \r | |
726 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
727 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
728 | Range 0..15.\r | |
729 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
730 | Range 0..15.\r | |
731 | @param AndData The value to AND with the PCI configuration register.\r | |
732 | \r | |
733 | @return The value written back to the PCI configuration register.\r | |
734 | \r | |
735 | **/\r | |
736 | UINT16\r | |
737 | EFIAPI\r | |
738 | S3PciSegmentBitFieldAnd16 (\r | |
739 | IN UINT64 Address,\r | |
740 | IN UINTN StartBit,\r | |
741 | IN UINTN EndBit,\r | |
742 | IN UINT16 AndData\r | |
743 | )\r | |
744 | {\r | |
745 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r | |
746 | }\r | |
747 | \r | |
748 | /**\r | |
749 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
750 | bitwise OR, writes the result back to the bit field in the 16-bit port,\r | |
751 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
752 | \r | |
753 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
754 | bitwise AND followed by a bitwise OR between the read result and\r | |
755 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
756 | configuration register specified by Address. The value written to the PCI\r | |
757 | configuration register is returned. This function must guarantee that all PCI\r | |
758 | read and write operations are serialized. Extra left bits in both AndData and\r | |
759 | OrData are stripped.\r | |
760 | \r | |
761 | If any reserved bits in Address are set, then ASSERT().\r | |
762 | If StartBit is greater than 15, then ASSERT().\r | |
763 | If EndBit is greater than 15, then ASSERT().\r | |
764 | If EndBit is less than StartBit, then ASSERT().\r | |
765 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
766 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
767 | \r | |
768 | @param Address PCI configuration register to write.\r | |
769 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
770 | Range 0..15.\r | |
771 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
772 | Range 0..15.\r | |
773 | @param AndData The value to AND with the PCI configuration register.\r | |
774 | @param OrData The value to OR with the result of the AND operation.\r | |
775 | \r | |
776 | @return The value written back to the PCI configuration register.\r | |
777 | \r | |
778 | **/\r | |
779 | UINT16\r | |
780 | EFIAPI\r | |
781 | S3PciSegmentBitFieldAndThenOr16 (\r | |
782 | IN UINT64 Address,\r | |
783 | IN UINTN StartBit,\r | |
784 | IN UINTN EndBit,\r | |
785 | IN UINT16 AndData,\r | |
786 | IN UINT16 OrData\r | |
787 | )\r | |
788 | {\r | |
789 | return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r | |
790 | }\r | |
791 | \r | |
792 | \r | |
793 | \r | |
794 | /**\r | |
795 | Saves a 32-bit PCI configuration value to the boot script.\r | |
796 | \r | |
797 | This internal worker function saves a 32-bit PCI configuration value in the S3 script\r | |
798 | to be replayed on S3 resume.\r | |
799 | \r | |
800 | If the saving process fails, then ASSERT().\r | |
801 | \r | |
802 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
803 | Register.\r | |
804 | @param Value The value saved to boot script.\r | |
805 | \r | |
806 | @return Value.\r | |
807 | \r | |
808 | **/\r | |
809 | UINT32\r | |
810 | InternalSavePciSegmentWrite32ValueToBootScript (\r | |
811 | IN UINT64 Address,\r | |
812 | IN UINT32 Value\r | |
813 | )\r | |
814 | {\r | |
815 | InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r | |
816 | \r | |
817 | return Value;\r | |
818 | }\r | |
819 | \r | |
820 | /**\r | |
821 | Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r | |
822 | to be replayed on S3 resume.\r | |
823 | \r | |
824 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
825 | This function must guarantee that all PCI read and write operations are serialized.\r | |
826 | \r | |
827 | If any reserved bits in Address are set, then ASSERT().\r | |
828 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
829 | \r | |
830 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
831 | \r | |
832 | @return The 32-bit PCI configuration register specified by Address.\r | |
833 | \r | |
834 | **/\r | |
835 | UINT32\r | |
836 | EFIAPI\r | |
837 | S3PciSegmentRead32 (\r | |
838 | IN UINT64 Address\r | |
839 | )\r | |
840 | {\r | |
841 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));\r | |
842 | }\r | |
843 | \r | |
844 | /**\r | |
845 | Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r | |
846 | be replayed on S3 resume.\r | |
847 | \r | |
848 | Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r | |
849 | Value is returned. This function must guarantee that all PCI read and write operations are serialized.\r | |
850 | \r | |
851 | If any reserved bits in Address are set, then ASSERT().\r | |
852 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
853 | \r | |
854 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
855 | @param Value The value to write.\r | |
856 | \r | |
857 | @return The parameter of Value.\r | |
858 | \r | |
859 | **/\r | |
860 | UINT32\r | |
861 | EFIAPI\r | |
862 | S3PciSegmentWrite32 (\r | |
863 | IN UINT64 Address,\r | |
864 | IN UINT32 Value\r | |
865 | )\r | |
866 | {\r | |
867 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));\r | |
868 | }\r | |
869 | \r | |
870 | /**\r | |
871 | Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r | |
872 | value, and saves the value in the S3 script to be replayed on S3 resume.\r | |
873 | \r | |
874 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
875 | bitwise OR between the read result and the value specified by OrData, and\r | |
876 | writes the result to the 32-bit PCI configuration register specified by Address.\r | |
877 | The value written to the PCI configuration register is returned. This function\r | |
878 | must guarantee that all PCI read and write operations are serialized.\r | |
879 | \r | |
880 | If any reserved bits in Address are set, then ASSERT().\r | |
881 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
882 | \r | |
883 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and\r | |
884 | Register.\r | |
885 | @param OrData The value to OR with the PCI configuration register.\r | |
886 | \r | |
887 | @return The value written back to the PCI configuration register.\r | |
888 | \r | |
889 | **/\r | |
890 | UINT32\r | |
891 | EFIAPI\r | |
892 | S3PciSegmentOr32 (\r | |
893 | IN UINT64 Address,\r | |
894 | IN UINT32 OrData\r | |
895 | )\r | |
896 | {\r | |
897 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));\r | |
898 | }\r | |
899 | \r | |
900 | /**\r | |
901 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r | |
902 | saves the value in the S3 script to be replayed on S3 resume.\r | |
903 | \r | |
904 | Reads the 32-bit PCI configuration register specified by Address,\r | |
905 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
906 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
907 | The value written to the PCI configuration register is returned.\r | |
908 | This function must guarantee that all PCI read and write operations are serialized.\r | |
909 | \r | |
910 | If any reserved bits in Address are set, then ASSERT().\r | |
911 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
912 | \r | |
913 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
914 | @param AndData The value to AND with the PCI configuration register.\r | |
915 | \r | |
916 | @return The value written to the PCI configuration register.\r | |
917 | \r | |
918 | **/\r | |
919 | UINT32\r | |
920 | EFIAPI\r | |
921 | S3PciSegmentAnd32 (\r | |
922 | IN UINT64 Address,\r | |
923 | IN UINT32 AndData\r | |
924 | )\r | |
925 | {\r | |
926 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));\r | |
927 | }\r | |
928 | \r | |
929 | /**\r | |
930 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r | |
931 | followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r | |
932 | be replayed on S3 resume.\r | |
933 | \r | |
934 | Reads the 32-bit PCI configuration register specified by Address,\r | |
935 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
936 | performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r | |
937 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
938 | The value written to the PCI configuration register is returned.\r | |
939 | This function must guarantee that all PCI read and write operations are serialized.\r | |
940 | \r | |
941 | If any reserved bits in Address are set, then ASSERT().\r | |
942 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
943 | \r | |
944 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
945 | @param AndData The value to AND with the PCI configuration register.\r | |
946 | @param OrData The value to OR with the PCI configuration register.\r | |
947 | \r | |
948 | @return The value written to the PCI configuration register.\r | |
949 | \r | |
950 | **/\r | |
951 | UINT32\r | |
952 | EFIAPI\r | |
953 | S3PciSegmentAndThenOr32 (\r | |
954 | IN UINT64 Address,\r | |
955 | IN UINT32 AndData,\r | |
956 | IN UINT32 OrData\r | |
957 | )\r | |
958 | {\r | |
959 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));\r | |
960 | }\r | |
961 | \r | |
962 | /**\r | |
963 | Reads a bit field of a PCI configuration register, and saves the value in the\r | |
964 | S3 script to be replayed on S3 resume.\r | |
965 | \r | |
966 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
967 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
968 | returned.\r | |
969 | \r | |
970 | If any reserved bits in Address are set, then ASSERT().\r | |
971 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
972 | If StartBit is greater than 31, then ASSERT().\r | |
973 | If EndBit is greater than 31, then ASSERT().\r | |
974 | If EndBit is less than StartBit, then ASSERT().\r | |
975 | \r | |
976 | @param Address PCI configuration register to read.\r | |
977 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
978 | Range 0..31.\r | |
979 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
980 | Range 0..31.\r | |
981 | \r | |
982 | @return The value of the bit field read from the PCI configuration register.\r | |
983 | \r | |
984 | **/\r | |
985 | UINT32\r | |
986 | EFIAPI\r | |
987 | S3PciSegmentBitFieldRead32 (\r | |
988 | IN UINT64 Address,\r | |
989 | IN UINTN StartBit,\r | |
990 | IN UINTN EndBit\r | |
991 | )\r | |
992 | {\r | |
993 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));\r | |
994 | }\r | |
995 | \r | |
996 | /**\r | |
997 | Writes a bit field to a PCI configuration register, and saves the value in\r | |
998 | the S3 script to be replayed on S3 resume.\r | |
999 | \r | |
1000 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1001 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1002 | destination PCI configuration register are preserved. The new value of the\r | |
1003 | 32-bit register is returned.\r | |
1004 | \r | |
1005 | If any reserved bits in Address are set, then ASSERT().\r | |
1006 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1007 | If StartBit is greater than 31, then ASSERT().\r | |
1008 | If EndBit is greater than 31, then ASSERT().\r | |
1009 | If EndBit is less than StartBit, then ASSERT().\r | |
1010 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1011 | \r | |
1012 | @param Address PCI configuration register to write.\r | |
1013 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1014 | Range 0..31.\r | |
1015 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1016 | Range 0..31.\r | |
1017 | @param Value New value of the bit field.\r | |
1018 | \r | |
1019 | @return The value written back to the PCI configuration register.\r | |
1020 | \r | |
1021 | **/\r | |
1022 | UINT32\r | |
1023 | EFIAPI\r | |
1024 | S3PciSegmentBitFieldWrite32 (\r | |
1025 | IN UINT64 Address,\r | |
1026 | IN UINTN StartBit,\r | |
1027 | IN UINTN EndBit,\r | |
1028 | IN UINT32 Value\r | |
1029 | )\r | |
1030 | {\r | |
1031 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));\r | |
1032 | }\r | |
1033 | \r | |
1034 | /**\r | |
1035 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r | |
1036 | the result back to the bit field in the 32-bit port, and saves the value in the\r | |
1037 | S3 script to be replayed on S3 resume.\r | |
1038 | \r | |
1039 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1040 | bitwise OR between the read result and the value specified by\r | |
1041 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1042 | specified by Address. The value written to the PCI configuration register is\r | |
1043 | returned. This function must guarantee that all PCI read and write operations\r | |
1044 | are serialized. Extra left bits in OrData are stripped.\r | |
1045 | \r | |
1046 | If any reserved bits in Address are set, then ASSERT().\r | |
1047 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1048 | If StartBit is greater than 31, then ASSERT().\r | |
1049 | If EndBit is greater than 31, then ASSERT().\r | |
1050 | If EndBit is less than StartBit, then ASSERT().\r | |
1051 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1052 | \r | |
1053 | @param Address PCI configuration register to write.\r | |
1054 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1055 | Range 0..31.\r | |
1056 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1057 | Range 0..31.\r | |
1058 | @param OrData The value to OR with the PCI configuration register.\r | |
1059 | \r | |
1060 | @return The value written back to the PCI configuration register.\r | |
1061 | \r | |
1062 | **/\r | |
1063 | UINT32\r | |
1064 | EFIAPI\r | |
1065 | S3PciSegmentBitFieldOr32 (\r | |
1066 | IN UINT64 Address,\r | |
1067 | IN UINTN StartBit,\r | |
1068 | IN UINTN EndBit,\r | |
1069 | IN UINT32 OrData\r | |
1070 | )\r | |
1071 | {\r | |
1072 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));\r | |
1073 | }\r | |
1074 | \r | |
1075 | /**\r | |
1076 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1077 | AND, and writes the result back to the bit field in the 32-bit register, and\r | |
1078 | saves the value in the S3 script to be replayed on S3 resume.\r | |
1079 | \r | |
1080 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1081 | bitwise AND between the read result and the value specified by AndData, and\r | |
1082 | writes the result to the 32-bit PCI configuration register specified by\r | |
1083 | Address. The value written to the PCI configuration register is returned.\r | |
1084 | This function must guarantee that all PCI read and write operations are\r | |
1085 | serialized. Extra left bits in AndData are stripped.\r | |
1086 | \r | |
1087 | If any reserved bits in Address are set, then ASSERT().\r | |
1088 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1089 | If StartBit is greater than 31, then ASSERT().\r | |
1090 | If EndBit is greater than 31, then ASSERT().\r | |
1091 | If EndBit is less than StartBit, then ASSERT().\r | |
1092 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1093 | \r | |
1094 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
1095 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1096 | Range 0..31.\r | |
1097 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1098 | Range 0..31.\r | |
1099 | @param AndData The value to AND with the PCI configuration register.\r | |
1100 | \r | |
1101 | @return The value written back to the PCI configuration register.\r | |
1102 | \r | |
1103 | **/\r | |
1104 | UINT32\r | |
1105 | EFIAPI\r | |
1106 | S3PciSegmentBitFieldAnd32 (\r | |
1107 | IN UINT64 Address,\r | |
1108 | IN UINTN StartBit,\r | |
1109 | IN UINTN EndBit,\r | |
1110 | IN UINT32 AndData\r | |
1111 | )\r | |
1112 | {\r | |
1113 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r | |
1114 | }\r | |
1115 | \r | |
1116 | /**\r | |
1117 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1118 | bitwise OR, writes the result back to the bit field in the 32-bit port,\r | |
1119 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1120 | \r | |
1121 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1122 | bitwise AND followed by a bitwise OR between the read result and\r | |
1123 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1124 | configuration register specified by Address. The value written to the PCI\r | |
1125 | configuration register is returned. This function must guarantee that all PCI\r | |
1126 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1127 | OrData are stripped.\r | |
1128 | \r | |
1129 | If any reserved bits in Address are set, then ASSERT().\r | |
1130 | If StartBit is greater than 31, then ASSERT().\r | |
1131 | If EndBit is greater than 31, then ASSERT().\r | |
1132 | If EndBit is less than StartBit, then ASSERT().\r | |
1133 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1134 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1135 | \r | |
1136 | @param Address PCI configuration register to write.\r | |
1137 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1138 | Range 0..31.\r | |
1139 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1140 | Range 0..31.\r | |
1141 | @param AndData The value to AND with the PCI configuration register.\r | |
1142 | @param OrData The value to OR with the result of the AND operation.\r | |
1143 | \r | |
1144 | @return The value written back to the PCI configuration register.\r | |
1145 | \r | |
1146 | **/\r | |
1147 | UINT32\r | |
1148 | EFIAPI\r | |
1149 | S3PciSegmentBitFieldAndThenOr32 (\r | |
1150 | IN UINT64 Address,\r | |
1151 | IN UINTN StartBit,\r | |
1152 | IN UINTN EndBit,\r | |
1153 | IN UINT32 AndData,\r | |
1154 | IN UINT32 OrData\r | |
1155 | )\r | |
1156 | {\r | |
1157 | return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r | |
1158 | }\r | |
1159 | \r | |
1160 | /**\r | |
1161 | Reads a range of PCI configuration registers into a caller supplied buffer,\r | |
1162 | and saves the value in the S3 script to be replayed on S3 resume.\r | |
1163 | \r | |
1164 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1165 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1166 | configuration registers from a single PCI function to be read. Size is\r | |
1167 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1168 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1169 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1170 | end of the range.\r | |
1171 | \r | |
1172 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1173 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1174 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1175 | \r | |
1176 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1177 | Function and Register.\r | |
1178 | @param Size Size in bytes of the transfer.\r | |
1179 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1180 | \r | |
1181 | @return Size\r | |
1182 | \r | |
1183 | **/\r | |
1184 | UINTN\r | |
1185 | EFIAPI\r | |
1186 | S3PciSegmentReadBuffer (\r | |
1187 | IN UINT64 StartAddress,\r | |
1188 | IN UINTN Size,\r | |
1189 | OUT VOID *Buffer\r | |
1190 | )\r | |
1191 | {\r | |
1192 | RETURN_STATUS Status;\r | |
1193 | \r | |
1194 | Status = S3BootScriptSavePciCfg2Write (\r | |
1195 | S3BootScriptWidthUint8,\r | |
1196 | RShiftU64 (StartAddress, 32) & 0xffff,\r | |
1197 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r | |
1198 | PciSegmentReadBuffer (StartAddress, Size, Buffer),\r | |
1199 | Buffer\r | |
1200 | );\r | |
1201 | ASSERT_RETURN_ERROR (Status);\r | |
1202 | return Size;\r | |
1203 | }\r | |
1204 | \r | |
1205 | /**\r | |
1206 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1207 | configuration space, and saves the value in the S3 script to be replayed on S3\r | |
1208 | resume.\r | |
1209 | \r | |
1210 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1211 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1212 | configuration registers from a single PCI function to be written. Size is\r | |
1213 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1214 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1215 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1216 | and the end of the range.\r | |
1217 | \r | |
1218 | If any reserved bits in StartAddress are set, then ASSERT().\r | |
1219 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1220 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1221 | \r | |
1222 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r | |
1223 | Function and Register.\r | |
1224 | @param Size Size in bytes of the transfer.\r | |
1225 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1226 | \r | |
1227 | @return The parameter of Size.\r | |
1228 | \r | |
1229 | **/\r | |
1230 | UINTN\r | |
1231 | EFIAPI\r | |
1232 | S3PciSegmentWriteBuffer (\r | |
1233 | IN UINT64 StartAddress,\r | |
1234 | IN UINTN Size,\r | |
1235 | IN VOID *Buffer\r | |
1236 | )\r | |
1237 | {\r | |
1238 | RETURN_STATUS Status;\r | |
1239 | \r | |
1240 | Status = S3BootScriptSavePciCfg2Write (\r | |
1241 | S3BootScriptWidthUint8,\r | |
1242 | RShiftU64 (StartAddress, 32) & 0xffff,\r | |
1243 | PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r | |
1244 | PciSegmentWriteBuffer (StartAddress, Size, Buffer),\r | |
1245 | Buffer\r | |
1246 | );\r | |
1247 | ASSERT_RETURN_ERROR (Status);\r | |
1248 | return Size;\r | |
1249 | }\r |