MdePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / MdePkg / Library / BaseS3PciSegmentLib / S3PciSegmentLib.c

/** @file\r
  The multiple segments PCI configuration Library Services that carry out\r
  PCI configuration and enable the PCI operations to be replayed during an\r
  S3 resume. This library class maps directly on top of the PciSegmentLib class.\r
\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
\r
#include <Base.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/S3BootScriptLib.h>\r
#include <Library/PciSegmentLib.h>\r
\r
/**\r
  Macro that converts address in PciSegmentLib format to the new address that can be pass\r
  to the S3 Boot Script Library functions. The Segment is dropped.\r
\r
  @param Address  Address in PciSegmentLib format.\r
\r
  @retval New address that can be pass to the S3 Boot Script Library functions.\r
**/\r
#define PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS(Address) \\r
          ((((UINT32)(Address) >> 20) & 0xff) << 24) | \\r
          ((((UINT32)(Address) >> 15) & 0x1f) << 16) | \\r
          ((((UINT32)(Address) >> 12) & 0x07) <<  8) | \\r
          LShiftU64 ((Address) & 0xfff, 32)    // Always put Register in high four bytes.\r
\r
/**\r
  Saves a PCI configuration value to the boot script.\r
\r
  This internal worker function saves a PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Width   The width of PCI configuration.\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Buffer  The buffer containing value.\r
\r
**/\r
VOID\r
InternalSavePciSegmentWriteValueToBootScript (\r
  IN S3_BOOT_SCRIPT_LIB_WIDTH  Width,\r
  IN UINT64                 Address,\r
  IN VOID                   *Buffer\r
  )\r
{\r
  RETURN_STATUS                Status;\r
\r
  Status = S3BootScriptSavePciCfg2Write (\r
             Width,\r
             RShiftU64 ((Address), 32) & 0xffff,\r
             PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (Address),\r
             1,\r
             Buffer\r
             );\r
  ASSERT_RETURN_ERROR (Status);\r
}\r
\r
/**\r
  Saves an 8-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves an 8-bit PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value saved to boot script.\r
\r
  @return Value.\r
\r
**/\r
UINT8\r
InternalSavePciSegmentWrite8ValueToBootScript (\r
  IN UINT64             Address,\r
  IN UINT8              Value\r
  )\r
{\r
  InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint8, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads an 8-bit PCI configuration register, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Reads and returns the 8-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
  @return The 8-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentRead8 (\r
  IN UINT64                    Address\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentRead8 (Address));\r
}\r
\r
/**\r
  Writes an 8-bit PCI configuration register, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Writes the 8-bit PCI configuration register specified by Address with the value specified by Value.\r
  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
\r
  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  Value       The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentWrite8 (\r
  IN UINT64                    Address,\r
  IN UINT8                     Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentWrite8 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of an 8-bit PCI configuration register with an 8-bit value, and saves\r
  the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address,\r
  performs a bitwise OR between the read result and the value specified by OrData,\r
  and writes the result to the 8-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentOr8 (\r
  IN UINT64                    Address,\r
  IN UINT8                     OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentOr8 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  and writes the result to the 8-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
  If any reserved bits in Address are set, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentAnd8 (\r
  IN UINT64                    Address,\r
  IN UINT8                     AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAnd8 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r
  followed a bitwise OR with another 8-bit value, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
  and writes the result to the 8-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData    The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentAndThenOr8 (\r
  IN UINT64                    Address,\r
  IN UINT8                     AndData,\r
  IN UINT8                     OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentAndThenOr8 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldRead8 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldRead8 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register, and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  8-bit register is returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldWrite8 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT8                     Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldWrite8 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, writes\r
  the result back to the bit field in the 8-bit port, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 8-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldOr8 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT8                     OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldOr8 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
  AND, writes the result back to the bit field in the 8-bit register, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 8-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAnd8 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT8                     AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAnd8 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
  bitwise OR, writes the result back to the bit field in the 8-bit port,\r
  and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 8-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr8 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT8                     AndData,\r
  IN UINT8                     OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite8ValueToBootScript (Address, PciSegmentBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
/**\r
  Saves a 16-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves a 16-bit PCI configuration value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value saved to boot script.\r
\r
  @return Value.\r
\r
**/\r
UINT16\r
InternalSavePciSegmentWrite16ValueToBootScript (\r
  IN UINT64             Address,\r
  IN UINT16             Value\r
  )\r
{\r
  InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint16, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads a 16-bit PCI configuration register, and saves the value in the S3 script\r
  to be replayed on S3 resume.\r
\r
  Reads and returns the 16-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
  @return The 16-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentRead16 (\r
  IN UINT64                    Address\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentRead16 (Address));\r
}\r
\r
/**\r
  Writes a 16-bit PCI configuration register, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Writes the 16-bit PCI configuration register specified by Address with the value specified by Value.\r
  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  Value       The value to write.\r
\r
  @return The parameter of Value.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentWrite16 (\r
  IN UINT64                    Address,\r
  IN UINT16                    Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentWrite16 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of a 16-bit PCI configuration register with a 16-bit\r
  value, and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by OrData, and\r
  writes the result to the 16-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned. This function\r
  must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Segment, Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentOr16 (\r
  IN UINT64                    Address,\r
  IN UINT16                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentOr16 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  and writes the result to the 16-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentAnd16 (\r
  IN UINT64                    Address,\r
  IN UINT16                    AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAnd16 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value,\r
  followed a bitwise OR with another 16-bit value, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
  and writes the result to the 16-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentAndThenOr16 (\r
  IN UINT64                    Address,\r
  IN UINT16                    AndData,\r
  IN UINT16                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentAndThenOr16 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldRead16 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldRead16 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register, and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  16-bit register is returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldWrite16 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT16                    Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldWrite16 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, writes\r
  the result back to the bit field in the 16-bit port, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 16-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldOr16 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT16                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldOr16 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
  AND, writes the result back to the bit field in the 16-bit register, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 16-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAnd16 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT16                    AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAnd16 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
  bitwise OR, writes the result back to the bit field in the 16-bit port,\r
  and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 16-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr16 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT16                    AndData,\r
  IN UINT16                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite16ValueToBootScript (Address, PciSegmentBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
\r
\r
/**\r
  Saves a 32-bit PCI configuration value to the boot script.\r
\r
  This internal worker function saves a 32-bit PCI configuration value in the S3 script\r
  to be replayed on S3 resume.\r
\r
  If the saving process fails, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value saved to boot script.\r
\r
  @return Value.\r
\r
**/\r
UINT32\r
InternalSavePciSegmentWrite32ValueToBootScript (\r
  IN UINT64             Address,\r
  IN UINT32             Value\r
  )\r
{\r
  InternalSavePciSegmentWriteValueToBootScript (S3BootScriptWidthUint32, Address, &Value);\r
\r
  return Value;\r
}\r
\r
/**\r
  Reads a 32-bit PCI configuration register, and saves the value in the S3 script\r
  to be replayed on S3 resume.\r
\r
  Reads and returns the 32-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
\r
  @return The 32-bit PCI configuration register specified by Address.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentRead32 (\r
  IN UINT64                    Address\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentRead32 (Address));\r
}\r
\r
/**\r
  Writes a 32-bit PCI configuration register, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Writes the 32-bit PCI configuration register specified by Address with the value specified by Value.\r
  Value is returned.  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address     Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  Value       The value to write.\r
\r
  @return The parameter of Value.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentWrite32 (\r
  IN UINT64                    Address,\r
  IN UINT32                    Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentWrite32 (Address, Value));\r
}\r
\r
/**\r
  Performs a bitwise OR of a 32-bit PCI configuration register with a 32-bit\r
  value, and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by OrData, and\r
  writes the result to the 32-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned. This function\r
  must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and\r
                    Register.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentOr32 (\r
  IN UINT64                    Address,\r
  IN UINT32                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentOr32 (Address, OrData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  and writes the result to the 32-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentAnd32 (\r
  IN UINT64                    Address,\r
  IN UINT32                    AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAnd32 (Address, AndData));\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r
  followed a bitwise OR with another 32-bit value, and saves the value in the S3 script to\r
  be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address,\r
  performs a bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and the value specified by OrData,\r
  and writes the result to the 32-bit PCI configuration register specified by Address.\r
  The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are serialized.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentAndThenOr32 (\r
  IN UINT64                    Address,\r
  IN UINT32                    AndData,\r
  IN UINT32                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentAndThenOr32 (Address, AndData, OrData));\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldRead32 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldRead32 (Address, StartBit, EndBit));\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register, and saves the value in\r
  the S3 script to be replayed on S3 resume.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  32-bit register is returned.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldWrite32 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT32                    Value\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldWrite32 (Address, StartBit, EndBit, Value));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, writes\r
  the result back to the bit field in the 32-bit port, and saves the value in the\r
  S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 32-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldOr32 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT32                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldOr32 (Address, StartBit, EndBit, OrData));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 32-bit register, and\r
  saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 32-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAnd32 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT32                    AndData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAnd32 (Address, StartBit, EndBit, AndData));\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
  bitwise OR, writes the result back to the bit field in the 32-bit port,\r
  and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 32-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If any reserved bits in Address are set, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
  If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
  If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
S3PciSegmentBitFieldAndThenOr32 (\r
  IN UINT64                    Address,\r
  IN UINTN                     StartBit,\r
  IN UINTN                     EndBit,\r
  IN UINT32                    AndData,\r
  IN UINT32                    OrData\r
  )\r
{\r
  return InternalSavePciSegmentWrite32ValueToBootScript (Address, PciSegmentBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData));\r
}\r
\r
/**\r
  Reads a range of PCI configuration registers into a caller supplied buffer,\r
  and saves the value in the S3 script to be replayed on S3 resume.\r
\r
  Reads the range of PCI configuration registers specified by StartAddress and\r
  Size into the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be read. Size is\r
  returned. When possible 32-bit PCI configuration read cycles are used to read\r
  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
  and 16-bit PCI configuration read cycles may be used at the beginning and the\r
  end of the range.\r
\r
  If any reserved bits in StartAddress are set, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer receiving the data read.\r
\r
  @return Size\r
\r
**/\r
UINTN\r
EFIAPI\r
S3PciSegmentReadBuffer (\r
  IN  UINT64                   StartAddress,\r
  IN  UINTN                    Size,\r
  OUT VOID                     *Buffer\r
  )\r
{\r
  RETURN_STATUS    Status;\r
\r
  Status = S3BootScriptSavePciCfg2Write (\r
             S3BootScriptWidthUint8,\r
             RShiftU64 (StartAddress, 32) & 0xffff,\r
             PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r
             PciSegmentReadBuffer (StartAddress, Size, Buffer),\r
             Buffer\r
             );\r
  ASSERT_RETURN_ERROR (Status);\r
  return Size;\r
}\r
\r
/**\r
  Copies the data in a caller supplied buffer to a specified range of PCI\r
  configuration space, and saves the value in the S3 script to be replayed on S3\r
  resume.\r
\r
  Writes the range of PCI configuration registers specified by StartAddress and\r
  Size from the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be written. Size is\r
  returned. When possible 32-bit PCI configuration write cycles are used to\r
  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
  8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
  and the end of the range.\r
\r
  If any reserved bits in StartAddress are set, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Segment, Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer containing the data to write.\r
\r
  @return The parameter of Size.\r
\r
**/\r
UINTN\r
EFIAPI\r
S3PciSegmentWriteBuffer (\r
  IN UINT64                    StartAddress,\r
  IN UINTN                     Size,\r
  IN VOID                      *Buffer\r
  )\r
{\r
  RETURN_STATUS    Status;\r
\r
  Status = S3BootScriptSavePciCfg2Write (\r
             S3BootScriptWidthUint8,\r
             RShiftU64 (StartAddress, 32) & 0xffff,\r
             PCI_SEGMENT_LIB_ADDRESS_TO_S3_BOOT_SCRIPT_PCI_ADDRESS (StartAddress),\r
             PciSegmentWriteBuffer (StartAddress, Size, Buffer),\r
             Buffer\r
             );\r
  ASSERT_RETURN_ERROR (Status);\r
  return Size;\r
}\r