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1 | /** @file\r |
| 2 | Base SMBUS library implementation built upon I/O library.\r |
| 3 | \r |
| 4 | Copyright (c) 2006, Intel Corporation<BR>\r |
| 5 | All rights reserved. This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| 13 | Module Name: SmbusLib.h\r |
| 14 | \r |
| 15 | **/\r |
| 16 | \r |
| 17 | #ifndef __SMBUS_LIB_REGISTER_H\r |
| 18 | #define __SMBUS_LIB_REGISTER_H\r |
| 19 | \r |
| 20 | #define SMBUS_R_HST_STS 0x00 // Host Status Register\r |
| 21 | #define SMBUS_B_HOST_BUSY 0x01 // RO\r |
| 22 | #define SMBUS_B_INTR 0x02 // R/WC\r |
| 23 | #define SMBUS_B_DEV_ERR 0x04 // R/WC\r |
| 24 | #define SMBUS_B_BUS_ERR 0x08 // R/WC\r |
| 25 | #define SMBUS_B_FAILED 0x10 // R/WC\r |
| 26 | #define SMBUS_B_SMBALERT_STS 0x20 // R/WC\r |
| 27 | #define SMBUS_B_INUSE_STS 0x40 // R/WC\r |
| 28 | #define SMBUS_B_BYTE_DONE_STS 0x80 // R/WC\r |
| 29 | #define SMBUS_B_ERROR (SMBUS_B_DEV_ERR | SMBUS_B_BUS_ERR | SMBUS_B_FAILED)\r |
| 30 | #define SMBUS_B_HSTS_ALL 0xFF // R/WC\r |
| 31 | \r |
| 32 | \r |
| 33 | #define SMBUS_R_HST_CTL 0x02 // Host Control Register R/W\r |
| 34 | #define SMBUS_B_INTREN 0x01 // RW\r |
| 35 | #define SMBUS_B_KILL 0x02 // RW\r |
| 36 | #define SMBUS_B_CMD (7 << 2) // RW\r |
| 37 | #define SMBUS_V_SMB_CMD_QUICK (0 << 2)\r |
| 38 | #define SMBUS_V_SMB_CMD_BYTE (1 << 2)\r |
| 39 | #define SMBUS_V_SMB_CMD_BYTE_DATA (2 << 2)\r |
| 40 | #define SMBUS_V_SMB_CMD_WORD_DATA (3 << 2)\r |
| 41 | #define SMBUS_V_SMB_CMD_PROCESS_CALL (4 << 2)\r |
| 42 | #define SMBUS_V_SMB_CMD_BLOCK (5 << 2)\r |
| 43 | #define SMBUS_V_SMB_CMD_IIC_READ (6 << 2)\r |
| 44 | #define SMBUS_V_SMB_CMD_BLOCK_PROCESS (7 << 2)\r |
| 45 | #define SMBUS_B_LAST_BYTE 0x20 // WO\r |
| 46 | #define SMBUS_B_START 0x40 // WO\r |
| 47 | #define SMBUS_B_PEC_EN 0x80 // RW\r |
| 48 | \r |
| 49 | \r |
| 50 | #define SMBUS_R_HST_CMD 0x03 // Host Command Register R/W\r |
| 51 | \r |
| 52 | \r |
| 53 | #define SMBUS_R_XMIT_SLVA 0x04 // Transmit Slave Address Register R/W\r |
| 54 | #define SMBUS_B_RW 0x01 // RW\r |
| 55 | #define SMBUS_B_READ 0x01 // RW\r |
| 56 | #define SMBUS_B_WRITE 0x00 // RW\r |
| 57 | #define SMBUS_B_ADDRESS 0xFE // RW\r |
| 58 | \r |
| 59 | \r |
| 60 | #define SMBUS_R_HST_D0 0x05 // Data 0 Register R/W\r |
| 61 | \r |
| 62 | \r |
| 63 | #define SMBUS_R_HST_D1 0x06 // Data 1 Register R/W\r |
| 64 | \r |
| 65 | \r |
| 66 | #define SMBUS_R_HOST_BLOCK_DB 0x07 // Host Block Data Register R/W\r |
| 67 | \r |
| 68 | \r |
| 69 | #define SMBUS_R_PEC 0x08 // Packet Error Check Data Register R/W\r |
| 70 | \r |
| 71 | \r |
| 72 | #define SMBUS_R_RCV_SLVA 0x09 // Receive Slave Address Register R/W\r |
| 73 | #define SMBUS_B_SLAVE_ADDR 0x7F // RW\r |
| 74 | \r |
| 75 | \r |
| 76 | #define SMBUS_R_SLV_DATA 0x0A // Receive Slave Data Register R/W\r |
| 77 | \r |
| 78 | \r |
| 79 | #define SMBUS_R_AUX_STS 0x0C // Auxiliary Status Register R/WC\r |
| 80 | #define SMBUS_B_CRCE 0x01 // R/WC\r |
| 81 | \r |
| 82 | \r |
| 83 | #define SMBUS_R_AUX_CTL 0x0D // Auxiliary Control Register R/W\r |
| 84 | #define SMBUS_B_AAC 0x01 // R/W\r |
| 85 | #define SMBUS_B_E32B 0x02 // R/W\r |
| 86 | \r |
| 87 | \r |
| 88 | #define SMBUS_R_SMLINK_PIN_CTL 0x0E // SMLINK Pin Control Register R/W\r |
| 89 | #define SMBUS_B_SMLINK0_CUR_STS 0x01 // RO\r |
| 90 | #define SMBUS_B_SMLINK1_CUR_STS 0x02 // RO\r |
| 91 | #define SMBUS_B_SMLINK_CLK_CTL 0x04 // RW\r |
| 92 | \r |
| 93 | \r |
| 94 | #define SMBUS_R_SMBUS_PIN_CTL 0x0F // SMBus Pin Control Register R/W\r |
| 95 | #define SMBUS_B_SMBCLK_CUR_STS 0x01 // RO\r |
| 96 | #define SMBUS_B_SMBDATA_CUR_STS 0x02 // RO\r |
| 97 | #define SMBUS_B_SMBCLK_CTL 0x04 // RW\r |
| 98 | \r |
| 99 | \r |
| 100 | #define SMBUS_R_SLV_STS 0x10 // Slave Status Register R/WC\r |
| 101 | #define SMBUS_B_HOST_NOTIFY_STS 0x01 // R/WC\r |
| 102 | \r |
| 103 | \r |
| 104 | #define SMBUS_R_SLV_CMD 0x11 // Slave Command Register R/W\r |
| 105 | #define SMBUS_B_HOST_NOTIFY_INTREN 0x01 // R/W\r |
| 106 | #define SMBUS_B_HOST_NOTIFY_WKEN 0x02 // R/W\r |
| 107 | #define SMBUS_B_SMBALERT_DIS 0x04 // R/W\r |
| 108 | \r |
| 109 | \r |
| 110 | #define SMBUS_R_NOTIFY_DADDR 0x14 // Notify Device Address Register RO\r |
| 111 | #define SMBUS_B_DEVICE_ADDRESS 0xFE // RO\r |
| 112 | \r |
| 113 | \r |
| 114 | #define SMBUS_R_NOTIFY_DLOW 0x16 // Notify Data Low Byte Register RO\r |
| 115 | \r |
| 116 | \r |
| 117 | #define SMBUS_R_NOTIFY_DHIGH 0x17 // Notify Data High Byte Register RO \r |
| 118 | \r |
| 119 | \r |
| 120 | #endif\r |
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