MdePkg: Replace BSD License with BSD+Patent License

[mirror_edk2.git] / MdePkg / Library / BaseSynchronizationLib / Ia32 / InternalGetSpinLockProperties.c

/** @file\r
  Internal function to get spin lock alignment.\r
\r
  Copyright (c) 2016 - 2018, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include "BaseSynchronizationLibInternals.h"\r
\r
/**\r
  Internal function to retrieve the architecture specific spin lock alignment\r
  requirements for optimal spin lock performance.\r
\r
  @return The architecture specific spin lock alignment.\r
\r
**/\r
UINTN\r
InternalGetSpinLockProperties (\r
  VOID\r
  )\r
{\r
  UINT32  RegEax;\r
  UINT32  RegEbx;\r
  UINTN   FamilyId;\r
  UINTN   ModelId;\r
  UINTN   CacheLineSize;\r
\r
  //\r
  // Retrieve CPUID Version Information\r
  //\r
  AsmCpuid (0x01, &RegEax, &RegEbx, NULL, NULL);\r
  //\r
  // EBX: Bits 15 - 08: CLFLUSH line size (Value * 8 = cache line size)\r
  //\r
  CacheLineSize = ((RegEbx >> 8) & 0xff) * 8;\r
  //\r
  // Retrieve CPU Family and Model\r
  //\r
  FamilyId = (RegEax >> 8) & 0xf;\r
  ModelId  = (RegEax >> 4) & 0xf;\r
  if (FamilyId == 0x0f) {\r
    //\r
    // In processors based on Intel NetBurst microarchitecture, use two cache lines\r
    //\r
    ModelId = ModelId | ((RegEax >> 12) & 0xf0);\r
    if (ModelId <= 0x04 || ModelId == 0x06) {\r
      CacheLineSize *= 2;\r
    }\r
  }\r
\r
  if (CacheLineSize < 32) {\r
    CacheLineSize = 32;\r
  }\r
\r
  return CacheLineSize;\r
}\r
\r