| 1a3eaf06 |
1 | /** @file\r |
| 2 | Functions accessing PCI configuration registers on any supported PCI segment\r |
| 3 | \r |
| 4 | Copyright (c) 2007 - 2008, Intel Corporation All rights\r |
| 5 | reserved. This program and the accompanying materials are\r |
| 6 | licensed and made available under the terms and conditions of\r |
| 7 | the BSD License which accompanies this distribution. The full\r |
| 8 | text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
| 14 | **/\r |
| 15 | \r |
| 16 | #include "PciSegmentLib.h"\r |
| 17 | \r |
| 18 | //\r |
| 19 | // Global varible to record data of PCI Root Bridge I/O Protcol instances\r |
| 20 | //\r |
| 21 | PCI_ROOT_BRIDGE_DATA *mPciRootBridgeData = NULL;\r |
| 22 | UINTN mNumberOfPciRootBridges = 0;\r |
| 23 | \r |
| 24 | /**\r |
| 25 | The constructor function caches data of PCI Root Bridge I/O Protcol instances.\r |
| 26 | \r |
| 27 | The constructor function locates PCI Root Bridge I/O protocol instances,\r |
| 28 | and caches the protocol instances, together with their segment numbers and bus ranges.\r |
| 29 | It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS. \r |
| 30 | \r |
| 31 | @param ImageHandle The firmware allocated handle for the EFI image.\r |
| 32 | @param SystemTable A pointer to the EFI System Table.\r |
| 33 | \r |
| 34 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r |
| 35 | \r |
| 36 | **/\r |
| 37 | EFI_STATUS\r |
| 38 | EFIAPI\r |
| 39 | PciSegmentLibConstructor (\r |
| 40 | IN EFI_HANDLE ImageHandle,\r |
| 41 | IN EFI_SYSTEM_TABLE *SystemTable\r |
| 42 | )\r |
| 43 | {\r |
| 44 | EFI_STATUS Status;\r |
| 45 | UINTN Index;\r |
| 46 | UINTN HandleCount;\r |
| 47 | EFI_HANDLE *HandleBuffer;\r |
| 48 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r |
| 49 | EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR *Descriptors;\r |
| 50 | \r |
| 51 | HandleCount = 0;\r |
| 52 | HandleBuffer = NULL;\r |
| 53 | PciRootBridgeIo = NULL;\r |
| 54 | Descriptors = NULL;\r |
| 55 | \r |
| 56 | Status = gBS->LocateHandleBuffer (\r |
| 57 | ByProtocol,\r |
| 58 | &gEfiPciRootBridgeIoProtocolGuid,\r |
| 59 | NULL,\r |
| 60 | &HandleCount,\r |
| 61 | &HandleBuffer\r |
| 62 | );\r |
| 63 | ASSERT_EFI_ERROR (Status);\r |
| 64 | \r |
| 65 | mNumberOfPciRootBridges = HandleCount;\r |
| 66 | \r |
| 67 | mPciRootBridgeData = AllocatePool (HandleCount * sizeof (PCI_ROOT_BRIDGE_DATA));\r |
| 68 | ASSERT (mPciRootBridgeData != NULL);\r |
| 69 | \r |
| 70 | //\r |
| 71 | // Traverse all PCI Root Bridge I/O Protocol instances, and record the protocol\r |
| 72 | // instances, together with their segment numbers and bus ranges.\r |
| 73 | //\r |
| 74 | for (Index = 0; Index < HandleCount; Index++) {\r |
| 75 | Status = gBS->HandleProtocol (\r |
| 76 | HandleBuffer[Index],\r |
| 77 | &gEfiPciRootBridgeIoProtocolGuid,\r |
| 78 | (VOID **) &PciRootBridgeIo\r |
| 79 | );\r |
| 80 | ASSERT_EFI_ERROR (Status);\r |
| 81 | \r |
| 82 | mPciRootBridgeData[Index].PciRootBridgeIo = PciRootBridgeIo;\r |
| 83 | mPciRootBridgeData[Index].SegmentNumber = PciRootBridgeIo->SegmentNumber;\r |
| 84 | \r |
| 85 | Status = PciRootBridgeIo->Configuration (PciRootBridgeIo, (VOID **) &Descriptors);\r |
| 86 | ASSERT_EFI_ERROR (Status);\r |
| 87 | \r |
| 88 | while (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR) {\r |
| 89 | if (Descriptors->ResType == ACPI_ADDRESS_SPACE_TYPE_BUS) {\r |
| 90 | mPciRootBridgeData[Index].MinBusNumber = Descriptors->AddrRangeMin;\r |
| 91 | mPciRootBridgeData[Index].MaxBusNumber = Descriptors->AddrRangeMax;\r |
| 92 | break;\r |
| 93 | }\r |
| 94 | Descriptors++;\r |
| 95 | }\r |
| 96 | ASSERT (Descriptors->Desc != ACPI_END_TAG_DESCRIPTOR);\r |
| 97 | }\r |
| 98 | \r |
| 99 | Status = gBS->FreePool(HandleBuffer);\r |
| 100 | ASSERT_EFI_ERROR (Status);\r |
| 101 | \r |
| 102 | return EFI_SUCCESS;\r |
| 103 | }\r |
| 104 | \r |
| 105 | /**\r |
| 106 | The destructor function frees memory allocated by constructor.\r |
| 107 | \r |
| 108 | The destructor function frees memory for data of protocol instances allocated by constructor.\r |
| 109 | It will ASSERT() if that related operation fails and it will always return EFI_SUCCESS. \r |
| 110 | \r |
| 111 | @param ImageHandle The firmware allocated handle for the EFI image.\r |
| 112 | @param SystemTable A pointer to the EFI System Table.\r |
| 113 | \r |
| 114 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r |
| 115 | \r |
| 116 | **/\r |
| 117 | EFI_STATUS\r |
| 118 | EFIAPI\r |
| 119 | PciSegmentLibDestructor (\r |
| 120 | IN EFI_HANDLE ImageHandle,\r |
| 121 | IN EFI_SYSTEM_TABLE *SystemTable\r |
| 122 | )\r |
| 123 | {\r |
| 124 | FreePool (mPciRootBridgeData);\r |
| 125 | \r |
| 126 | return EFI_SUCCESS;\r |
| 127 | }\r |
| 128 | \r |
| 129 | /**\r |
| 130 | According to address, search for the corresponding PCI Root Bridge I/O Protocol instance.\r |
| 131 | \r |
| 132 | This internal function extracts segment number and bus number data from address, and\r |
| 133 | retrieves the corresponding PCI Root Bridge I/O Protocol instance.\r |
| 134 | \r |
| 135 | @param Address Address that encodes the Segment, PCI Bus, Device, Function and\r |
| 136 | Register.\r |
| 137 | \r |
| 138 | @return The address for PCI Root Bridge I/O Protocol.\r |
| 139 | \r |
| 140 | **/\r |
| 141 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *\r |
| 142 | PciSegmentLibSearchForRootBridge (\r |
| 143 | IN UINT64 Address\r |
| 144 | )\r |
| 145 | {\r |
| 146 | UINTN Index;\r |
| 147 | UINT64 SegmentNumber;\r |
| 148 | UINT64 BusNumber;\r |
| 149 | \r |
| 150 | for (Index = 0; Index < mNumberOfPciRootBridges; Index++) {\r |
| 151 | //\r |
| 152 | // Matches segment number of address with the segment number of protocol instance.\r |
| 153 | //\r |
| 154 | SegmentNumber = BitFieldRead64 (Address, 32, 63);\r |
| 155 | if (SegmentNumber == mPciRootBridgeData[Index].SegmentNumber) {\r |
| 156 | //\r |
| 157 | // Matches the bus number of address with bus number range of protocol instance.\r |
| 158 | //\r |
| 159 | BusNumber = BitFieldRead64 (Address, 20, 27);\r |
| 160 | if (BusNumber >= mPciRootBridgeData[Index].MinBusNumber && BusNumber <= mPciRootBridgeData[Index].MaxBusNumber) {\r |
| 161 | return mPciRootBridgeData[Index].PciRootBridgeIo;\r |
| 162 | }\r |
| 163 | } \r |
| 164 | }\r |
| 165 | return NULL;\r |
| 166 | }\r |
| 167 | \r |
| 168 | /**\r |
| 169 | Internal worker function to read a PCI configuration register.\r |
| 170 | \r |
| 171 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.\r |
| 172 | It reads and returns the PCI configuration register specified by Address,\r |
| 173 | the width of data is specified by Width.\r |
| 174 | \r |
| 175 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 176 | Register.\r |
| 177 | @param Width Width of data to read\r |
| 178 | \r |
| 179 | @return The value read from the PCI configuration register.\r |
| 180 | \r |
| 181 | **/\r |
| 182 | UINT32\r |
| 183 | DxePciSegmentLibPciRootBridgeIoReadWorker (\r |
| 184 | IN UINT64 Address,\r |
| 185 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width\r |
| 186 | )\r |
| 187 | {\r |
| 188 | UINT32 Data;\r |
| 189 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r |
| 190 | \r |
| 191 | PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r |
| 192 | ASSERT (PciRootBridgeIo != NULL);\r |
| 193 | \r |
| 194 | PciRootBridgeIo->Pci.Read (\r |
| 195 | PciRootBridgeIo,\r |
| 196 | Width,\r |
| 197 | PCI_TO_PCICFG2_ADDRESS (Address),\r |
| 198 | 1,\r |
| 199 | &Data\r |
| 200 | );\r |
| 201 | \r |
| 202 | return Data;\r |
| 203 | }\r |
| 204 | \r |
| 205 | /**\r |
| 206 | Internal worker function to writes a PCI configuration register.\r |
| 207 | \r |
| 208 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r |
| 209 | It writes the PCI configuration register specified by Address with the\r |
| 210 | value specified by Data. The width of data is specifed by Width.\r |
| 211 | Data is returned.\r |
| 212 | \r |
| 213 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 214 | Register.\r |
| 215 | @param Width Width of data to write\r |
| 216 | @param Data The value to write.\r |
| 217 | \r |
| 218 | @return The value written to the PCI configuration register.\r |
| 219 | \r |
| 220 | **/\r |
| 221 | UINT32\r |
| 222 | DxePciSegmentLibPciRootBridgeIoWriteWorker (\r |
| 223 | IN UINT64 Address,\r |
| 224 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r |
| 225 | IN UINT32 Data\r |
| 226 | )\r |
| 227 | {\r |
| 228 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo; \r |
| 229 | \r |
| 230 | PciRootBridgeIo = PciSegmentLibSearchForRootBridge (Address);\r |
| 231 | ASSERT (PciRootBridgeIo != NULL);\r |
| 232 | \r |
| 233 | PciRootBridgeIo->Pci.Write (\r |
| 234 | PciRootBridgeIo,\r |
| 235 | Width,\r |
| 236 | PCI_TO_PCICFG2_ADDRESS (Address),\r |
| 237 | 1,\r |
| 238 | &Data\r |
| 239 | );\r |
| 240 | \r |
| 241 | return Data;\r |
| 242 | }\r |
| 243 | \r |
| 244 | /**\r |
| 245 | Reads an 8-bit PCI configuration register.\r |
| 246 | \r |
| 247 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 248 | This function must guarantee that all PCI read and write operations are\r |
| 249 | serialized.\r |
| 250 | \r |
| 251 | If any reserved bits in Address are set, then ASSERT().\r |
| 252 | \r |
| 253 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 254 | Register.\r |
| 255 | \r |
| 256 | @return The value read from the PCI configuration register.\r |
| 257 | \r |
| 258 | **/\r |
| 259 | UINT8\r |
| 260 | EFIAPI\r |
| 261 | PciSegmentRead8 (\r |
| 262 | IN UINT64 Address\r |
| 263 | )\r |
| 264 | {\r |
| 265 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r |
| 266 | \r |
| 267 | return (UINT8) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r |
| 268 | }\r |
| 269 | \r |
| 270 | /**\r |
| 271 | Writes an 8-bit PCI configuration register.\r |
| 272 | \r |
| 273 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 274 | value specified by Value. Value is returned. This function must guarantee\r |
| 275 | that all PCI read and write operations are serialized.\r |
| 276 | \r |
| 277 | If any reserved bits in Address are set, then ASSERT().\r |
| 278 | \r |
| 279 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 280 | Register.\r |
| 281 | @param Data The value to write.\r |
| 282 | \r |
| 283 | @return The value written to the PCI configuration register.\r |
| 284 | \r |
| 285 | **/\r |
| 286 | UINT8\r |
| 287 | EFIAPI\r |
| 288 | PciSegmentWrite8 (\r |
| 289 | IN UINT64 Address,\r |
| 290 | IN UINT8 Data\r |
| 291 | )\r |
| 292 | {\r |
| 293 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r |
| 294 | \r |
| 295 | return (UINT8) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r |
| 296 | }\r |
| 297 | \r |
| 298 | /**\r |
| 299 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 300 | an 8-bit value.\r |
| 301 | \r |
| 302 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 303 | bitwise inclusive OR between the read result and the value specified by\r |
| 304 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 305 | specified by Address. The value written to the PCI configuration register is\r |
| 306 | returned. This function must guarantee that all PCI read and write operations\r |
| 307 | are serialized.\r |
| 308 | \r |
| 309 | If any reserved bits in Address are set, then ASSERT().\r |
| 310 | \r |
| 311 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 312 | Register.\r |
| 313 | @param OrData The value to OR with the PCI configuration register.\r |
| 314 | \r |
| 315 | @return The value written back to the PCI configuration register.\r |
| 316 | \r |
| 317 | **/\r |
| 318 | UINT8\r |
| 319 | EFIAPI\r |
| 320 | PciSegmentOr8 (\r |
| 321 | IN UINT64 Address,\r |
| 322 | IN UINT8 OrData\r |
| 323 | )\r |
| 324 | {\r |
| 325 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r |
| 326 | }\r |
| 327 | \r |
| 328 | /**\r |
| 329 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 330 | value.\r |
| 331 | \r |
| 332 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 333 | bitwise AND between the read result and the value specified by AndData, and\r |
| 334 | writes the result to the 8-bit PCI configuration register specified by\r |
| 335 | Address. The value written to the PCI configuration register is returned.\r |
| 336 | This function must guarantee that all PCI read and write operations are\r |
| 337 | serialized.\r |
| 338 | \r |
| 339 | If any reserved bits in Address are set, then ASSERT().\r |
| 340 | \r |
| 341 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 342 | Register.\r |
| 343 | @param AndData The value to AND with the PCI configuration register.\r |
| 344 | \r |
| 345 | @return The value written back to the PCI configuration register.\r |
| 346 | \r |
| 347 | **/\r |
| 348 | UINT8\r |
| 349 | EFIAPI\r |
| 350 | PciSegmentAnd8 (\r |
| 351 | IN UINT64 Address,\r |
| 352 | IN UINT8 AndData\r |
| 353 | )\r |
| 354 | {\r |
| 355 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r |
| 356 | }\r |
| 357 | \r |
| 358 | /**\r |
| 359 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 360 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 361 | \r |
| 362 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 363 | bitwise AND between the read result and the value specified by AndData,\r |
| 364 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 365 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 366 | configuration register specified by Address. The value written to the PCI\r |
| 367 | configuration register is returned. This function must guarantee that all PCI\r |
| 368 | read and write operations are serialized.\r |
| 369 | \r |
| 370 | If any reserved bits in Address are set, then ASSERT().\r |
| 371 | \r |
| 372 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 373 | Register.\r |
| 374 | @param AndData The value to AND with the PCI configuration register.\r |
| 375 | @param OrData The value to OR with the result of the AND operation.\r |
| 376 | \r |
| 377 | @return The value written back to the PCI configuration register.\r |
| 378 | \r |
| 379 | **/\r |
| 380 | UINT8\r |
| 381 | EFIAPI\r |
| 382 | PciSegmentAndThenOr8 (\r |
| 383 | IN UINT64 Address,\r |
| 384 | IN UINT8 AndData,\r |
| 385 | IN UINT8 OrData\r |
| 386 | )\r |
| 387 | {\r |
| 388 | return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r |
| 389 | }\r |
| 390 | \r |
| 391 | /**\r |
| 392 | Reads a bit field of a PCI configuration register.\r |
| 393 | \r |
| 394 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 395 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 396 | returned.\r |
| 397 | \r |
| 398 | If any reserved bits in Address are set, then ASSERT().\r |
| 399 | If StartBit is greater than 7, then ASSERT().\r |
| 400 | If EndBit is greater than 7, then ASSERT().\r |
| 401 | If EndBit is less than StartBit, then ASSERT().\r |
| 402 | \r |
| 403 | @param Address PCI configuration register to read.\r |
| 404 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 405 | Range 0..7.\r |
| 406 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 407 | Range 0..7.\r |
| 408 | \r |
| 409 | @return The value of the bit field read from the PCI configuration register.\r |
| 410 | \r |
| 411 | **/\r |
| 412 | UINT8\r |
| 413 | EFIAPI\r |
| 414 | PciSegmentBitFieldRead8 (\r |
| 415 | IN UINT64 Address,\r |
| 416 | IN UINTN StartBit,\r |
| 417 | IN UINTN EndBit\r |
| 418 | )\r |
| 419 | {\r |
| 420 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r |
| 421 | }\r |
| 422 | \r |
| 423 | /**\r |
| 424 | Writes a bit field to a PCI configuration register.\r |
| 425 | \r |
| 426 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 427 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 428 | destination PCI configuration register are preserved. The new value of the\r |
| 429 | 8-bit register is returned.\r |
| 430 | \r |
| 431 | If any reserved bits in Address are set, then ASSERT().\r |
| 432 | If StartBit is greater than 7, then ASSERT().\r |
| 433 | If EndBit is greater than 7, then ASSERT().\r |
| 434 | If EndBit is less than StartBit, then ASSERT().\r |
| 435 | \r |
| 436 | @param Address PCI configuration register to write.\r |
| 437 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 438 | Range 0..7.\r |
| 439 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 440 | Range 0..7.\r |
| 441 | @param Value New value of the bit field.\r |
| 442 | \r |
| 443 | @return The value written back to the PCI configuration register.\r |
| 444 | \r |
| 445 | **/\r |
| 446 | UINT8\r |
| 447 | EFIAPI\r |
| 448 | PciSegmentBitFieldWrite8 (\r |
| 449 | IN UINT64 Address,\r |
| 450 | IN UINTN StartBit,\r |
| 451 | IN UINTN EndBit,\r |
| 452 | IN UINT8 Value\r |
| 453 | )\r |
| 454 | {\r |
| 455 | return PciSegmentWrite8 (\r |
| 456 | Address,\r |
| 457 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r |
| 458 | );\r |
| 459 | }\r |
| 460 | \r |
| 461 | /**\r |
| 462 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 463 | writes the result back to the bit field in the 8-bit port.\r |
| 464 | \r |
| 465 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 466 | bitwise inclusive OR between the read result and the value specified by\r |
| 467 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 468 | specified by Address. The value written to the PCI configuration register is\r |
| 469 | returned. This function must guarantee that all PCI read and write operations\r |
| 470 | are serialized. Extra left bits in OrData are stripped.\r |
| 471 | \r |
| 472 | If any reserved bits in Address are set, then ASSERT().\r |
| 473 | If StartBit is greater than 7, then ASSERT().\r |
| 474 | If EndBit is greater than 7, then ASSERT().\r |
| 475 | If EndBit is less than StartBit, then ASSERT().\r |
| 476 | \r |
| 477 | @param Address PCI configuration register to write.\r |
| 478 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 479 | Range 0..7.\r |
| 480 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 481 | Range 0..7.\r |
| 482 | @param OrData The value to OR with the PCI configuration register.\r |
| 483 | \r |
| 484 | @return The value written back to the PCI configuration register.\r |
| 485 | \r |
| 486 | **/\r |
| 487 | UINT8\r |
| 488 | EFIAPI\r |
| 489 | PciSegmentBitFieldOr8 (\r |
| 490 | IN UINT64 Address,\r |
| 491 | IN UINTN StartBit,\r |
| 492 | IN UINTN EndBit,\r |
| 493 | IN UINT8 OrData\r |
| 494 | )\r |
| 495 | {\r |
| 496 | return PciSegmentWrite8 (\r |
| 497 | Address,\r |
| 498 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r |
| 499 | );\r |
| 500 | }\r |
| 501 | \r |
| 502 | /**\r |
| 503 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 504 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 505 | \r |
| 506 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 507 | bitwise AND between the read result and the value specified by AndData, and\r |
| 508 | writes the result to the 8-bit PCI configuration register specified by\r |
| 509 | Address. The value written to the PCI configuration register is returned.\r |
| 510 | This function must guarantee that all PCI read and write operations are\r |
| 511 | serialized. Extra left bits in AndData are stripped.\r |
| 512 | \r |
| 513 | If any reserved bits in Address are set, then ASSERT().\r |
| 514 | If StartBit is greater than 7, then ASSERT().\r |
| 515 | If EndBit is greater than 7, then ASSERT().\r |
| 516 | If EndBit is less than StartBit, then ASSERT().\r |
| 517 | \r |
| 518 | @param Address PCI configuration register to write.\r |
| 519 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 520 | Range 0..7.\r |
| 521 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 522 | Range 0..7.\r |
| 523 | @param AndData The value to AND with the PCI configuration register.\r |
| 524 | \r |
| 525 | @return The value written back to the PCI configuration register.\r |
| 526 | \r |
| 527 | **/\r |
| 528 | UINT8\r |
| 529 | EFIAPI\r |
| 530 | PciSegmentBitFieldAnd8 (\r |
| 531 | IN UINT64 Address,\r |
| 532 | IN UINTN StartBit,\r |
| 533 | IN UINTN EndBit,\r |
| 534 | IN UINT8 AndData\r |
| 535 | )\r |
| 536 | {\r |
| 537 | return PciSegmentWrite8 (\r |
| 538 | Address,\r |
| 539 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r |
| 540 | );\r |
| 541 | }\r |
| 542 | \r |
| 543 | /**\r |
| 544 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 545 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 546 | 8-bit port.\r |
| 547 | \r |
| 548 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 549 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 550 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 551 | configuration register specified by Address. The value written to the PCI\r |
| 552 | configuration register is returned. This function must guarantee that all PCI\r |
| 553 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 554 | OrData are stripped.\r |
| 555 | \r |
| 556 | If any reserved bits in Address are set, then ASSERT().\r |
| 557 | If StartBit is greater than 7, then ASSERT().\r |
| 558 | If EndBit is greater than 7, then ASSERT().\r |
| 559 | If EndBit is less than StartBit, then ASSERT().\r |
| 560 | \r |
| 561 | @param Address PCI configuration register to write.\r |
| 562 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 563 | Range 0..7.\r |
| 564 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 565 | Range 0..7.\r |
| 566 | @param AndData The value to AND with the PCI configuration register.\r |
| 567 | @param OrData The value to OR with the result of the AND operation.\r |
| 568 | \r |
| 569 | @return The value written back to the PCI configuration register.\r |
| 570 | \r |
| 571 | **/\r |
| 572 | UINT8\r |
| 573 | EFIAPI\r |
| 574 | PciSegmentBitFieldAndThenOr8 (\r |
| 575 | IN UINT64 Address,\r |
| 576 | IN UINTN StartBit,\r |
| 577 | IN UINTN EndBit,\r |
| 578 | IN UINT8 AndData,\r |
| 579 | IN UINT8 OrData\r |
| 580 | )\r |
| 581 | {\r |
| 582 | return PciSegmentWrite8 (\r |
| 583 | Address,\r |
| 584 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r |
| 585 | );\r |
| 586 | }\r |
| 587 | \r |
| 588 | /**\r |
| 589 | Reads a 16-bit PCI configuration register.\r |
| 590 | \r |
| 591 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 592 | This function must guarantee that all PCI read and write operations are\r |
| 593 | serialized.\r |
| 594 | \r |
| 595 | If any reserved bits in Address are set, then ASSERT().\r |
| 596 | \r |
| 597 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 598 | Register.\r |
| 599 | \r |
| 600 | @return The value read from the PCI configuration register.\r |
| 601 | \r |
| 602 | **/\r |
| 603 | UINT16\r |
| 604 | EFIAPI\r |
| 605 | PciSegmentRead16 (\r |
| 606 | IN UINT64 Address\r |
| 607 | )\r |
| 608 | {\r |
| 609 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r |
| 610 | \r |
| 611 | return (UINT16) DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r |
| 612 | }\r |
| 613 | \r |
| 614 | /**\r |
| 615 | Writes a 16-bit PCI configuration register.\r |
| 616 | \r |
| 617 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 618 | value specified by Value. Value is returned. This function must guarantee\r |
| 619 | that all PCI read and write operations are serialized.\r |
| 620 | \r |
| 621 | If any reserved bits in Address are set, then ASSERT().\r |
| 622 | \r |
| 623 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 624 | Register.\r |
| 625 | @param Data The value to write.\r |
| 626 | \r |
| 627 | @return The value written to the PCI configuration register.\r |
| 628 | \r |
| 629 | **/\r |
| 630 | UINT16\r |
| 631 | EFIAPI\r |
| 632 | PciSegmentWrite16 (\r |
| 633 | IN UINT64 Address,\r |
| 634 | IN UINT16 Data\r |
| 635 | )\r |
| 636 | {\r |
| 637 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r |
| 638 | \r |
| 639 | return (UINT16) DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r |
| 640 | }\r |
| 641 | \r |
| 642 | /**\r |
| 643 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 644 | a 16-bit value.\r |
| 645 | \r |
| 646 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 647 | bitwise inclusive OR between the read result and the value specified by\r |
| 648 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 649 | specified by Address. The value written to the PCI configuration register is\r |
| 650 | returned. This function must guarantee that all PCI read and write operations\r |
| 651 | are serialized.\r |
| 652 | \r |
| 653 | If any reserved bits in Address are set, then ASSERT().\r |
| 654 | \r |
| 655 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 656 | Register.\r |
| 657 | @param OrData The value to OR with the PCI configuration register.\r |
| 658 | \r |
| 659 | @return The value written back to the PCI configuration register.\r |
| 660 | \r |
| 661 | **/\r |
| 662 | UINT16\r |
| 663 | EFIAPI\r |
| 664 | PciSegmentOr16 (\r |
| 665 | IN UINT64 Address,\r |
| 666 | IN UINT16 OrData\r |
| 667 | )\r |
| 668 | {\r |
| 669 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r |
| 670 | }\r |
| 671 | \r |
| 672 | /**\r |
| 673 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 674 | value.\r |
| 675 | \r |
| 676 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 677 | bitwise AND between the read result and the value specified by AndData, and\r |
| 678 | writes the result to the 16-bit PCI configuration register specified by\r |
| 679 | Address. The value written to the PCI configuration register is returned.\r |
| 680 | This function must guarantee that all PCI read and write operations are\r |
| 681 | serialized.\r |
| 682 | \r |
| 683 | If any reserved bits in Address are set, then ASSERT().\r |
| 684 | \r |
| 685 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 686 | Register.\r |
| 687 | @param AndData The value to AND with the PCI configuration register.\r |
| 688 | \r |
| 689 | @return The value written back to the PCI configuration register.\r |
| 690 | \r |
| 691 | **/\r |
| 692 | UINT16\r |
| 693 | EFIAPI\r |
| 694 | PciSegmentAnd16 (\r |
| 695 | IN UINT64 Address,\r |
| 696 | IN UINT16 AndData\r |
| 697 | )\r |
| 698 | {\r |
| 699 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r |
| 700 | }\r |
| 701 | \r |
| 702 | /**\r |
| 703 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 704 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 705 | \r |
| 706 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 707 | bitwise AND between the read result and the value specified by AndData,\r |
| 708 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 709 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 710 | configuration register specified by Address. The value written to the PCI\r |
| 711 | configuration register is returned. This function must guarantee that all PCI\r |
| 712 | read and write operations are serialized.\r |
| 713 | \r |
| 714 | If any reserved bits in Address are set, then ASSERT().\r |
| 715 | \r |
| 716 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 717 | Register.\r |
| 718 | @param AndData The value to AND with the PCI configuration register.\r |
| 719 | @param OrData The value to OR with the result of the AND operation.\r |
| 720 | \r |
| 721 | @return The value written back to the PCI configuration register.\r |
| 722 | \r |
| 723 | **/\r |
| 724 | UINT16\r |
| 725 | EFIAPI\r |
| 726 | PciSegmentAndThenOr16 (\r |
| 727 | IN UINT64 Address,\r |
| 728 | IN UINT16 AndData,\r |
| 729 | IN UINT16 OrData\r |
| 730 | )\r |
| 731 | {\r |
| 732 | return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r |
| 733 | }\r |
| 734 | \r |
| 735 | /**\r |
| 736 | Reads a bit field of a PCI configuration register.\r |
| 737 | \r |
| 738 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 739 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 740 | returned.\r |
| 741 | \r |
| 742 | If any reserved bits in Address are set, then ASSERT().\r |
| 743 | If StartBit is greater than 15, then ASSERT().\r |
| 744 | If EndBit is greater than 15, then ASSERT().\r |
| 745 | If EndBit is less than StartBit, then ASSERT().\r |
| 746 | \r |
| 747 | @param Address PCI configuration register to read.\r |
| 748 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 749 | Range 0..15.\r |
| 750 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 751 | Range 0..15.\r |
| 752 | \r |
| 753 | @return The value of the bit field read from the PCI configuration register.\r |
| 754 | \r |
| 755 | **/\r |
| 756 | UINT16\r |
| 757 | EFIAPI\r |
| 758 | PciSegmentBitFieldRead16 (\r |
| 759 | IN UINT64 Address,\r |
| 760 | IN UINTN StartBit,\r |
| 761 | IN UINTN EndBit\r |
| 762 | )\r |
| 763 | {\r |
| 764 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r |
| 765 | }\r |
| 766 | \r |
| 767 | /**\r |
| 768 | Writes a bit field to a PCI configuration register.\r |
| 769 | \r |
| 770 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 771 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 772 | destination PCI configuration register are preserved. The new value of the\r |
| 773 | 16-bit register is returned.\r |
| 774 | \r |
| 775 | If any reserved bits in Address are set, then ASSERT().\r |
| 776 | If StartBit is greater than 15, then ASSERT().\r |
| 777 | If EndBit is greater than 15, then ASSERT().\r |
| 778 | If EndBit is less than StartBit, then ASSERT().\r |
| 779 | \r |
| 780 | @param Address PCI configuration register to write.\r |
| 781 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 782 | Range 0..15.\r |
| 783 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 784 | Range 0..15.\r |
| 785 | @param Value New value of the bit field.\r |
| 786 | \r |
| 787 | @return The value written back to the PCI configuration register.\r |
| 788 | \r |
| 789 | **/\r |
| 790 | UINT16\r |
| 791 | EFIAPI\r |
| 792 | PciSegmentBitFieldWrite16 (\r |
| 793 | IN UINT64 Address,\r |
| 794 | IN UINTN StartBit,\r |
| 795 | IN UINTN EndBit,\r |
| 796 | IN UINT16 Value\r |
| 797 | )\r |
| 798 | {\r |
| 799 | return PciSegmentWrite16 (\r |
| 800 | Address,\r |
| 801 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r |
| 802 | );\r |
| 803 | }\r |
| 804 | \r |
| 805 | /**\r |
| 806 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 807 | writes the result back to the bit field in the 16-bit port.\r |
| 808 | \r |
| 809 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 810 | bitwise inclusive OR between the read result and the value specified by\r |
| 811 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 812 | specified by Address. The value written to the PCI configuration register is\r |
| 813 | returned. This function must guarantee that all PCI read and write operations\r |
| 814 | are serialized. Extra left bits in OrData are stripped.\r |
| 815 | \r |
| 816 | If any reserved bits in Address are set, then ASSERT().\r |
| 817 | If StartBit is greater than 15, then ASSERT().\r |
| 818 | If EndBit is greater than 15, then ASSERT().\r |
| 819 | If EndBit is less than StartBit, then ASSERT().\r |
| 820 | \r |
| 821 | @param Address PCI configuration register to write.\r |
| 822 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 823 | Range 0..15.\r |
| 824 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 825 | Range 0..15.\r |
| 826 | @param OrData The value to OR with the PCI configuration register.\r |
| 827 | \r |
| 828 | @return The value written back to the PCI configuration register.\r |
| 829 | \r |
| 830 | **/\r |
| 831 | UINT16\r |
| 832 | EFIAPI\r |
| 833 | PciSegmentBitFieldOr16 (\r |
| 834 | IN UINT64 Address,\r |
| 835 | IN UINTN StartBit,\r |
| 836 | IN UINTN EndBit,\r |
| 837 | IN UINT16 OrData\r |
| 838 | )\r |
| 839 | {\r |
| 840 | return PciSegmentWrite16 (\r |
| 841 | Address,\r |
| 842 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r |
| 843 | );\r |
| 844 | }\r |
| 845 | \r |
| 846 | /**\r |
| 847 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 848 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 849 | \r |
| 850 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 851 | bitwise AND between the read result and the value specified by AndData, and\r |
| 852 | writes the result to the 16-bit PCI configuration register specified by\r |
| 853 | Address. The value written to the PCI configuration register is returned.\r |
| 854 | This function must guarantee that all PCI read and write operations are\r |
| 855 | serialized. Extra left bits in AndData are stripped.\r |
| 856 | \r |
| 857 | If any reserved bits in Address are set, then ASSERT().\r |
| 858 | If StartBit is greater than 15, then ASSERT().\r |
| 859 | If EndBit is greater than 15, then ASSERT().\r |
| 860 | If EndBit is less than StartBit, then ASSERT().\r |
| 861 | \r |
| 862 | @param Address PCI configuration register to write.\r |
| 863 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 864 | Range 0..15.\r |
| 865 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 866 | Range 0..15.\r |
| 867 | @param AndData The value to AND with the PCI configuration register.\r |
| 868 | \r |
| 869 | @return The value written back to the PCI configuration register.\r |
| 870 | \r |
| 871 | **/\r |
| 872 | UINT16\r |
| 873 | EFIAPI\r |
| 874 | PciSegmentBitFieldAnd16 (\r |
| 875 | IN UINT64 Address,\r |
| 876 | IN UINTN StartBit,\r |
| 877 | IN UINTN EndBit,\r |
| 878 | IN UINT16 AndData\r |
| 879 | )\r |
| 880 | {\r |
| 881 | return PciSegmentWrite16 (\r |
| 882 | Address,\r |
| 883 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r |
| 884 | );\r |
| 885 | }\r |
| 886 | \r |
| 887 | /**\r |
| 888 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 889 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 890 | 16-bit port.\r |
| 891 | \r |
| 892 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 893 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 894 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 895 | configuration register specified by Address. The value written to the PCI\r |
| 896 | configuration register is returned. This function must guarantee that all PCI\r |
| 897 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 898 | OrData are stripped.\r |
| 899 | \r |
| 900 | If any reserved bits in Address are set, then ASSERT().\r |
| 901 | If StartBit is greater than 15, then ASSERT().\r |
| 902 | If EndBit is greater than 15, then ASSERT().\r |
| 903 | If EndBit is less than StartBit, then ASSERT().\r |
| 904 | \r |
| 905 | @param Address PCI configuration register to write.\r |
| 906 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 907 | Range 0..15.\r |
| 908 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 909 | Range 0..15.\r |
| 910 | @param AndData The value to AND with the PCI configuration register.\r |
| 911 | @param OrData The value to OR with the result of the AND operation.\r |
| 912 | \r |
| 913 | @return The value written back to the PCI configuration register.\r |
| 914 | \r |
| 915 | **/\r |
| 916 | UINT16\r |
| 917 | EFIAPI\r |
| 918 | PciSegmentBitFieldAndThenOr16 (\r |
| 919 | IN UINT64 Address,\r |
| 920 | IN UINTN StartBit,\r |
| 921 | IN UINTN EndBit,\r |
| 922 | IN UINT16 AndData,\r |
| 923 | IN UINT16 OrData\r |
| 924 | )\r |
| 925 | {\r |
| 926 | return PciSegmentWrite16 (\r |
| 927 | Address,\r |
| 928 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r |
| 929 | );\r |
| 930 | }\r |
| 931 | \r |
| 932 | /**\r |
| 933 | Reads a 32-bit PCI configuration register.\r |
| 934 | \r |
| 935 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 936 | This function must guarantee that all PCI read and write operations are\r |
| 937 | serialized.\r |
| 938 | \r |
| 939 | If any reserved bits in Address are set, then ASSERT().\r |
| 940 | \r |
| 941 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 942 | Register.\r |
| 943 | \r |
| 944 | @return The value read from the PCI configuration register.\r |
| 945 | \r |
| 946 | **/\r |
| 947 | UINT32\r |
| 948 | EFIAPI\r |
| 949 | PciSegmentRead32 (\r |
| 950 | IN UINT64 Address\r |
| 951 | )\r |
| 952 | {\r |
| 953 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r |
| 954 | \r |
| 955 | return DxePciSegmentLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);\r |
| 956 | }\r |
| 957 | \r |
| 958 | /**\r |
| 959 | Writes a 32-bit PCI configuration register.\r |
| 960 | \r |
| 961 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 962 | value specified by Value. Value is returned. This function must guarantee\r |
| 963 | that all PCI read and write operations are serialized.\r |
| 964 | \r |
| 965 | If any reserved bits in Address are set, then ASSERT().\r |
| 966 | \r |
| 967 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 968 | Register.\r |
| 969 | @param Data The value to write.\r |
| 970 | \r |
| 971 | @return The value written to the PCI configuration register.\r |
| 972 | \r |
| 973 | **/\r |
| 974 | UINT32\r |
| 975 | EFIAPI\r |
| 976 | PciSegmentWrite32 (\r |
| 977 | IN UINT64 Address,\r |
| 978 | IN UINT32 Data\r |
| 979 | )\r |
| 980 | {\r |
| 981 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r |
| 982 | \r |
| 983 | return DxePciSegmentLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r |
| 984 | }\r |
| 985 | \r |
| 986 | /**\r |
| 987 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 988 | a 32-bit value.\r |
| 989 | \r |
| 990 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 991 | bitwise inclusive OR between the read result and the value specified by\r |
| 992 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 993 | specified by Address. The value written to the PCI configuration register is\r |
| 994 | returned. This function must guarantee that all PCI read and write operations\r |
| 995 | are serialized.\r |
| 996 | \r |
| 997 | If any reserved bits in Address are set, then ASSERT().\r |
| 998 | \r |
| 999 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 1000 | Register.\r |
| 1001 | @param OrData The value to OR with the PCI configuration register.\r |
| 1002 | \r |
| 1003 | @return The value written back to the PCI configuration register.\r |
| 1004 | \r |
| 1005 | **/\r |
| 1006 | UINT32\r |
| 1007 | EFIAPI\r |
| 1008 | PciSegmentOr32 (\r |
| 1009 | IN UINT64 Address,\r |
| 1010 | IN UINT32 OrData\r |
| 1011 | )\r |
| 1012 | {\r |
| 1013 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r |
| 1014 | }\r |
| 1015 | \r |
| 1016 | /**\r |
| 1017 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 1018 | value.\r |
| 1019 | \r |
| 1020 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1021 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1022 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1023 | Address. The value written to the PCI configuration register is returned.\r |
| 1024 | This function must guarantee that all PCI read and write operations are\r |
| 1025 | serialized.\r |
| 1026 | \r |
| 1027 | If any reserved bits in Address are set, then ASSERT().\r |
| 1028 | \r |
| 1029 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 1030 | Register.\r |
| 1031 | @param AndData The value to AND with the PCI configuration register.\r |
| 1032 | \r |
| 1033 | @return The value written back to the PCI configuration register.\r |
| 1034 | \r |
| 1035 | **/\r |
| 1036 | UINT32\r |
| 1037 | EFIAPI\r |
| 1038 | PciSegmentAnd32 (\r |
| 1039 | IN UINT64 Address,\r |
| 1040 | IN UINT32 AndData\r |
| 1041 | )\r |
| 1042 | {\r |
| 1043 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r |
| 1044 | }\r |
| 1045 | \r |
| 1046 | /**\r |
| 1047 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 1048 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 1049 | \r |
| 1050 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1051 | bitwise AND between the read result and the value specified by AndData,\r |
| 1052 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 1053 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 1054 | configuration register specified by Address. The value written to the PCI\r |
| 1055 | configuration register is returned. This function must guarantee that all PCI\r |
| 1056 | read and write operations are serialized.\r |
| 1057 | \r |
| 1058 | If any reserved bits in Address are set, then ASSERT().\r |
| 1059 | \r |
| 1060 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r |
| 1061 | Register.\r |
| 1062 | @param AndData The value to AND with the PCI configuration register.\r |
| 1063 | @param OrData The value to OR with the result of the AND operation.\r |
| 1064 | \r |
| 1065 | @return The value written back to the PCI configuration register.\r |
| 1066 | \r |
| 1067 | **/\r |
| 1068 | UINT32\r |
| 1069 | EFIAPI\r |
| 1070 | PciSegmentAndThenOr32 (\r |
| 1071 | IN UINT64 Address,\r |
| 1072 | IN UINT32 AndData,\r |
| 1073 | IN UINT32 OrData\r |
| 1074 | )\r |
| 1075 | {\r |
| 1076 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r |
| 1077 | }\r |
| 1078 | \r |
| 1079 | /**\r |
| 1080 | Reads a bit field of a PCI configuration register.\r |
| 1081 | \r |
| 1082 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 1083 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 1084 | returned.\r |
| 1085 | \r |
| 1086 | If any reserved bits in Address are set, then ASSERT().\r |
| 1087 | If StartBit is greater than 31, then ASSERT().\r |
| 1088 | If EndBit is greater than 31, then ASSERT().\r |
| 1089 | If EndBit is less than StartBit, then ASSERT().\r |
| 1090 | \r |
| 1091 | @param Address PCI configuration register to read.\r |
| 1092 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1093 | Range 0..31.\r |
| 1094 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1095 | Range 0..31.\r |
| 1096 | \r |
| 1097 | @return The value of the bit field read from the PCI configuration register.\r |
| 1098 | \r |
| 1099 | **/\r |
| 1100 | UINT32\r |
| 1101 | EFIAPI\r |
| 1102 | PciSegmentBitFieldRead32 (\r |
| 1103 | IN UINT64 Address,\r |
| 1104 | IN UINTN StartBit,\r |
| 1105 | IN UINTN EndBit\r |
| 1106 | )\r |
| 1107 | {\r |
| 1108 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r |
| 1109 | }\r |
| 1110 | \r |
| 1111 | /**\r |
| 1112 | Writes a bit field to a PCI configuration register.\r |
| 1113 | \r |
| 1114 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 1115 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 1116 | destination PCI configuration register are preserved. The new value of the\r |
| 1117 | 32-bit register is returned.\r |
| 1118 | \r |
| 1119 | If any reserved bits in Address are set, then ASSERT().\r |
| 1120 | If StartBit is greater than 31, then ASSERT().\r |
| 1121 | If EndBit is greater than 31, then ASSERT().\r |
| 1122 | If EndBit is less than StartBit, then ASSERT().\r |
| 1123 | \r |
| 1124 | @param Address PCI configuration register to write.\r |
| 1125 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1126 | Range 0..31.\r |
| 1127 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1128 | Range 0..31.\r |
| 1129 | @param Value New value of the bit field.\r |
| 1130 | \r |
| 1131 | @return The value written back to the PCI configuration register.\r |
| 1132 | \r |
| 1133 | **/\r |
| 1134 | UINT32\r |
| 1135 | EFIAPI\r |
| 1136 | PciSegmentBitFieldWrite32 (\r |
| 1137 | IN UINT64 Address,\r |
| 1138 | IN UINTN StartBit,\r |
| 1139 | IN UINTN EndBit,\r |
| 1140 | IN UINT32 Value\r |
| 1141 | )\r |
| 1142 | {\r |
| 1143 | return PciSegmentWrite32 (\r |
| 1144 | Address,\r |
| 1145 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r |
| 1146 | );\r |
| 1147 | }\r |
| 1148 | \r |
| 1149 | /**\r |
| 1150 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 1151 | writes the result back to the bit field in the 32-bit port.\r |
| 1152 | \r |
| 1153 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1154 | bitwise inclusive OR between the read result and the value specified by\r |
| 1155 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 1156 | specified by Address. The value written to the PCI configuration register is\r |
| 1157 | returned. This function must guarantee that all PCI read and write operations\r |
| 1158 | are serialized. Extra left bits in OrData are stripped.\r |
| 1159 | \r |
| 1160 | If any reserved bits in Address are set, then ASSERT().\r |
| 1161 | If StartBit is greater than 31, then ASSERT().\r |
| 1162 | If EndBit is greater than 31, then ASSERT().\r |
| 1163 | If EndBit is less than StartBit, then ASSERT().\r |
| 1164 | \r |
| 1165 | @param Address PCI configuration register to write.\r |
| 1166 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1167 | Range 0..31.\r |
| 1168 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1169 | Range 0..31.\r |
| 1170 | @param OrData The value to OR with the PCI configuration register.\r |
| 1171 | \r |
| 1172 | @return The value written back to the PCI configuration register.\r |
| 1173 | \r |
| 1174 | **/\r |
| 1175 | UINT32\r |
| 1176 | EFIAPI\r |
| 1177 | PciSegmentBitFieldOr32 (\r |
| 1178 | IN UINT64 Address,\r |
| 1179 | IN UINTN StartBit,\r |
| 1180 | IN UINTN EndBit,\r |
| 1181 | IN UINT32 OrData\r |
| 1182 | )\r |
| 1183 | {\r |
| 1184 | return PciSegmentWrite32 (\r |
| 1185 | Address,\r |
| 1186 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r |
| 1187 | );\r |
| 1188 | }\r |
| 1189 | \r |
| 1190 | /**\r |
| 1191 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 1192 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 1193 | \r |
| 1194 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1195 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1196 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1197 | Address. The value written to the PCI configuration register is returned.\r |
| 1198 | This function must guarantee that all PCI read and write operations are\r |
| 1199 | serialized. Extra left bits in AndData are stripped.\r |
| 1200 | \r |
| 1201 | If any reserved bits in Address are set, then ASSERT().\r |
| 1202 | If StartBit is greater than 31, then ASSERT().\r |
| 1203 | If EndBit is greater than 31, then ASSERT().\r |
| 1204 | If EndBit is less than StartBit, then ASSERT().\r |
| 1205 | \r |
| 1206 | @param Address PCI configuration register to write.\r |
| 1207 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1208 | Range 0..31.\r |
| 1209 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1210 | Range 0..31.\r |
| 1211 | @param AndData The value to AND with the PCI configuration register.\r |
| 1212 | \r |
| 1213 | @return The value written back to the PCI configuration register.\r |
| 1214 | \r |
| 1215 | **/\r |
| 1216 | UINT32\r |
| 1217 | EFIAPI\r |
| 1218 | PciSegmentBitFieldAnd32 (\r |
| 1219 | IN UINT64 Address,\r |
| 1220 | IN UINTN StartBit,\r |
| 1221 | IN UINTN EndBit,\r |
| 1222 | IN UINT32 AndData\r |
| 1223 | )\r |
| 1224 | {\r |
| 1225 | return PciSegmentWrite32 (\r |
| 1226 | Address,\r |
| 1227 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r |
| 1228 | );\r |
| 1229 | }\r |
| 1230 | \r |
| 1231 | /**\r |
| 1232 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 1233 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 1234 | 32-bit port.\r |
| 1235 | \r |
| 1236 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1237 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 1238 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 1239 | configuration register specified by Address. The value written to the PCI\r |
| 1240 | configuration register is returned. This function must guarantee that all PCI\r |
| 1241 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1242 | OrData are stripped.\r |
| 1243 | \r |
| 1244 | If any reserved bits in Address are set, then ASSERT().\r |
| 1245 | If StartBit is greater than 31, then ASSERT().\r |
| 1246 | If EndBit is greater than 31, then ASSERT().\r |
| 1247 | If EndBit is less than StartBit, then ASSERT().\r |
| 1248 | \r |
| 1249 | @param Address PCI configuration register to write.\r |
| 1250 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1251 | Range 0..31.\r |
| 1252 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1253 | Range 0..31.\r |
| 1254 | @param AndData The value to AND with the PCI configuration register.\r |
| 1255 | @param OrData The value to OR with the result of the AND operation.\r |
| 1256 | \r |
| 1257 | @return The value written back to the PCI configuration register.\r |
| 1258 | \r |
| 1259 | **/\r |
| 1260 | UINT32\r |
| 1261 | EFIAPI\r |
| 1262 | PciSegmentBitFieldAndThenOr32 (\r |
| 1263 | IN UINT64 Address,\r |
| 1264 | IN UINTN StartBit,\r |
| 1265 | IN UINTN EndBit,\r |
| 1266 | IN UINT32 AndData,\r |
| 1267 | IN UINT32 OrData\r |
| 1268 | )\r |
| 1269 | {\r |
| 1270 | return PciSegmentWrite32 (\r |
| 1271 | Address,\r |
| 1272 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r |
| 1273 | );\r |
| 1274 | }\r |
| 1275 | \r |
| 1276 | /**\r |
| 1277 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1278 | \r |
| 1279 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1280 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1281 | configuration registers from a single PCI function to be read. Size is\r |
| 1282 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1283 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1284 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1285 | end of the range.\r |
| 1286 | \r |
| 1287 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1288 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1289 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1290 | \r |
| 1291 | @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r |
| 1292 | Function and Register.\r |
| 1293 | @param Size Size in bytes of the transfer.\r |
| 1294 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1295 | \r |
| 1296 | @return Size\r |
| 1297 | \r |
| 1298 | **/\r |
| 1299 | UINTN\r |
| 1300 | EFIAPI\r |
| 1301 | PciSegmentReadBuffer (\r |
| 1302 | IN UINT64 StartAddress,\r |
| 1303 | IN UINTN Size,\r |
| 1304 | OUT VOID *Buffer\r |
| 1305 | )\r |
| 1306 | {\r |
| 1307 | UINTN ReturnValue;\r |
| 1308 | \r |
| 1309 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r |
| 1310 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1311 | \r |
| 1312 | if (Size == 0) {\r |
| 1313 | return Size;\r |
| 1314 | }\r |
| 1315 | \r |
| 1316 | ASSERT (Buffer != NULL);\r |
| 1317 | \r |
| 1318 | //\r |
| 1319 | // Save Size for return\r |
| 1320 | //\r |
| 1321 | ReturnValue = Size;\r |
| 1322 | \r |
| 1323 | if ((StartAddress & 1) != 0) {\r |
| 1324 | //\r |
| 1325 | // Read a byte if StartAddress is byte aligned\r |
| 1326 | //\r |
| 1327 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r |
| 1328 | StartAddress += sizeof (UINT8);\r |
| 1329 | Size -= sizeof (UINT8);\r |
| 1330 | Buffer = (UINT8*)Buffer + 1;\r |
| 1331 | }\r |
| 1332 | \r |
| 1333 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1334 | //\r |
| 1335 | // Read a word if StartAddress is word aligned\r |
| 1336 | //\r |
| 1337 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r |
| 1338 | StartAddress += sizeof (UINT16);\r |
| 1339 | Size -= sizeof (UINT16);\r |
| 1340 | Buffer = (UINT16*)Buffer + 1;\r |
| 1341 | }\r |
| 1342 | \r |
| 1343 | while (Size >= sizeof (UINT32)) {\r |
| 1344 | //\r |
| 1345 | // Read as many double words as possible\r |
| 1346 | //\r |
| 1347 | *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r |
| 1348 | StartAddress += sizeof (UINT32);\r |
| 1349 | Size -= sizeof (UINT32);\r |
| 1350 | Buffer = (UINT32*)Buffer + 1;\r |
| 1351 | }\r |
| 1352 | \r |
| 1353 | if (Size >= sizeof (UINT16)) {\r |
| 1354 | //\r |
| 1355 | // Read the last remaining word if exist\r |
| 1356 | //\r |
| 1357 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r |
| 1358 | StartAddress += sizeof (UINT16);\r |
| 1359 | Size -= sizeof (UINT16);\r |
| 1360 | Buffer = (UINT16*)Buffer + 1;\r |
| 1361 | }\r |
| 1362 | \r |
| 1363 | if (Size >= sizeof (UINT8)) {\r |
| 1364 | //\r |
| 1365 | // Read the last remaining byte if exist\r |
| 1366 | //\r |
| 1367 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r |
| 1368 | }\r |
| 1369 | \r |
| 1370 | return ReturnValue;\r |
| 1371 | }\r |
| 1372 | \r |
| 1373 | /**\r |
| 1374 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1375 | configuration space.\r |
| 1376 | \r |
| 1377 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1378 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1379 | configuration registers from a single PCI function to be written. Size is\r |
| 1380 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1381 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1382 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1383 | and the end of the range.\r |
| 1384 | \r |
| 1385 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1386 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1387 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1388 | \r |
| 1389 | @param StartAddress Starting Address that encodes the PCI Segment, Bus, Device,\r |
| 1390 | Function and Register.\r |
| 1391 | @param Size Size in bytes of the transfer.\r |
| 1392 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1393 | \r |
| 1394 | @return Size\r |
| 1395 | \r |
| 1396 | **/\r |
| 1397 | UINTN\r |
| 1398 | EFIAPI\r |
| 1399 | PciSegmentWriteBuffer (\r |
| 1400 | IN UINT64 StartAddress,\r |
| 1401 | IN UINTN Size,\r |
| 1402 | IN VOID *Buffer\r |
| 1403 | )\r |
| 1404 | {\r |
| 1405 | UINTN ReturnValue;\r |
| 1406 | \r |
| 1407 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r |
| 1408 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1409 | \r |
| 1410 | if (Size == 0) {\r |
| 1411 | return 0;\r |
| 1412 | }\r |
| 1413 | \r |
| 1414 | ASSERT (Buffer != NULL);\r |
| 1415 | \r |
| 1416 | //\r |
| 1417 | // Save Size for return\r |
| 1418 | //\r |
| 1419 | ReturnValue = Size;\r |
| 1420 | \r |
| 1421 | if ((StartAddress & 1) != 0) {\r |
| 1422 | //\r |
| 1423 | // Write a byte if StartAddress is byte aligned\r |
| 1424 | //\r |
| 1425 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1426 | StartAddress += sizeof (UINT8);\r |
| 1427 | Size -= sizeof (UINT8);\r |
| 1428 | Buffer = (UINT8*)Buffer + 1;\r |
| 1429 | }\r |
| 1430 | \r |
| 1431 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1432 | //\r |
| 1433 | // Write a word if StartAddress is word aligned\r |
| 1434 | //\r |
| 1435 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r |
| 1436 | StartAddress += sizeof (UINT16);\r |
| 1437 | Size -= sizeof (UINT16);\r |
| 1438 | Buffer = (UINT16*)Buffer + 1;\r |
| 1439 | }\r |
| 1440 | \r |
| 1441 | while (Size >= sizeof (UINT32)) {\r |
| 1442 | //\r |
| 1443 | // Write as many double words as possible\r |
| 1444 | //\r |
| 1445 | PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r |
| 1446 | StartAddress += sizeof (UINT32);\r |
| 1447 | Size -= sizeof (UINT32);\r |
| 1448 | Buffer = (UINT32*)Buffer + 1;\r |
| 1449 | }\r |
| 1450 | \r |
| 1451 | if (Size >= sizeof (UINT16)) {\r |
| 1452 | //\r |
| 1453 | // Write the last remaining word if exist\r |
| 1454 | //\r |
| 1455 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r |
| 1456 | StartAddress += sizeof (UINT16);\r |
| 1457 | Size -= sizeof (UINT16);\r |
| 1458 | Buffer = (UINT16*)Buffer + 1;\r |
| 1459 | }\r |
| 1460 | \r |
| 1461 | if (Size >= sizeof (UINT8)) {\r |
| 1462 | //\r |
| 1463 | // Write the last remaining byte if exist\r |
| 1464 | //\r |
| 1465 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1466 | }\r |
| 1467 | \r |
| 1468 | return ReturnValue;\r |
| 1469 | }\r |
projects / mirror_edk2.git / blame