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93b5b853 | 1 | /** @file\r |
2 | Functions in this library instance make use of MMIO functions in IoLib to\r | |
3 | access memory mapped PCI configuration space.\r | |
4 | \r | |
5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r | |
6 | Library.\r | |
7 | \r | |
687add70 | 8 | Copyright (c) 2006 - 2009, Intel Corporation<BR>\r |
93b5b853 | 9 | All rights reserved. This program and the accompanying materials\r |
10 | are licensed and made available under the terms and conditions of the BSD License\r | |
11 | which accompanies this distribution. The full text of the license may be found at\r | |
12 | http://opensource.org/licenses/bsd-license.php\r | |
13 | \r | |
14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
16 | \r | |
17 | **/\r | |
18 | \r | |
19 | \r | |
20 | #include <PiDxe.h>\r | |
21 | \r | |
7c188740 | 22 | #include <Guid/EventGroup.h>\r |
23 | \r | |
93b5b853 | 24 | #include <Library/BaseLib.h>\r |
25 | #include <Library/PciExpressLib.h>\r | |
26 | #include <Library/IoLib.h>\r | |
27 | #include <Library/DebugLib.h>\r | |
28 | #include <Library/PcdLib.h>\r | |
29 | #include <Library/MemoryAllocationLib.h>\r | |
30 | #include <Library/UefiBootServicesTableLib.h>\r | |
31 | #include <Library/DxeServicesTableLib.h>\r | |
32 | #include <Library/UefiRuntimeLib.h>\r | |
33 | \r | |
34 | ///\r | |
35 | /// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime\r | |
36 | ///\r | |
37 | typedef struct {\r | |
38 | UINTN PhysicalAddress;\r | |
39 | UINTN VirtualAddress;\r | |
40 | } PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;\r | |
41 | \r | |
42 | ///\r | |
43 | /// Set Virtual Address Map Event\r | |
44 | ///\r | |
45 | EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r | |
46 | \r | |
47 | ///\r | |
48 | /// Module global that contains the base physical address of the PCI Express MMIO range\r | |
49 | ///\r | |
50 | UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r | |
51 | \r | |
52 | ///\r | |
53 | /// The number of PCI devices that have been registered for runtime access\r | |
54 | ///\r | |
55 | UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r | |
56 | \r | |
57 | ///\r | |
58 | /// The table of PCI devices that have been registered for runtime access\r | |
59 | ///\r | |
60 | PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciExpressLibRegistrationTable = NULL;\r | |
61 | \r | |
62 | ///\r | |
63 | /// The table index of the most recent virtual address lookup\r | |
64 | ///\r | |
65 | UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r | |
66 | \r | |
67 | \r | |
68 | /**\r | |
69 | Convert the physical PCI Express MMIO addresses for all registered PCI devices\r | |
70 | to virtual addresses.\r | |
71 | \r | |
72 | @param[in] Event The Event that is being processed\r | |
73 | @param[in] Context Event Context\r | |
74 | **/\r | |
75 | VOID\r | |
76 | EFIAPI\r | |
77 | DxeRuntimePciExpressLibVirtualNotify (\r | |
78 | IN EFI_EVENT Event,\r | |
79 | IN VOID *Context\r | |
80 | )\r | |
81 | {\r | |
82 | UINTN Index;\r | |
83 | \r | |
84 | //\r | |
85 | // If there have been no runtime registrations, then just return\r | |
86 | //\r | |
87 | if (mDxeRuntimePciExpressLibRegistrationTable == NULL) {\r | |
88 | return;\r | |
89 | }\r | |
90 | \r | |
91 | //\r | |
92 | // Convert physical addresses associated with the set of registered PCI devices to\r | |
93 | // virtual addresses.\r | |
94 | //\r | |
95 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r | |
96 | EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r | |
97 | }\r | |
98 | \r | |
99 | //\r | |
100 | // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r | |
101 | //\r | |
102 | EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);\r | |
103 | }\r | |
104 | \r | |
105 | /**\r | |
106 | The constructor function caches the PCI Express Base Address and creates a \r | |
107 | Set Virtual Address Map event to convert physical address to virtual addresses.\r | |
108 | \r | |
109 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
110 | @param SystemTable A pointer to the EFI System Table.\r | |
111 | \r | |
112 | @retval EFI_SUCCESS The constructor completed successfully.\r | |
113 | @retval Other value The constructor did not complete successfully.\r | |
114 | \r | |
115 | **/\r | |
116 | EFI_STATUS\r | |
117 | EFIAPI\r | |
118 | DxeRuntimePciExpressLibConstructor (\r | |
56733004 | 119 | IN EFI_HANDLE ImageHandle,\r |
120 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
93b5b853 | 121 | )\r |
122 | {\r | |
123 | EFI_STATUS Status;\r | |
124 | \r | |
125 | //\r | |
126 | // Cache the physical address of the PCI Express MMIO range into a module global variable\r | |
127 | //\r | |
128 | mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r | |
129 | \r | |
130 | //\r | |
131 | // Register SetVirtualAddressMap () notify function\r | |
132 | //\r | |
7c188740 | 133 | Status = gBS->CreateEventEx (\r |
134 | EVT_NOTIFY_SIGNAL,\r | |
93b5b853 | 135 | TPL_NOTIFY,\r |
136 | DxeRuntimePciExpressLibVirtualNotify,\r | |
137 | NULL,\r | |
7c188740 | 138 | &gEfiEventVirtualAddressChangeGuid,\r |
93b5b853 | 139 | &mDxeRuntimePciExpressLibVirtualNotifyEvent\r |
140 | );\r | |
141 | ASSERT_EFI_ERROR (Status);\r | |
142 | \r | |
143 | return Status;\r | |
144 | }\r | |
145 | \r | |
146 | /**\r | |
147 | The destructor function frees any allocated buffers and closes the Set Virtual \r | |
148 | Address Map event.\r | |
149 | \r | |
150 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
151 | @param SystemTable A pointer to the EFI System Table.\r | |
152 | \r | |
153 | @retval EFI_SUCCESS The destructor completed successfully.\r | |
154 | @retval Other value The destructor did not complete successfully.\r | |
155 | \r | |
156 | **/\r | |
157 | EFI_STATUS\r | |
158 | EFIAPI\r | |
159 | DxeRuntimePciExpressLibDestructor (\r | |
56733004 | 160 | IN EFI_HANDLE ImageHandle,\r |
161 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
93b5b853 | 162 | )\r |
163 | {\r | |
164 | EFI_STATUS Status;\r | |
165 | \r | |
166 | //\r | |
167 | // If one or more PCI devices have been registered for runtime access, then \r | |
168 | // free the registration table.\r | |
169 | //\r | |
170 | if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {\r | |
171 | FreePool (mDxeRuntimePciExpressLibRegistrationTable);\r | |
172 | }\r | |
173 | \r | |
174 | //\r | |
175 | // Close the Set Virtual Address Map event\r | |
176 | //\r | |
177 | Status = gBS->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent);\r | |
178 | ASSERT_EFI_ERROR (Status);\r | |
179 | \r | |
180 | return Status;\r | |
181 | }\r | |
182 | \r | |
183 | /**\r | |
184 | Gets the base address of PCI Express.\r | |
185 | \r | |
186 | This internal functions retrieves PCI Express Base Address via a PCD entry\r | |
187 | PcdPciExpressBaseAddress.\r | |
188 | \r | |
8f0dd97e | 189 | @param Address Address that encodes the PCI Bus, Device, Function and Register.\r |
190 | @return The base address of PCI Express.\r | |
93b5b853 | 191 | \r |
192 | **/\r | |
193 | UINTN\r | |
194 | GetPciExpressAddress (\r | |
195 | IN UINTN Address\r | |
196 | )\r | |
197 | {\r | |
198 | UINTN Index;\r | |
199 | \r | |
200 | //\r | |
201 | // Make sure Address is valid\r | |
202 | //\r | |
203 | ASSERT (((Address) & ~0xfffffff) == 0);\r | |
204 | \r | |
205 | //\r | |
206 | // Convert Address to a physical address in the MMIO PCI Express range\r | |
207 | //\r | |
208 | Address += mDxeRuntimePciExpressLibPciExpressBaseAddress;\r | |
209 | \r | |
210 | //\r | |
211 | // If SetVirtualAddressMap() has not been called, then just return the physical address\r | |
212 | //\r | |
213 | if (!EfiGoneVirtual ()) {\r | |
214 | return Address;\r | |
215 | }\r | |
216 | \r | |
217 | //\r | |
218 | // See if there is a physical address match at the exact same index as the last address match\r | |
219 | //\r | |
687add70 | 220 | if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {\r |
93b5b853 | 221 | //\r |
222 | // Convert the physical address to a virtual address and return the virtual address\r | |
223 | //\r | |
224 | return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].VirtualAddress;\r | |
225 | }\r | |
226 | \r | |
227 | //\r | |
d908a2d6 | 228 | // Search the entire table for a physical address match\r |
93b5b853 | 229 | //\r |
230 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r | |
687add70 | 231 | if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {\r |
93b5b853 | 232 | //\r |
233 | // Cache the matching index value\r | |
234 | //\r | |
235 | mDxeRuntimePciExpressLibLastRuntimeRange = Index;\r | |
236 | //\r | |
237 | // Convert the physical address to a virtual address and return the virtual address\r | |
238 | //\r | |
239 | return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress;\r | |
240 | }\r | |
241 | }\r | |
242 | \r | |
243 | //\r | |
244 | // No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.\r | |
245 | //\r | |
246 | ASSERT (FALSE);\r | |
247 | CpuBreakpoint();\r | |
248 | \r | |
249 | //\r | |
250 | // Return the physical address \r | |
251 | //\r | |
252 | return Address;\r | |
253 | }\r | |
254 | \r | |
255 | /**\r | |
518db1d9 | 256 | Registers a PCI device so PCI configuration registers may be accessed after \r |
93b5b853 | 257 | SetVirtualAddressMap().\r |
258 | \r | |
518db1d9 | 259 | Registers the PCI device specified by Address so all the PCI configuration \r |
260 | registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r | |
261 | is called.\r | |
262 | \r | |
93b5b853 | 263 | If Address > 0x0FFFFFFF, then ASSERT().\r |
264 | \r | |
265 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
266 | Register.\r | |
267 | \r | |
268 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
269 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
270 | after ExitBootServices().\r | |
271 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
272 | at runtime could not be mapped.\r | |
273 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
274 | complete the registration.\r | |
275 | \r | |
276 | **/\r | |
277 | RETURN_STATUS\r | |
278 | EFIAPI\r | |
279 | PciExpressRegisterForRuntimeAccess (\r | |
280 | IN UINTN Address\r | |
281 | )\r | |
282 | {\r | |
283 | EFI_STATUS Status;\r | |
284 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r | |
285 | UINTN Index;\r | |
286 | VOID *NewTable;\r | |
287 | \r | |
288 | //\r | |
289 | // Return an error if this function is called after ExitBootServices().\r | |
290 | //\r | |
291 | if (EfiAtRuntime ()) {\r | |
292 | return RETURN_UNSUPPORTED;\r | |
293 | }\r | |
294 | \r | |
295 | //\r | |
296 | // Make sure Address is valid\r | |
297 | //\r | |
298 | ASSERT (((Address) & ~0xfffffff) == 0);\r | |
299 | \r | |
300 | //\r | |
301 | // Convert Address to a physical address in the MMIO PCI Express range\r | |
302 | // at the beginning of the PCI Configuration header for the specified\r | |
303 | // PCI Bus/Dev/Func\r | |
304 | //\r | |
305 | Address = GetPciExpressAddress (Address & 0x0ffff000);\r | |
306 | \r | |
307 | //\r | |
308 | // See if Address has already been registerd for runtime access\r | |
309 | //\r | |
310 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r | |
311 | if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {\r | |
312 | return RETURN_SUCCESS;\r | |
313 | }\r | |
314 | }\r | |
315 | \r | |
316 | //\r | |
317 | // Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address\r | |
318 | //\r | |
319 | Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);\r | |
320 | if (EFI_ERROR (Status)) {\r | |
321 | return RETURN_UNSUPPORTED;\r | |
322 | }\r | |
323 | \r | |
324 | //\r | |
325 | // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS\r | |
326 | // will allocate a virtual address range for the 4KB PCI Configuration Header.\r | |
327 | //\r | |
328 | Status = gDS->SetMemorySpaceAttributes (Address, 0x1000, Descriptor.Attributes | EFI_MEMORY_RUNTIME);\r | |
329 | if (EFI_ERROR (Status)) {\r | |
330 | return RETURN_UNSUPPORTED;\r | |
331 | }\r | |
332 | \r | |
333 | //\r | |
334 | // Grow the size of the registration table\r | |
335 | //\r | |
336 | NewTable = ReallocateRuntimePool (\r | |
337 | (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r | |
338 | (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r | |
339 | mDxeRuntimePciExpressLibRegistrationTable\r | |
340 | );\r | |
341 | if (NewTable == NULL) {\r | |
342 | return RETURN_OUT_OF_RESOURCES;\r | |
343 | }\r | |
344 | mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r | |
345 | mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r | |
346 | mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress = Address;\r | |
347 | mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;\r | |
348 | \r | |
349 | return RETURN_SUCCESS;\r | |
350 | }\r | |
351 | \r | |
352 | \r | |
353 | /**\r | |
354 | Reads an 8-bit PCI configuration register.\r | |
355 | \r | |
356 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
357 | This function must guarantee that all PCI read and write operations are\r | |
358 | serialized.\r | |
359 | \r | |
360 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
361 | \r | |
362 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
363 | Register.\r | |
364 | \r | |
365 | @return The read value from the PCI configuration register.\r | |
366 | \r | |
367 | **/\r | |
368 | UINT8\r | |
369 | EFIAPI\r | |
370 | PciExpressRead8 (\r | |
371 | IN UINTN Address\r | |
372 | )\r | |
373 | {\r | |
374 | return MmioRead8 (GetPciExpressAddress (Address));\r | |
375 | }\r | |
376 | \r | |
377 | /**\r | |
378 | Writes an 8-bit PCI configuration register.\r | |
379 | \r | |
380 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
381 | value specified by Value. Value is returned. This function must guarantee\r | |
382 | that all PCI read and write operations are serialized.\r | |
383 | \r | |
384 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
385 | \r | |
386 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
387 | Register.\r | |
388 | @param Value The value to write.\r | |
389 | \r | |
390 | @return The value written to the PCI configuration register.\r | |
391 | \r | |
392 | **/\r | |
393 | UINT8\r | |
394 | EFIAPI\r | |
395 | PciExpressWrite8 (\r | |
396 | IN UINTN Address,\r | |
397 | IN UINT8 Value\r | |
398 | )\r | |
399 | {\r | |
400 | return MmioWrite8 (GetPciExpressAddress (Address), Value);\r | |
401 | }\r | |
402 | \r | |
403 | /**\r | |
62991af2 | 404 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
93b5b853 | 405 | an 8-bit value.\r |
406 | \r | |
407 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 408 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 409 | OrData, and writes the result to the 8-bit PCI configuration register\r |
410 | specified by Address. The value written to the PCI configuration register is\r | |
411 | returned. This function must guarantee that all PCI read and write operations\r | |
412 | are serialized.\r | |
413 | \r | |
414 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
415 | \r | |
416 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
417 | Register.\r | |
418 | @param OrData The value to OR with the PCI configuration register.\r | |
419 | \r | |
420 | @return The value written back to the PCI configuration register.\r | |
421 | \r | |
422 | **/\r | |
423 | UINT8\r | |
424 | EFIAPI\r | |
425 | PciExpressOr8 (\r | |
426 | IN UINTN Address,\r | |
427 | IN UINT8 OrData\r | |
428 | )\r | |
429 | {\r | |
430 | return MmioOr8 (GetPciExpressAddress (Address), OrData);\r | |
431 | }\r | |
432 | \r | |
433 | /**\r | |
434 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
435 | value.\r | |
436 | \r | |
437 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
438 | bitwise AND between the read result and the value specified by AndData, and\r | |
439 | writes the result to the 8-bit PCI configuration register specified by\r | |
440 | Address. The value written to the PCI configuration register is returned.\r | |
441 | This function must guarantee that all PCI read and write operations are\r | |
442 | serialized.\r | |
443 | \r | |
444 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
445 | \r | |
446 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
447 | Register.\r | |
448 | @param AndData The value to AND with the PCI configuration register.\r | |
449 | \r | |
450 | @return The value written back to the PCI configuration register.\r | |
451 | \r | |
452 | **/\r | |
453 | UINT8\r | |
454 | EFIAPI\r | |
455 | PciExpressAnd8 (\r | |
456 | IN UINTN Address,\r | |
457 | IN UINT8 AndData\r | |
458 | )\r | |
459 | {\r | |
460 | return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r | |
461 | }\r | |
462 | \r | |
463 | /**\r | |
464 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 465 | value, followed a bitwise OR with another 8-bit value.\r |
93b5b853 | 466 | \r |
467 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
468 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 469 | performs a bitwise OR between the result of the AND operation and\r |
93b5b853 | 470 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
471 | configuration register specified by Address. The value written to the PCI\r | |
472 | configuration register is returned. This function must guarantee that all PCI\r | |
473 | read and write operations are serialized.\r | |
474 | \r | |
475 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
476 | \r | |
477 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
478 | Register.\r | |
479 | @param AndData The value to AND with the PCI configuration register.\r | |
480 | @param OrData The value to OR with the result of the AND operation.\r | |
481 | \r | |
482 | @return The value written back to the PCI configuration register.\r | |
483 | \r | |
484 | **/\r | |
485 | UINT8\r | |
486 | EFIAPI\r | |
487 | PciExpressAndThenOr8 (\r | |
488 | IN UINTN Address,\r | |
489 | IN UINT8 AndData,\r | |
490 | IN UINT8 OrData\r | |
491 | )\r | |
492 | {\r | |
493 | return MmioAndThenOr8 (\r | |
494 | GetPciExpressAddress (Address),\r | |
495 | AndData,\r | |
496 | OrData\r | |
497 | );\r | |
498 | }\r | |
499 | \r | |
500 | /**\r | |
501 | Reads a bit field of a PCI configuration register.\r | |
502 | \r | |
503 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
504 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
505 | returned.\r | |
506 | \r | |
507 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
508 | If StartBit is greater than 7, then ASSERT().\r | |
509 | If EndBit is greater than 7, then ASSERT().\r | |
510 | If EndBit is less than StartBit, then ASSERT().\r | |
511 | \r | |
512 | @param Address PCI configuration register to read.\r | |
513 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
514 | Range 0..7.\r | |
515 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
516 | Range 0..7.\r | |
517 | \r | |
518 | @return The value of the bit field read from the PCI configuration register.\r | |
519 | \r | |
520 | **/\r | |
521 | UINT8\r | |
522 | EFIAPI\r | |
523 | PciExpressBitFieldRead8 (\r | |
524 | IN UINTN Address,\r | |
525 | IN UINTN StartBit,\r | |
526 | IN UINTN EndBit\r | |
527 | )\r | |
528 | {\r | |
529 | return MmioBitFieldRead8 (\r | |
530 | GetPciExpressAddress (Address),\r | |
531 | StartBit,\r | |
532 | EndBit\r | |
533 | );\r | |
534 | }\r | |
535 | \r | |
536 | /**\r | |
537 | Writes a bit field to a PCI configuration register.\r | |
538 | \r | |
539 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
540 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
541 | destination PCI configuration register are preserved. The new value of the\r | |
542 | 8-bit register is returned.\r | |
543 | \r | |
544 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
545 | If StartBit is greater than 7, then ASSERT().\r | |
546 | If EndBit is greater than 7, then ASSERT().\r | |
547 | If EndBit is less than StartBit, then ASSERT().\r | |
548 | \r | |
549 | @param Address PCI configuration register to write.\r | |
550 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
551 | Range 0..7.\r | |
552 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
553 | Range 0..7.\r | |
554 | @param Value New value of the bit field.\r | |
555 | \r | |
556 | @return The value written back to the PCI configuration register.\r | |
557 | \r | |
558 | **/\r | |
559 | UINT8\r | |
560 | EFIAPI\r | |
561 | PciExpressBitFieldWrite8 (\r | |
562 | IN UINTN Address,\r | |
563 | IN UINTN StartBit,\r | |
564 | IN UINTN EndBit,\r | |
565 | IN UINT8 Value\r | |
566 | )\r | |
567 | {\r | |
568 | return MmioBitFieldWrite8 (\r | |
569 | GetPciExpressAddress (Address),\r | |
570 | StartBit,\r | |
571 | EndBit,\r | |
572 | Value\r | |
573 | );\r | |
574 | }\r | |
575 | \r | |
576 | /**\r | |
577 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
578 | writes the result back to the bit field in the 8-bit port.\r | |
579 | \r | |
580 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 581 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 582 | OrData, and writes the result to the 8-bit PCI configuration register\r |
583 | specified by Address. The value written to the PCI configuration register is\r | |
584 | returned. This function must guarantee that all PCI read and write operations\r | |
585 | are serialized. Extra left bits in OrData are stripped.\r | |
586 | \r | |
587 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
588 | If StartBit is greater than 7, then ASSERT().\r | |
589 | If EndBit is greater than 7, then ASSERT().\r | |
590 | If EndBit is less than StartBit, then ASSERT().\r | |
591 | \r | |
592 | @param Address PCI configuration register to write.\r | |
593 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
594 | Range 0..7.\r | |
595 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
596 | Range 0..7.\r | |
597 | @param OrData The value to OR with the PCI configuration register.\r | |
598 | \r | |
599 | @return The value written back to the PCI configuration register.\r | |
600 | \r | |
601 | **/\r | |
602 | UINT8\r | |
603 | EFIAPI\r | |
604 | PciExpressBitFieldOr8 (\r | |
605 | IN UINTN Address,\r | |
606 | IN UINTN StartBit,\r | |
607 | IN UINTN EndBit,\r | |
608 | IN UINT8 OrData\r | |
609 | )\r | |
610 | {\r | |
611 | return MmioBitFieldOr8 (\r | |
612 | GetPciExpressAddress (Address),\r | |
613 | StartBit,\r | |
614 | EndBit,\r | |
615 | OrData\r | |
616 | );\r | |
617 | }\r | |
618 | \r | |
619 | /**\r | |
620 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
621 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
622 | \r | |
623 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
624 | bitwise AND between the read result and the value specified by AndData, and\r | |
625 | writes the result to the 8-bit PCI configuration register specified by\r | |
626 | Address. The value written to the PCI configuration register is returned.\r | |
627 | This function must guarantee that all PCI read and write operations are\r | |
628 | serialized. Extra left bits in AndData are stripped.\r | |
629 | \r | |
630 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
631 | If StartBit is greater than 7, then ASSERT().\r | |
632 | If EndBit is greater than 7, then ASSERT().\r | |
633 | If EndBit is less than StartBit, then ASSERT().\r | |
634 | \r | |
635 | @param Address PCI configuration register to write.\r | |
636 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
637 | Range 0..7.\r | |
638 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
639 | Range 0..7.\r | |
640 | @param AndData The value to AND with the PCI configuration register.\r | |
641 | \r | |
642 | @return The value written back to the PCI configuration register.\r | |
643 | \r | |
644 | **/\r | |
645 | UINT8\r | |
646 | EFIAPI\r | |
647 | PciExpressBitFieldAnd8 (\r | |
648 | IN UINTN Address,\r | |
649 | IN UINTN StartBit,\r | |
650 | IN UINTN EndBit,\r | |
651 | IN UINT8 AndData\r | |
652 | )\r | |
653 | {\r | |
654 | return MmioBitFieldAnd8 (\r | |
655 | GetPciExpressAddress (Address),\r | |
656 | StartBit,\r | |
657 | EndBit,\r | |
658 | AndData\r | |
659 | );\r | |
660 | }\r | |
661 | \r | |
662 | /**\r | |
663 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 664 | bitwise OR, and writes the result back to the bit field in the\r |
93b5b853 | 665 | 8-bit port.\r |
666 | \r | |
667 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 668 | bitwise AND followed by a bitwise OR between the read result and\r |
93b5b853 | 669 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
670 | configuration register specified by Address. The value written to the PCI\r | |
671 | configuration register is returned. This function must guarantee that all PCI\r | |
672 | read and write operations are serialized. Extra left bits in both AndData and\r | |
673 | OrData are stripped.\r | |
674 | \r | |
675 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
676 | If StartBit is greater than 7, then ASSERT().\r | |
677 | If EndBit is greater than 7, then ASSERT().\r | |
678 | If EndBit is less than StartBit, then ASSERT().\r | |
679 | \r | |
680 | @param Address PCI configuration register to write.\r | |
681 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
682 | Range 0..7.\r | |
683 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
684 | Range 0..7.\r | |
685 | @param AndData The value to AND with the PCI configuration register.\r | |
686 | @param OrData The value to OR with the result of the AND operation.\r | |
687 | \r | |
688 | @return The value written back to the PCI configuration register.\r | |
689 | \r | |
690 | **/\r | |
691 | UINT8\r | |
692 | EFIAPI\r | |
693 | PciExpressBitFieldAndThenOr8 (\r | |
694 | IN UINTN Address,\r | |
695 | IN UINTN StartBit,\r | |
696 | IN UINTN EndBit,\r | |
697 | IN UINT8 AndData,\r | |
698 | IN UINT8 OrData\r | |
699 | )\r | |
700 | {\r | |
701 | return MmioBitFieldAndThenOr8 (\r | |
702 | GetPciExpressAddress (Address),\r | |
703 | StartBit,\r | |
704 | EndBit,\r | |
705 | AndData,\r | |
706 | OrData\r | |
707 | );\r | |
708 | }\r | |
709 | \r | |
710 | /**\r | |
711 | Reads a 16-bit PCI configuration register.\r | |
712 | \r | |
713 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
714 | This function must guarantee that all PCI read and write operations are\r | |
715 | serialized.\r | |
716 | \r | |
717 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
718 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
719 | \r | |
720 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
721 | Register.\r | |
722 | \r | |
723 | @return The read value from the PCI configuration register.\r | |
724 | \r | |
725 | **/\r | |
726 | UINT16\r | |
727 | EFIAPI\r | |
728 | PciExpressRead16 (\r | |
729 | IN UINTN Address\r | |
730 | )\r | |
731 | {\r | |
732 | return MmioRead16 (GetPciExpressAddress (Address));\r | |
733 | }\r | |
734 | \r | |
735 | /**\r | |
736 | Writes a 16-bit PCI configuration register.\r | |
737 | \r | |
738 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
739 | value specified by Value. Value is returned. This function must guarantee\r | |
740 | that all PCI read and write operations are serialized.\r | |
741 | \r | |
742 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
743 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
744 | \r | |
745 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
746 | Register.\r | |
747 | @param Value The value to write.\r | |
748 | \r | |
749 | @return The value written to the PCI configuration register.\r | |
750 | \r | |
751 | **/\r | |
752 | UINT16\r | |
753 | EFIAPI\r | |
754 | PciExpressWrite16 (\r | |
755 | IN UINTN Address,\r | |
756 | IN UINT16 Value\r | |
757 | )\r | |
758 | {\r | |
759 | return MmioWrite16 (GetPciExpressAddress (Address), Value);\r | |
760 | }\r | |
761 | \r | |
762 | /**\r | |
62991af2 | 763 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
93b5b853 | 764 | a 16-bit value.\r |
765 | \r | |
766 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 767 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 768 | OrData, and writes the result to the 16-bit PCI configuration register\r |
769 | specified by Address. The value written to the PCI configuration register is\r | |
770 | returned. This function must guarantee that all PCI read and write operations\r | |
771 | are serialized.\r | |
772 | \r | |
773 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
774 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
775 | \r | |
776 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
777 | Register.\r | |
778 | @param OrData The value to OR with the PCI configuration register.\r | |
779 | \r | |
780 | @return The value written back to the PCI configuration register.\r | |
781 | \r | |
782 | **/\r | |
783 | UINT16\r | |
784 | EFIAPI\r | |
785 | PciExpressOr16 (\r | |
786 | IN UINTN Address,\r | |
787 | IN UINT16 OrData\r | |
788 | )\r | |
789 | {\r | |
790 | return MmioOr16 (GetPciExpressAddress (Address), OrData);\r | |
791 | }\r | |
792 | \r | |
793 | /**\r | |
794 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
795 | value.\r | |
796 | \r | |
797 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
798 | bitwise AND between the read result and the value specified by AndData, and\r | |
799 | writes the result to the 16-bit PCI configuration register specified by\r | |
800 | Address. The value written to the PCI configuration register is returned.\r | |
801 | This function must guarantee that all PCI read and write operations are\r | |
802 | serialized.\r | |
803 | \r | |
804 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
805 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
806 | \r | |
807 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
808 | Register.\r | |
809 | @param AndData The value to AND with the PCI configuration register.\r | |
810 | \r | |
811 | @return The value written back to the PCI configuration register.\r | |
812 | \r | |
813 | **/\r | |
814 | UINT16\r | |
815 | EFIAPI\r | |
816 | PciExpressAnd16 (\r | |
817 | IN UINTN Address,\r | |
818 | IN UINT16 AndData\r | |
819 | )\r | |
820 | {\r | |
821 | return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r | |
822 | }\r | |
823 | \r | |
824 | /**\r | |
825 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 826 | value, followed a bitwise OR with another 16-bit value.\r |
93b5b853 | 827 | \r |
828 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
829 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 830 | performs a bitwise OR between the result of the AND operation and\r |
93b5b853 | 831 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
832 | configuration register specified by Address. The value written to the PCI\r | |
833 | configuration register is returned. This function must guarantee that all PCI\r | |
834 | read and write operations are serialized.\r | |
835 | \r | |
836 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
837 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
838 | \r | |
839 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
840 | Register.\r | |
841 | @param AndData The value to AND with the PCI configuration register.\r | |
842 | @param OrData The value to OR with the result of the AND operation.\r | |
843 | \r | |
844 | @return The value written back to the PCI configuration register.\r | |
845 | \r | |
846 | **/\r | |
847 | UINT16\r | |
848 | EFIAPI\r | |
849 | PciExpressAndThenOr16 (\r | |
850 | IN UINTN Address,\r | |
851 | IN UINT16 AndData,\r | |
852 | IN UINT16 OrData\r | |
853 | )\r | |
854 | {\r | |
855 | return MmioAndThenOr16 (\r | |
856 | GetPciExpressAddress (Address),\r | |
857 | AndData,\r | |
858 | OrData\r | |
859 | );\r | |
860 | }\r | |
861 | \r | |
862 | /**\r | |
863 | Reads a bit field of a PCI configuration register.\r | |
864 | \r | |
865 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
866 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
867 | returned.\r | |
868 | \r | |
869 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
870 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
871 | If StartBit is greater than 15, then ASSERT().\r | |
872 | If EndBit is greater than 15, then ASSERT().\r | |
873 | If EndBit is less than StartBit, then ASSERT().\r | |
874 | \r | |
875 | @param Address PCI configuration register to read.\r | |
876 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
877 | Range 0..15.\r | |
878 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
879 | Range 0..15.\r | |
880 | \r | |
881 | @return The value of the bit field read from the PCI configuration register.\r | |
882 | \r | |
883 | **/\r | |
884 | UINT16\r | |
885 | EFIAPI\r | |
886 | PciExpressBitFieldRead16 (\r | |
887 | IN UINTN Address,\r | |
888 | IN UINTN StartBit,\r | |
889 | IN UINTN EndBit\r | |
890 | )\r | |
891 | {\r | |
892 | return MmioBitFieldRead16 (\r | |
893 | GetPciExpressAddress (Address),\r | |
894 | StartBit,\r | |
895 | EndBit\r | |
896 | );\r | |
897 | }\r | |
898 | \r | |
899 | /**\r | |
900 | Writes a bit field to a PCI configuration register.\r | |
901 | \r | |
902 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
903 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
904 | destination PCI configuration register are preserved. The new value of the\r | |
905 | 16-bit register is returned.\r | |
906 | \r | |
907 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
908 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
909 | If StartBit is greater than 15, then ASSERT().\r | |
910 | If EndBit is greater than 15, then ASSERT().\r | |
911 | If EndBit is less than StartBit, then ASSERT().\r | |
912 | \r | |
913 | @param Address PCI configuration register to write.\r | |
914 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
915 | Range 0..15.\r | |
916 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
917 | Range 0..15.\r | |
918 | @param Value New value of the bit field.\r | |
919 | \r | |
920 | @return The value written back to the PCI configuration register.\r | |
921 | \r | |
922 | **/\r | |
923 | UINT16\r | |
924 | EFIAPI\r | |
925 | PciExpressBitFieldWrite16 (\r | |
926 | IN UINTN Address,\r | |
927 | IN UINTN StartBit,\r | |
928 | IN UINTN EndBit,\r | |
929 | IN UINT16 Value\r | |
930 | )\r | |
931 | {\r | |
932 | return MmioBitFieldWrite16 (\r | |
933 | GetPciExpressAddress (Address),\r | |
934 | StartBit,\r | |
935 | EndBit,\r | |
936 | Value\r | |
937 | );\r | |
938 | }\r | |
939 | \r | |
940 | /**\r | |
941 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
942 | writes the result back to the bit field in the 16-bit port.\r | |
943 | \r | |
944 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 945 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 946 | OrData, and writes the result to the 16-bit PCI configuration register\r |
947 | specified by Address. The value written to the PCI configuration register is\r | |
948 | returned. This function must guarantee that all PCI read and write operations\r | |
949 | are serialized. Extra left bits in OrData are stripped.\r | |
950 | \r | |
951 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
952 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
953 | If StartBit is greater than 15, then ASSERT().\r | |
954 | If EndBit is greater than 15, then ASSERT().\r | |
955 | If EndBit is less than StartBit, then ASSERT().\r | |
956 | \r | |
957 | @param Address PCI configuration register to write.\r | |
958 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
959 | Range 0..15.\r | |
960 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
961 | Range 0..15.\r | |
962 | @param OrData The value to OR with the PCI configuration register.\r | |
963 | \r | |
964 | @return The value written back to the PCI configuration register.\r | |
965 | \r | |
966 | **/\r | |
967 | UINT16\r | |
968 | EFIAPI\r | |
969 | PciExpressBitFieldOr16 (\r | |
970 | IN UINTN Address,\r | |
971 | IN UINTN StartBit,\r | |
972 | IN UINTN EndBit,\r | |
973 | IN UINT16 OrData\r | |
974 | )\r | |
975 | {\r | |
976 | return MmioBitFieldOr16 (\r | |
977 | GetPciExpressAddress (Address),\r | |
978 | StartBit,\r | |
979 | EndBit,\r | |
980 | OrData\r | |
981 | );\r | |
982 | }\r | |
983 | \r | |
984 | /**\r | |
985 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
986 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
987 | \r | |
988 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
989 | bitwise AND between the read result and the value specified by AndData, and\r | |
990 | writes the result to the 16-bit PCI configuration register specified by\r | |
991 | Address. The value written to the PCI configuration register is returned.\r | |
992 | This function must guarantee that all PCI read and write operations are\r | |
993 | serialized. Extra left bits in AndData are stripped.\r | |
994 | \r | |
995 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
996 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
997 | If StartBit is greater than 15, then ASSERT().\r | |
998 | If EndBit is greater than 15, then ASSERT().\r | |
999 | If EndBit is less than StartBit, then ASSERT().\r | |
1000 | \r | |
1001 | @param Address PCI configuration register to write.\r | |
1002 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1003 | Range 0..15.\r | |
1004 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1005 | Range 0..15.\r | |
1006 | @param AndData The value to AND with the PCI configuration register.\r | |
1007 | \r | |
1008 | @return The value written back to the PCI configuration register.\r | |
1009 | \r | |
1010 | **/\r | |
1011 | UINT16\r | |
1012 | EFIAPI\r | |
1013 | PciExpressBitFieldAnd16 (\r | |
1014 | IN UINTN Address,\r | |
1015 | IN UINTN StartBit,\r | |
1016 | IN UINTN EndBit,\r | |
1017 | IN UINT16 AndData\r | |
1018 | )\r | |
1019 | {\r | |
1020 | return MmioBitFieldAnd16 (\r | |
1021 | GetPciExpressAddress (Address),\r | |
1022 | StartBit,\r | |
1023 | EndBit,\r | |
1024 | AndData\r | |
1025 | );\r | |
1026 | }\r | |
1027 | \r | |
1028 | /**\r | |
1029 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1030 | bitwise OR, and writes the result back to the bit field in the\r |
93b5b853 | 1031 | 16-bit port.\r |
1032 | \r | |
1033 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1034 | bitwise AND followed by a bitwise OR between the read result and\r |
93b5b853 | 1035 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
1036 | configuration register specified by Address. The value written to the PCI\r | |
1037 | configuration register is returned. This function must guarantee that all PCI\r | |
1038 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1039 | OrData are stripped.\r | |
1040 | \r | |
1041 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1042 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
1043 | If StartBit is greater than 15, then ASSERT().\r | |
1044 | If EndBit is greater than 15, then ASSERT().\r | |
1045 | If EndBit is less than StartBit, then ASSERT().\r | |
1046 | \r | |
1047 | @param Address PCI configuration register to write.\r | |
1048 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1049 | Range 0..15.\r | |
1050 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1051 | Range 0..15.\r | |
1052 | @param AndData The value to AND with the PCI configuration register.\r | |
1053 | @param OrData The value to OR with the result of the AND operation.\r | |
1054 | \r | |
1055 | @return The value written back to the PCI configuration register.\r | |
1056 | \r | |
1057 | **/\r | |
1058 | UINT16\r | |
1059 | EFIAPI\r | |
1060 | PciExpressBitFieldAndThenOr16 (\r | |
1061 | IN UINTN Address,\r | |
1062 | IN UINTN StartBit,\r | |
1063 | IN UINTN EndBit,\r | |
1064 | IN UINT16 AndData,\r | |
1065 | IN UINT16 OrData\r | |
1066 | )\r | |
1067 | {\r | |
1068 | return MmioBitFieldAndThenOr16 (\r | |
1069 | GetPciExpressAddress (Address),\r | |
1070 | StartBit,\r | |
1071 | EndBit,\r | |
1072 | AndData,\r | |
1073 | OrData\r | |
1074 | );\r | |
1075 | }\r | |
1076 | \r | |
1077 | /**\r | |
1078 | Reads a 32-bit PCI configuration register.\r | |
1079 | \r | |
1080 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
1081 | This function must guarantee that all PCI read and write operations are\r | |
1082 | serialized.\r | |
1083 | \r | |
1084 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1085 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1086 | \r | |
1087 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1088 | Register.\r | |
1089 | \r | |
1090 | @return The read value from the PCI configuration register.\r | |
1091 | \r | |
1092 | **/\r | |
1093 | UINT32\r | |
1094 | EFIAPI\r | |
1095 | PciExpressRead32 (\r | |
1096 | IN UINTN Address\r | |
1097 | )\r | |
1098 | {\r | |
1099 | return MmioRead32 (GetPciExpressAddress (Address));\r | |
1100 | }\r | |
1101 | \r | |
1102 | /**\r | |
1103 | Writes a 32-bit PCI configuration register.\r | |
1104 | \r | |
1105 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
1106 | value specified by Value. Value is returned. This function must guarantee\r | |
1107 | that all PCI read and write operations are serialized.\r | |
1108 | \r | |
1109 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1110 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1111 | \r | |
1112 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1113 | Register.\r | |
1114 | @param Value The value to write.\r | |
1115 | \r | |
1116 | @return The value written to the PCI configuration register.\r | |
1117 | \r | |
1118 | **/\r | |
1119 | UINT32\r | |
1120 | EFIAPI\r | |
1121 | PciExpressWrite32 (\r | |
1122 | IN UINTN Address,\r | |
1123 | IN UINT32 Value\r | |
1124 | )\r | |
1125 | {\r | |
1126 | return MmioWrite32 (GetPciExpressAddress (Address), Value);\r | |
1127 | }\r | |
1128 | \r | |
1129 | /**\r | |
62991af2 | 1130 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
93b5b853 | 1131 | a 32-bit value.\r |
1132 | \r | |
1133 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1134 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 1135 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1136 | specified by Address. The value written to the PCI configuration register is\r | |
1137 | returned. This function must guarantee that all PCI read and write operations\r | |
1138 | are serialized.\r | |
1139 | \r | |
1140 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1141 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1142 | \r | |
1143 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1144 | Register.\r | |
1145 | @param OrData The value to OR with the PCI configuration register.\r | |
1146 | \r | |
1147 | @return The value written back to the PCI configuration register.\r | |
1148 | \r | |
1149 | **/\r | |
1150 | UINT32\r | |
1151 | EFIAPI\r | |
1152 | PciExpressOr32 (\r | |
1153 | IN UINTN Address,\r | |
1154 | IN UINT32 OrData\r | |
1155 | )\r | |
1156 | {\r | |
1157 | return MmioOr32 (GetPciExpressAddress (Address), OrData);\r | |
1158 | }\r | |
1159 | \r | |
1160 | /**\r | |
1161 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
1162 | value.\r | |
1163 | \r | |
1164 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1165 | bitwise AND between the read result and the value specified by AndData, and\r | |
1166 | writes the result to the 32-bit PCI configuration register specified by\r | |
1167 | Address. The value written to the PCI configuration register is returned.\r | |
1168 | This function must guarantee that all PCI read and write operations are\r | |
1169 | serialized.\r | |
1170 | \r | |
1171 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1172 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1173 | \r | |
1174 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1175 | Register.\r | |
1176 | @param AndData The value to AND with the PCI configuration register.\r | |
1177 | \r | |
1178 | @return The value written back to the PCI configuration register.\r | |
1179 | \r | |
1180 | **/\r | |
1181 | UINT32\r | |
1182 | EFIAPI\r | |
1183 | PciExpressAnd32 (\r | |
1184 | IN UINTN Address,\r | |
1185 | IN UINT32 AndData\r | |
1186 | )\r | |
1187 | {\r | |
1188 | return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r | |
1189 | }\r | |
1190 | \r | |
1191 | /**\r | |
1192 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 1193 | value, followed a bitwise OR with another 32-bit value.\r |
93b5b853 | 1194 | \r |
1195 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1196 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 1197 | performs a bitwise OR between the result of the AND operation and\r |
93b5b853 | 1198 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
1199 | configuration register specified by Address. The value written to the PCI\r | |
1200 | configuration register is returned. This function must guarantee that all PCI\r | |
1201 | read and write operations are serialized.\r | |
1202 | \r | |
1203 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1204 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1205 | \r | |
1206 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1207 | Register.\r | |
1208 | @param AndData The value to AND with the PCI configuration register.\r | |
1209 | @param OrData The value to OR with the result of the AND operation.\r | |
1210 | \r | |
1211 | @return The value written back to the PCI configuration register.\r | |
1212 | \r | |
1213 | **/\r | |
1214 | UINT32\r | |
1215 | EFIAPI\r | |
1216 | PciExpressAndThenOr32 (\r | |
1217 | IN UINTN Address,\r | |
1218 | IN UINT32 AndData,\r | |
1219 | IN UINT32 OrData\r | |
1220 | )\r | |
1221 | {\r | |
1222 | return MmioAndThenOr32 (\r | |
1223 | GetPciExpressAddress (Address),\r | |
1224 | AndData,\r | |
1225 | OrData\r | |
1226 | );\r | |
1227 | }\r | |
1228 | \r | |
1229 | /**\r | |
1230 | Reads a bit field of a PCI configuration register.\r | |
1231 | \r | |
1232 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1233 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1234 | returned.\r | |
1235 | \r | |
1236 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1237 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1238 | If StartBit is greater than 31, then ASSERT().\r | |
1239 | If EndBit is greater than 31, then ASSERT().\r | |
1240 | If EndBit is less than StartBit, then ASSERT().\r | |
1241 | \r | |
1242 | @param Address PCI configuration register to read.\r | |
1243 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1244 | Range 0..31.\r | |
1245 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1246 | Range 0..31.\r | |
1247 | \r | |
1248 | @return The value of the bit field read from the PCI configuration register.\r | |
1249 | \r | |
1250 | **/\r | |
1251 | UINT32\r | |
1252 | EFIAPI\r | |
1253 | PciExpressBitFieldRead32 (\r | |
1254 | IN UINTN Address,\r | |
1255 | IN UINTN StartBit,\r | |
1256 | IN UINTN EndBit\r | |
1257 | )\r | |
1258 | {\r | |
1259 | return MmioBitFieldRead32 (\r | |
1260 | GetPciExpressAddress (Address),\r | |
1261 | StartBit,\r | |
1262 | EndBit\r | |
1263 | );\r | |
1264 | }\r | |
1265 | \r | |
1266 | /**\r | |
1267 | Writes a bit field to a PCI configuration register.\r | |
1268 | \r | |
1269 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1270 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1271 | destination PCI configuration register are preserved. The new value of the\r | |
1272 | 32-bit register is returned.\r | |
1273 | \r | |
1274 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1275 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1276 | If StartBit is greater than 31, then ASSERT().\r | |
1277 | If EndBit is greater than 31, then ASSERT().\r | |
1278 | If EndBit is less than StartBit, then ASSERT().\r | |
1279 | \r | |
1280 | @param Address PCI configuration register to write.\r | |
1281 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1282 | Range 0..31.\r | |
1283 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1284 | Range 0..31.\r | |
1285 | @param Value New value of the bit field.\r | |
1286 | \r | |
1287 | @return The value written back to the PCI configuration register.\r | |
1288 | \r | |
1289 | **/\r | |
1290 | UINT32\r | |
1291 | EFIAPI\r | |
1292 | PciExpressBitFieldWrite32 (\r | |
1293 | IN UINTN Address,\r | |
1294 | IN UINTN StartBit,\r | |
1295 | IN UINTN EndBit,\r | |
1296 | IN UINT32 Value\r | |
1297 | )\r | |
1298 | {\r | |
1299 | return MmioBitFieldWrite32 (\r | |
1300 | GetPciExpressAddress (Address),\r | |
1301 | StartBit,\r | |
1302 | EndBit,\r | |
1303 | Value\r | |
1304 | );\r | |
1305 | }\r | |
1306 | \r | |
1307 | /**\r | |
1308 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1309 | writes the result back to the bit field in the 32-bit port.\r | |
1310 | \r | |
1311 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1312 | bitwise OR between the read result and the value specified by\r |
93b5b853 | 1313 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1314 | specified by Address. The value written to the PCI configuration register is\r | |
1315 | returned. This function must guarantee that all PCI read and write operations\r | |
1316 | are serialized. Extra left bits in OrData are stripped.\r | |
1317 | \r | |
1318 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1319 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1320 | If StartBit is greater than 31, then ASSERT().\r | |
1321 | If EndBit is greater than 31, then ASSERT().\r | |
1322 | If EndBit is less than StartBit, then ASSERT().\r | |
1323 | \r | |
1324 | @param Address PCI configuration register to write.\r | |
1325 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1326 | Range 0..31.\r | |
1327 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1328 | Range 0..31.\r | |
1329 | @param OrData The value to OR with the PCI configuration register.\r | |
1330 | \r | |
1331 | @return The value written back to the PCI configuration register.\r | |
1332 | \r | |
1333 | **/\r | |
1334 | UINT32\r | |
1335 | EFIAPI\r | |
1336 | PciExpressBitFieldOr32 (\r | |
1337 | IN UINTN Address,\r | |
1338 | IN UINTN StartBit,\r | |
1339 | IN UINTN EndBit,\r | |
1340 | IN UINT32 OrData\r | |
1341 | )\r | |
1342 | {\r | |
1343 | return MmioBitFieldOr32 (\r | |
1344 | GetPciExpressAddress (Address),\r | |
1345 | StartBit,\r | |
1346 | EndBit,\r | |
1347 | OrData\r | |
1348 | );\r | |
1349 | }\r | |
1350 | \r | |
1351 | /**\r | |
1352 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1353 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1354 | \r | |
1355 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1356 | bitwise AND between the read result and the value specified by AndData, and\r | |
1357 | writes the result to the 32-bit PCI configuration register specified by\r | |
1358 | Address. The value written to the PCI configuration register is returned.\r | |
1359 | This function must guarantee that all PCI read and write operations are\r | |
1360 | serialized. Extra left bits in AndData are stripped.\r | |
1361 | \r | |
1362 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1363 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1364 | If StartBit is greater than 31, then ASSERT().\r | |
1365 | If EndBit is greater than 31, then ASSERT().\r | |
1366 | If EndBit is less than StartBit, then ASSERT().\r | |
1367 | \r | |
1368 | @param Address PCI configuration register to write.\r | |
1369 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1370 | Range 0..31.\r | |
1371 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1372 | Range 0..31.\r | |
1373 | @param AndData The value to AND with the PCI configuration register.\r | |
1374 | \r | |
1375 | @return The value written back to the PCI configuration register.\r | |
1376 | \r | |
1377 | **/\r | |
1378 | UINT32\r | |
1379 | EFIAPI\r | |
1380 | PciExpressBitFieldAnd32 (\r | |
1381 | IN UINTN Address,\r | |
1382 | IN UINTN StartBit,\r | |
1383 | IN UINTN EndBit,\r | |
1384 | IN UINT32 AndData\r | |
1385 | )\r | |
1386 | {\r | |
1387 | return MmioBitFieldAnd32 (\r | |
1388 | GetPciExpressAddress (Address),\r | |
1389 | StartBit,\r | |
1390 | EndBit,\r | |
1391 | AndData\r | |
1392 | );\r | |
1393 | }\r | |
1394 | \r | |
1395 | /**\r | |
1396 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1397 | bitwise OR, and writes the result back to the bit field in the\r |
93b5b853 | 1398 | 32-bit port.\r |
1399 | \r | |
1400 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1401 | bitwise AND followed by a bitwise OR between the read result and\r |
93b5b853 | 1402 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1403 | configuration register specified by Address. The value written to the PCI\r | |
1404 | configuration register is returned. This function must guarantee that all PCI\r | |
1405 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1406 | OrData are stripped.\r | |
1407 | \r | |
1408 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1409 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1410 | If StartBit is greater than 31, then ASSERT().\r | |
1411 | If EndBit is greater than 31, then ASSERT().\r | |
1412 | If EndBit is less than StartBit, then ASSERT().\r | |
1413 | \r | |
1414 | @param Address PCI configuration register to write.\r | |
1415 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1416 | Range 0..31.\r | |
1417 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1418 | Range 0..31.\r | |
1419 | @param AndData The value to AND with the PCI configuration register.\r | |
1420 | @param OrData The value to OR with the result of the AND operation.\r | |
1421 | \r | |
1422 | @return The value written back to the PCI configuration register.\r | |
1423 | \r | |
1424 | **/\r | |
1425 | UINT32\r | |
1426 | EFIAPI\r | |
1427 | PciExpressBitFieldAndThenOr32 (\r | |
1428 | IN UINTN Address,\r | |
1429 | IN UINTN StartBit,\r | |
1430 | IN UINTN EndBit,\r | |
1431 | IN UINT32 AndData,\r | |
1432 | IN UINT32 OrData\r | |
1433 | )\r | |
1434 | {\r | |
1435 | return MmioBitFieldAndThenOr32 (\r | |
1436 | GetPciExpressAddress (Address),\r | |
1437 | StartBit,\r | |
1438 | EndBit,\r | |
1439 | AndData,\r | |
1440 | OrData\r | |
1441 | );\r | |
1442 | }\r | |
1443 | \r | |
1444 | /**\r | |
1445 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1446 | \r | |
1447 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1448 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1449 | configuration registers from a single PCI function to be read. Size is\r | |
1450 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1451 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1452 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1453 | end of the range.\r | |
1454 | \r | |
1455 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1456 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1457 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1458 | \r | |
1459 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1460 | Function and Register.\r | |
1461 | @param Size Size in bytes of the transfer.\r | |
1462 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1463 | \r | |
518db1d9 | 1464 | @return Size read data from StartAddress.\r |
93b5b853 | 1465 | \r |
1466 | **/\r | |
1467 | UINTN\r | |
1468 | EFIAPI\r | |
1469 | PciExpressReadBuffer (\r | |
1470 | IN UINTN StartAddress,\r | |
1471 | IN UINTN Size,\r | |
1472 | OUT VOID *Buffer\r | |
1473 | )\r | |
1474 | {\r | |
1475 | UINTN ReturnValue;\r | |
1476 | \r | |
d908a2d6 | 1477 | //\r |
1478 | // Make sure Address is valid\r | |
1479 | //\r | |
1480 | ASSERT (((StartAddress) & ~0xfffffff) == 0);\r | |
93b5b853 | 1481 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1482 | \r | |
1483 | if (Size == 0) {\r | |
1484 | return Size;\r | |
1485 | }\r | |
1486 | \r | |
1487 | ASSERT (Buffer != NULL);\r | |
1488 | \r | |
1489 | //\r | |
1490 | // Save Size for return\r | |
1491 | //\r | |
1492 | ReturnValue = Size;\r | |
1493 | \r | |
1494 | if ((StartAddress & 1) != 0) {\r | |
1495 | //\r | |
1496 | // Read a byte if StartAddress is byte aligned\r | |
1497 | //\r | |
1498 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1499 | StartAddress += sizeof (UINT8);\r | |
1500 | Size -= sizeof (UINT8);\r | |
1501 | Buffer = (UINT8*)Buffer + 1;\r | |
1502 | }\r | |
1503 | \r | |
1504 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1505 | //\r | |
1506 | // Read a word if StartAddress is word aligned\r | |
1507 | //\r | |
1508 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1509 | \r | |
1510 | StartAddress += sizeof (UINT16);\r | |
1511 | Size -= sizeof (UINT16);\r | |
1512 | Buffer = (UINT16*)Buffer + 1;\r | |
1513 | }\r | |
1514 | \r | |
1515 | while (Size >= sizeof (UINT32)) {\r | |
1516 | //\r | |
1517 | // Read as many double words as possible\r | |
1518 | //\r | |
1519 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r | |
1520 | \r | |
1521 | StartAddress += sizeof (UINT32);\r | |
1522 | Size -= sizeof (UINT32);\r | |
1523 | Buffer = (UINT32*)Buffer + 1;\r | |
1524 | }\r | |
1525 | \r | |
1526 | if (Size >= sizeof (UINT16)) {\r | |
1527 | //\r | |
1528 | // Read the last remaining word if exist\r | |
1529 | //\r | |
1530 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r | |
1531 | StartAddress += sizeof (UINT16);\r | |
1532 | Size -= sizeof (UINT16);\r | |
1533 | Buffer = (UINT16*)Buffer + 1;\r | |
1534 | }\r | |
1535 | \r | |
1536 | if (Size >= sizeof (UINT8)) {\r | |
1537 | //\r | |
1538 | // Read the last remaining byte if exist\r | |
1539 | //\r | |
1540 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r | |
1541 | }\r | |
1542 | \r | |
1543 | return ReturnValue;\r | |
1544 | }\r | |
1545 | \r | |
1546 | /**\r | |
1547 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1548 | configuration space.\r | |
1549 | \r | |
1550 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1551 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1552 | configuration registers from a single PCI function to be written. Size is\r | |
1553 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1554 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1555 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1556 | and the end of the range.\r | |
1557 | \r | |
1558 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1559 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1560 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1561 | \r | |
1562 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1563 | Function and Register.\r | |
1564 | @param Size Size in bytes of the transfer.\r | |
1565 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1566 | \r | |
518db1d9 | 1567 | @return Size written to StartAddress.\r |
93b5b853 | 1568 | \r |
1569 | **/\r | |
1570 | UINTN\r | |
1571 | EFIAPI\r | |
1572 | PciExpressWriteBuffer (\r | |
1573 | IN UINTN StartAddress,\r | |
1574 | IN UINTN Size,\r | |
1575 | IN VOID *Buffer\r | |
1576 | )\r | |
1577 | {\r | |
1578 | UINTN ReturnValue;\r | |
1579 | \r | |
d908a2d6 | 1580 | //\r |
1581 | // Make sure Address is valid\r | |
1582 | //\r | |
1583 | ASSERT (((StartAddress) & ~0xfffffff) == 0);\r | |
93b5b853 | 1584 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1585 | \r | |
1586 | if (Size == 0) {\r | |
1587 | return 0;\r | |
1588 | }\r | |
1589 | \r | |
1590 | ASSERT (Buffer != NULL);\r | |
1591 | \r | |
1592 | //\r | |
1593 | // Save Size for return\r | |
1594 | //\r | |
1595 | ReturnValue = Size;\r | |
1596 | \r | |
1597 | if ((StartAddress & 1) != 0) {\r | |
1598 | //\r | |
1599 | // Write a byte if StartAddress is byte aligned\r | |
1600 | //\r | |
1601 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1602 | StartAddress += sizeof (UINT8);\r | |
1603 | Size -= sizeof (UINT8);\r | |
1604 | Buffer = (UINT8*)Buffer + 1;\r | |
1605 | }\r | |
1606 | \r | |
1607 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r | |
1608 | //\r | |
1609 | // Write a word if StartAddress is word aligned\r | |
1610 | //\r | |
1611 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1612 | StartAddress += sizeof (UINT16);\r | |
1613 | Size -= sizeof (UINT16);\r | |
1614 | Buffer = (UINT16*)Buffer + 1;\r | |
1615 | }\r | |
1616 | \r | |
1617 | while (Size >= sizeof (UINT32)) {\r | |
1618 | //\r | |
1619 | // Write as many double words as possible\r | |
1620 | //\r | |
1621 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r | |
1622 | StartAddress += sizeof (UINT32);\r | |
1623 | Size -= sizeof (UINT32);\r | |
1624 | Buffer = (UINT32*)Buffer + 1;\r | |
1625 | }\r | |
1626 | \r | |
1627 | if (Size >= sizeof (UINT16)) {\r | |
1628 | //\r | |
1629 | // Write the last remaining word if exist\r | |
1630 | //\r | |
1631 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r | |
1632 | StartAddress += sizeof (UINT16);\r | |
1633 | Size -= sizeof (UINT16);\r | |
1634 | Buffer = (UINT16*)Buffer + 1;\r | |
1635 | }\r | |
1636 | \r | |
1637 | if (Size >= sizeof (UINT8)) {\r | |
1638 | //\r | |
1639 | // Write the last remaining byte if exist\r | |
1640 | //\r | |
1641 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1642 | }\r | |
1643 | \r | |
1644 | return ReturnValue;\r | |
1645 | }\r |