| 93b5b853 |
1 | /** @file\r |
| 2 | Functions in this library instance make use of MMIO functions in IoLib to\r |
| 3 | access memory mapped PCI configuration space.\r |
| 4 | \r |
| 5 | All assertions for I/O operations are handled in MMIO functions in the IoLib\r |
| 6 | Library.\r |
| 7 | \r |
| 8 | Copyright (c) 2006 - 2008, Intel Corporation<BR>\r |
| 9 | All rights reserved. This program and the accompanying materials\r |
| 10 | are licensed and made available under the terms and conditions of the BSD License\r |
| 11 | which accompanies this distribution. The full text of the license may be found at\r |
| 12 | http://opensource.org/licenses/bsd-license.php\r |
| 13 | \r |
| 14 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 15 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 16 | \r |
| 17 | **/\r |
| 18 | \r |
| 19 | \r |
| 20 | #include <PiDxe.h>\r |
| 21 | \r |
| 22 | #include <Library/BaseLib.h>\r |
| 23 | #include <Library/PciExpressLib.h>\r |
| 24 | #include <Library/IoLib.h>\r |
| 25 | #include <Library/DebugLib.h>\r |
| 26 | #include <Library/PcdLib.h>\r |
| 27 | #include <Library/MemoryAllocationLib.h>\r |
| 28 | #include <Library/UefiBootServicesTableLib.h>\r |
| 29 | #include <Library/DxeServicesTableLib.h>\r |
| 30 | #include <Library/UefiRuntimeLib.h>\r |
| 31 | \r |
| 32 | ///\r |
| 33 | /// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime\r |
| 34 | ///\r |
| 35 | typedef struct {\r |
| 36 | UINTN PhysicalAddress;\r |
| 37 | UINTN VirtualAddress;\r |
| 38 | } PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;\r |
| 39 | \r |
| 40 | ///\r |
| 41 | /// Set Virtual Address Map Event\r |
| 42 | ///\r |
| 43 | EFI_EVENT mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r |
| 44 | \r |
| 45 | ///\r |
| 46 | /// Module global that contains the base physical address of the PCI Express MMIO range\r |
| 47 | ///\r |
| 48 | UINTN mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r |
| 49 | \r |
| 50 | ///\r |
| 51 | /// The number of PCI devices that have been registered for runtime access\r |
| 52 | ///\r |
| 53 | UINTN mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r |
| 54 | \r |
| 55 | ///\r |
| 56 | /// The table of PCI devices that have been registered for runtime access\r |
| 57 | ///\r |
| 58 | PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE *mDxeRuntimePciExpressLibRegistrationTable = NULL;\r |
| 59 | \r |
| 60 | ///\r |
| 61 | /// The table index of the most recent virtual address lookup\r |
| 62 | ///\r |
| 63 | UINTN mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r |
| 64 | \r |
| 65 | \r |
| 66 | /**\r |
| 67 | Convert the physical PCI Express MMIO addresses for all registered PCI devices\r |
| 68 | to virtual addresses.\r |
| 69 | \r |
| 70 | @param[in] Event The Event that is being processed\r |
| 71 | @param[in] Context Event Context\r |
| 72 | **/\r |
| 73 | VOID\r |
| 74 | EFIAPI\r |
| 75 | DxeRuntimePciExpressLibVirtualNotify (\r |
| 76 | IN EFI_EVENT Event,\r |
| 77 | IN VOID *Context\r |
| 78 | )\r |
| 79 | {\r |
| 80 | UINTN Index;\r |
| 81 | \r |
| 82 | //\r |
| 83 | // If there have been no runtime registrations, then just return\r |
| 84 | //\r |
| 85 | if (mDxeRuntimePciExpressLibRegistrationTable == NULL) {\r |
| 86 | return;\r |
| 87 | }\r |
| 88 | \r |
| 89 | //\r |
| 90 | // Convert physical addresses associated with the set of registered PCI devices to\r |
| 91 | // virtual addresses.\r |
| 92 | //\r |
| 93 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r |
| 94 | EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r |
| 95 | }\r |
| 96 | \r |
| 97 | //\r |
| 98 | // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r |
| 99 | //\r |
| 100 | EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);\r |
| 101 | }\r |
| 102 | \r |
| 103 | /**\r |
| 104 | The constructor function caches the PCI Express Base Address and creates a \r |
| 105 | Set Virtual Address Map event to convert physical address to virtual addresses.\r |
| 106 | \r |
| 107 | @param ImageHandle The firmware allocated handle for the EFI image.\r |
| 108 | @param SystemTable A pointer to the EFI System Table.\r |
| 109 | \r |
| 110 | @retval EFI_SUCCESS The constructor completed successfully.\r |
| 111 | @retval Other value The constructor did not complete successfully.\r |
| 112 | \r |
| 113 | **/\r |
| 114 | EFI_STATUS\r |
| 115 | EFIAPI\r |
| 116 | DxeRuntimePciExpressLibConstructor (\r |
| 117 | VOID\r |
| 118 | )\r |
| 119 | {\r |
| 120 | EFI_STATUS Status;\r |
| 121 | \r |
| 122 | //\r |
| 123 | // Cache the physical address of the PCI Express MMIO range into a module global variable\r |
| 124 | //\r |
| 125 | mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r |
| 126 | \r |
| 127 | //\r |
| 128 | // Register SetVirtualAddressMap () notify function\r |
| 129 | //\r |
| 130 | Status = gBS->CreateEvent (\r |
| 131 | EVT_SIGNAL_VIRTUAL_ADDRESS_CHANGE,\r |
| 132 | TPL_NOTIFY,\r |
| 133 | DxeRuntimePciExpressLibVirtualNotify,\r |
| 134 | NULL,\r |
| 135 | &mDxeRuntimePciExpressLibVirtualNotifyEvent\r |
| 136 | );\r |
| 137 | ASSERT_EFI_ERROR (Status);\r |
| 138 | \r |
| 139 | return Status;\r |
| 140 | }\r |
| 141 | \r |
| 142 | /**\r |
| 143 | The destructor function frees any allocated buffers and closes the Set Virtual \r |
| 144 | Address Map event.\r |
| 145 | \r |
| 146 | @param ImageHandle The firmware allocated handle for the EFI image.\r |
| 147 | @param SystemTable A pointer to the EFI System Table.\r |
| 148 | \r |
| 149 | @retval EFI_SUCCESS The destructor completed successfully.\r |
| 150 | @retval Other value The destructor did not complete successfully.\r |
| 151 | \r |
| 152 | **/\r |
| 153 | EFI_STATUS\r |
| 154 | EFIAPI\r |
| 155 | DxeRuntimePciExpressLibDestructor (\r |
| 156 | VOID\r |
| 157 | )\r |
| 158 | {\r |
| 159 | EFI_STATUS Status;\r |
| 160 | \r |
| 161 | //\r |
| 162 | // If one or more PCI devices have been registered for runtime access, then \r |
| 163 | // free the registration table.\r |
| 164 | //\r |
| 165 | if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {\r |
| 166 | FreePool (mDxeRuntimePciExpressLibRegistrationTable);\r |
| 167 | }\r |
| 168 | \r |
| 169 | //\r |
| 170 | // Close the Set Virtual Address Map event\r |
| 171 | //\r |
| 172 | Status = gBS->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent);\r |
| 173 | ASSERT_EFI_ERROR (Status);\r |
| 174 | \r |
| 175 | return Status;\r |
| 176 | }\r |
| 177 | \r |
| 178 | /**\r |
| 179 | Gets the base address of PCI Express.\r |
| 180 | \r |
| 181 | This internal functions retrieves PCI Express Base Address via a PCD entry\r |
| 182 | PcdPciExpressBaseAddress.\r |
| 183 | \r |
| 184 | @return The base address of PCI Express.\r |
| 185 | \r |
| 186 | **/\r |
| 187 | UINTN\r |
| 188 | GetPciExpressAddress (\r |
| 189 | IN UINTN Address\r |
| 190 | )\r |
| 191 | {\r |
| 192 | UINTN Index;\r |
| 193 | \r |
| 194 | //\r |
| 195 | // Make sure Address is valid\r |
| 196 | //\r |
| 197 | ASSERT (((Address) & ~0xfffffff) == 0);\r |
| 198 | \r |
| 199 | //\r |
| 200 | // Convert Address to a physical address in the MMIO PCI Express range\r |
| 201 | //\r |
| 202 | Address += mDxeRuntimePciExpressLibPciExpressBaseAddress;\r |
| 203 | \r |
| 204 | //\r |
| 205 | // If SetVirtualAddressMap() has not been called, then just return the physical address\r |
| 206 | //\r |
| 207 | if (!EfiGoneVirtual ()) {\r |
| 208 | return Address;\r |
| 209 | }\r |
| 210 | \r |
| 211 | //\r |
| 212 | // See if there is a physical address match at the exact same index as the last address match\r |
| 213 | //\r |
| 214 | if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & 0x0ffff000)) {\r |
| 215 | //\r |
| 216 | // Convert the physical address to a virtual address and return the virtual address\r |
| 217 | //\r |
| 218 | return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].VirtualAddress;\r |
| 219 | }\r |
| 220 | \r |
| 221 | //\r |
| 222 | // Search the entire table for a phyical address match\r |
| 223 | //\r |
| 224 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r |
| 225 | if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & 0x0ffff000)) {\r |
| 226 | //\r |
| 227 | // Cache the matching index value\r |
| 228 | //\r |
| 229 | mDxeRuntimePciExpressLibLastRuntimeRange = Index;\r |
| 230 | //\r |
| 231 | // Convert the physical address to a virtual address and return the virtual address\r |
| 232 | //\r |
| 233 | return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress;\r |
| 234 | }\r |
| 235 | }\r |
| 236 | \r |
| 237 | //\r |
| 238 | // No match was found. This is a critical error at OS runtime, so ASSERT() and force a breakpoint.\r |
| 239 | //\r |
| 240 | ASSERT (FALSE);\r |
| 241 | CpuBreakpoint();\r |
| 242 | \r |
| 243 | //\r |
| 244 | // Return the physical address \r |
| 245 | //\r |
| 246 | return Address;\r |
| 247 | }\r |
| 248 | \r |
| 249 | /**\r |
| 250 | Register a PCI device so PCI configuration registers may be accessed after \r |
| 251 | SetVirtualAddressMap().\r |
| 252 | \r |
| 253 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 254 | \r |
| 255 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 256 | Register.\r |
| 257 | \r |
| 258 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 259 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 260 | after ExitBootServices().\r |
| 261 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 262 | at runtime could not be mapped.\r |
| 263 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 264 | complete the registration.\r |
| 265 | \r |
| 266 | **/\r |
| 267 | RETURN_STATUS\r |
| 268 | EFIAPI\r |
| 269 | PciExpressRegisterForRuntimeAccess (\r |
| 270 | IN UINTN Address\r |
| 271 | )\r |
| 272 | {\r |
| 273 | EFI_STATUS Status;\r |
| 274 | EFI_GCD_MEMORY_SPACE_DESCRIPTOR Descriptor;\r |
| 275 | UINTN Index;\r |
| 276 | VOID *NewTable;\r |
| 277 | \r |
| 278 | //\r |
| 279 | // Return an error if this function is called after ExitBootServices().\r |
| 280 | //\r |
| 281 | if (EfiAtRuntime ()) {\r |
| 282 | return RETURN_UNSUPPORTED;\r |
| 283 | }\r |
| 284 | \r |
| 285 | //\r |
| 286 | // Make sure Address is valid\r |
| 287 | //\r |
| 288 | ASSERT (((Address) & ~0xfffffff) == 0);\r |
| 289 | \r |
| 290 | //\r |
| 291 | // Convert Address to a physical address in the MMIO PCI Express range\r |
| 292 | // at the beginning of the PCI Configuration header for the specified\r |
| 293 | // PCI Bus/Dev/Func\r |
| 294 | //\r |
| 295 | Address = GetPciExpressAddress (Address & 0x0ffff000);\r |
| 296 | \r |
| 297 | //\r |
| 298 | // See if Address has already been registerd for runtime access\r |
| 299 | //\r |
| 300 | for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r |
| 301 | if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {\r |
| 302 | return RETURN_SUCCESS;\r |
| 303 | }\r |
| 304 | }\r |
| 305 | \r |
| 306 | //\r |
| 307 | // Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address\r |
| 308 | //\r |
| 309 | Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);\r |
| 310 | if (EFI_ERROR (Status)) {\r |
| 311 | return RETURN_UNSUPPORTED;\r |
| 312 | }\r |
| 313 | \r |
| 314 | //\r |
| 315 | // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS\r |
| 316 | // will allocate a virtual address range for the 4KB PCI Configuration Header.\r |
| 317 | //\r |
| 318 | Status = gDS->SetMemorySpaceAttributes (Address, 0x1000, Descriptor.Attributes | EFI_MEMORY_RUNTIME);\r |
| 319 | if (EFI_ERROR (Status)) {\r |
| 320 | return RETURN_UNSUPPORTED;\r |
| 321 | }\r |
| 322 | \r |
| 323 | //\r |
| 324 | // Grow the size of the registration table\r |
| 325 | //\r |
| 326 | NewTable = ReallocateRuntimePool (\r |
| 327 | (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r |
| 328 | (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r |
| 329 | mDxeRuntimePciExpressLibRegistrationTable\r |
| 330 | );\r |
| 331 | if (NewTable == NULL) {\r |
| 332 | return RETURN_OUT_OF_RESOURCES;\r |
| 333 | }\r |
| 334 | mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r |
| 335 | mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r |
| 336 | mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress = Address;\r |
| 337 | mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;\r |
| 338 | \r |
| 339 | return RETURN_SUCCESS;\r |
| 340 | }\r |
| 341 | \r |
| 342 | \r |
| 343 | /**\r |
| 344 | Reads an 8-bit PCI configuration register.\r |
| 345 | \r |
| 346 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 347 | This function must guarantee that all PCI read and write operations are\r |
| 348 | serialized.\r |
| 349 | \r |
| 350 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 351 | \r |
| 352 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 353 | Register.\r |
| 354 | \r |
| 355 | @return The read value from the PCI configuration register.\r |
| 356 | \r |
| 357 | **/\r |
| 358 | UINT8\r |
| 359 | EFIAPI\r |
| 360 | PciExpressRead8 (\r |
| 361 | IN UINTN Address\r |
| 362 | )\r |
| 363 | {\r |
| 364 | return MmioRead8 (GetPciExpressAddress (Address));\r |
| 365 | }\r |
| 366 | \r |
| 367 | /**\r |
| 368 | Writes an 8-bit PCI configuration register.\r |
| 369 | \r |
| 370 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 371 | value specified by Value. Value is returned. This function must guarantee\r |
| 372 | that all PCI read and write operations are serialized.\r |
| 373 | \r |
| 374 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 375 | \r |
| 376 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 377 | Register.\r |
| 378 | @param Value The value to write.\r |
| 379 | \r |
| 380 | @return The value written to the PCI configuration register.\r |
| 381 | \r |
| 382 | **/\r |
| 383 | UINT8\r |
| 384 | EFIAPI\r |
| 385 | PciExpressWrite8 (\r |
| 386 | IN UINTN Address,\r |
| 387 | IN UINT8 Value\r |
| 388 | )\r |
| 389 | {\r |
| 390 | return MmioWrite8 (GetPciExpressAddress (Address), Value);\r |
| 391 | }\r |
| 392 | \r |
| 393 | /**\r |
| 394 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r |
| 395 | an 8-bit value.\r |
| 396 | \r |
| 397 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 398 | bitwise inclusive OR between the read result and the value specified by\r |
| 399 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 400 | specified by Address. The value written to the PCI configuration register is\r |
| 401 | returned. This function must guarantee that all PCI read and write operations\r |
| 402 | are serialized.\r |
| 403 | \r |
| 404 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 405 | \r |
| 406 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 407 | Register.\r |
| 408 | @param OrData The value to OR with the PCI configuration register.\r |
| 409 | \r |
| 410 | @return The value written back to the PCI configuration register.\r |
| 411 | \r |
| 412 | **/\r |
| 413 | UINT8\r |
| 414 | EFIAPI\r |
| 415 | PciExpressOr8 (\r |
| 416 | IN UINTN Address,\r |
| 417 | IN UINT8 OrData\r |
| 418 | )\r |
| 419 | {\r |
| 420 | return MmioOr8 (GetPciExpressAddress (Address), OrData);\r |
| 421 | }\r |
| 422 | \r |
| 423 | /**\r |
| 424 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 425 | value.\r |
| 426 | \r |
| 427 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 428 | bitwise AND between the read result and the value specified by AndData, and\r |
| 429 | writes the result to the 8-bit PCI configuration register specified by\r |
| 430 | Address. The value written to the PCI configuration register is returned.\r |
| 431 | This function must guarantee that all PCI read and write operations are\r |
| 432 | serialized.\r |
| 433 | \r |
| 434 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 435 | \r |
| 436 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 437 | Register.\r |
| 438 | @param AndData The value to AND with the PCI configuration register.\r |
| 439 | \r |
| 440 | @return The value written back to the PCI configuration register.\r |
| 441 | \r |
| 442 | **/\r |
| 443 | UINT8\r |
| 444 | EFIAPI\r |
| 445 | PciExpressAnd8 (\r |
| 446 | IN UINTN Address,\r |
| 447 | IN UINT8 AndData\r |
| 448 | )\r |
| 449 | {\r |
| 450 | return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r |
| 451 | }\r |
| 452 | \r |
| 453 | /**\r |
| 454 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 455 | value, followed a bitwise inclusive OR with another 8-bit value.\r |
| 456 | \r |
| 457 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 458 | bitwise AND between the read result and the value specified by AndData,\r |
| 459 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 460 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 461 | configuration register specified by Address. The value written to the PCI\r |
| 462 | configuration register is returned. This function must guarantee that all PCI\r |
| 463 | read and write operations are serialized.\r |
| 464 | \r |
| 465 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 466 | \r |
| 467 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 468 | Register.\r |
| 469 | @param AndData The value to AND with the PCI configuration register.\r |
| 470 | @param OrData The value to OR with the result of the AND operation.\r |
| 471 | \r |
| 472 | @return The value written back to the PCI configuration register.\r |
| 473 | \r |
| 474 | **/\r |
| 475 | UINT8\r |
| 476 | EFIAPI\r |
| 477 | PciExpressAndThenOr8 (\r |
| 478 | IN UINTN Address,\r |
| 479 | IN UINT8 AndData,\r |
| 480 | IN UINT8 OrData\r |
| 481 | )\r |
| 482 | {\r |
| 483 | return MmioAndThenOr8 (\r |
| 484 | GetPciExpressAddress (Address),\r |
| 485 | AndData,\r |
| 486 | OrData\r |
| 487 | );\r |
| 488 | }\r |
| 489 | \r |
| 490 | /**\r |
| 491 | Reads a bit field of a PCI configuration register.\r |
| 492 | \r |
| 493 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 494 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 495 | returned.\r |
| 496 | \r |
| 497 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 498 | If StartBit is greater than 7, then ASSERT().\r |
| 499 | If EndBit is greater than 7, then ASSERT().\r |
| 500 | If EndBit is less than StartBit, then ASSERT().\r |
| 501 | \r |
| 502 | @param Address PCI configuration register to read.\r |
| 503 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 504 | Range 0..7.\r |
| 505 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 506 | Range 0..7.\r |
| 507 | \r |
| 508 | @return The value of the bit field read from the PCI configuration register.\r |
| 509 | \r |
| 510 | **/\r |
| 511 | UINT8\r |
| 512 | EFIAPI\r |
| 513 | PciExpressBitFieldRead8 (\r |
| 514 | IN UINTN Address,\r |
| 515 | IN UINTN StartBit,\r |
| 516 | IN UINTN EndBit\r |
| 517 | )\r |
| 518 | {\r |
| 519 | return MmioBitFieldRead8 (\r |
| 520 | GetPciExpressAddress (Address),\r |
| 521 | StartBit,\r |
| 522 | EndBit\r |
| 523 | );\r |
| 524 | }\r |
| 525 | \r |
| 526 | /**\r |
| 527 | Writes a bit field to a PCI configuration register.\r |
| 528 | \r |
| 529 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 530 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 531 | destination PCI configuration register are preserved. The new value of the\r |
| 532 | 8-bit register is returned.\r |
| 533 | \r |
| 534 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 535 | If StartBit is greater than 7, then ASSERT().\r |
| 536 | If EndBit is greater than 7, then ASSERT().\r |
| 537 | If EndBit is less than StartBit, then ASSERT().\r |
| 538 | \r |
| 539 | @param Address PCI configuration register to write.\r |
| 540 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 541 | Range 0..7.\r |
| 542 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 543 | Range 0..7.\r |
| 544 | @param Value New value of the bit field.\r |
| 545 | \r |
| 546 | @return The value written back to the PCI configuration register.\r |
| 547 | \r |
| 548 | **/\r |
| 549 | UINT8\r |
| 550 | EFIAPI\r |
| 551 | PciExpressBitFieldWrite8 (\r |
| 552 | IN UINTN Address,\r |
| 553 | IN UINTN StartBit,\r |
| 554 | IN UINTN EndBit,\r |
| 555 | IN UINT8 Value\r |
| 556 | )\r |
| 557 | {\r |
| 558 | return MmioBitFieldWrite8 (\r |
| 559 | GetPciExpressAddress (Address),\r |
| 560 | StartBit,\r |
| 561 | EndBit,\r |
| 562 | Value\r |
| 563 | );\r |
| 564 | }\r |
| 565 | \r |
| 566 | /**\r |
| 567 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 568 | writes the result back to the bit field in the 8-bit port.\r |
| 569 | \r |
| 570 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 571 | bitwise inclusive OR between the read result and the value specified by\r |
| 572 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 573 | specified by Address. The value written to the PCI configuration register is\r |
| 574 | returned. This function must guarantee that all PCI read and write operations\r |
| 575 | are serialized. Extra left bits in OrData are stripped.\r |
| 576 | \r |
| 577 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 578 | If StartBit is greater than 7, then ASSERT().\r |
| 579 | If EndBit is greater than 7, then ASSERT().\r |
| 580 | If EndBit is less than StartBit, then ASSERT().\r |
| 581 | \r |
| 582 | @param Address PCI configuration register to write.\r |
| 583 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 584 | Range 0..7.\r |
| 585 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 586 | Range 0..7.\r |
| 587 | @param OrData The value to OR with the PCI configuration register.\r |
| 588 | \r |
| 589 | @return The value written back to the PCI configuration register.\r |
| 590 | \r |
| 591 | **/\r |
| 592 | UINT8\r |
| 593 | EFIAPI\r |
| 594 | PciExpressBitFieldOr8 (\r |
| 595 | IN UINTN Address,\r |
| 596 | IN UINTN StartBit,\r |
| 597 | IN UINTN EndBit,\r |
| 598 | IN UINT8 OrData\r |
| 599 | )\r |
| 600 | {\r |
| 601 | return MmioBitFieldOr8 (\r |
| 602 | GetPciExpressAddress (Address),\r |
| 603 | StartBit,\r |
| 604 | EndBit,\r |
| 605 | OrData\r |
| 606 | );\r |
| 607 | }\r |
| 608 | \r |
| 609 | /**\r |
| 610 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 611 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 612 | \r |
| 613 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 614 | bitwise AND between the read result and the value specified by AndData, and\r |
| 615 | writes the result to the 8-bit PCI configuration register specified by\r |
| 616 | Address. The value written to the PCI configuration register is returned.\r |
| 617 | This function must guarantee that all PCI read and write operations are\r |
| 618 | serialized. Extra left bits in AndData are stripped.\r |
| 619 | \r |
| 620 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 621 | If StartBit is greater than 7, then ASSERT().\r |
| 622 | If EndBit is greater than 7, then ASSERT().\r |
| 623 | If EndBit is less than StartBit, then ASSERT().\r |
| 624 | \r |
| 625 | @param Address PCI configuration register to write.\r |
| 626 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 627 | Range 0..7.\r |
| 628 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 629 | Range 0..7.\r |
| 630 | @param AndData The value to AND with the PCI configuration register.\r |
| 631 | \r |
| 632 | @return The value written back to the PCI configuration register.\r |
| 633 | \r |
| 634 | **/\r |
| 635 | UINT8\r |
| 636 | EFIAPI\r |
| 637 | PciExpressBitFieldAnd8 (\r |
| 638 | IN UINTN Address,\r |
| 639 | IN UINTN StartBit,\r |
| 640 | IN UINTN EndBit,\r |
| 641 | IN UINT8 AndData\r |
| 642 | )\r |
| 643 | {\r |
| 644 | return MmioBitFieldAnd8 (\r |
| 645 | GetPciExpressAddress (Address),\r |
| 646 | StartBit,\r |
| 647 | EndBit,\r |
| 648 | AndData\r |
| 649 | );\r |
| 650 | }\r |
| 651 | \r |
| 652 | /**\r |
| 653 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 654 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 655 | 8-bit port.\r |
| 656 | \r |
| 657 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 658 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 659 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 660 | configuration register specified by Address. The value written to the PCI\r |
| 661 | configuration register is returned. This function must guarantee that all PCI\r |
| 662 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 663 | OrData are stripped.\r |
| 664 | \r |
| 665 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 666 | If StartBit is greater than 7, then ASSERT().\r |
| 667 | If EndBit is greater than 7, then ASSERT().\r |
| 668 | If EndBit is less than StartBit, then ASSERT().\r |
| 669 | \r |
| 670 | @param Address PCI configuration register to write.\r |
| 671 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 672 | Range 0..7.\r |
| 673 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 674 | Range 0..7.\r |
| 675 | @param AndData The value to AND with the PCI configuration register.\r |
| 676 | @param OrData The value to OR with the result of the AND operation.\r |
| 677 | \r |
| 678 | @return The value written back to the PCI configuration register.\r |
| 679 | \r |
| 680 | **/\r |
| 681 | UINT8\r |
| 682 | EFIAPI\r |
| 683 | PciExpressBitFieldAndThenOr8 (\r |
| 684 | IN UINTN Address,\r |
| 685 | IN UINTN StartBit,\r |
| 686 | IN UINTN EndBit,\r |
| 687 | IN UINT8 AndData,\r |
| 688 | IN UINT8 OrData\r |
| 689 | )\r |
| 690 | {\r |
| 691 | return MmioBitFieldAndThenOr8 (\r |
| 692 | GetPciExpressAddress (Address),\r |
| 693 | StartBit,\r |
| 694 | EndBit,\r |
| 695 | AndData,\r |
| 696 | OrData\r |
| 697 | );\r |
| 698 | }\r |
| 699 | \r |
| 700 | /**\r |
| 701 | Reads a 16-bit PCI configuration register.\r |
| 702 | \r |
| 703 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 704 | This function must guarantee that all PCI read and write operations are\r |
| 705 | serialized.\r |
| 706 | \r |
| 707 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 708 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 709 | \r |
| 710 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 711 | Register.\r |
| 712 | \r |
| 713 | @return The read value from the PCI configuration register.\r |
| 714 | \r |
| 715 | **/\r |
| 716 | UINT16\r |
| 717 | EFIAPI\r |
| 718 | PciExpressRead16 (\r |
| 719 | IN UINTN Address\r |
| 720 | )\r |
| 721 | {\r |
| 722 | return MmioRead16 (GetPciExpressAddress (Address));\r |
| 723 | }\r |
| 724 | \r |
| 725 | /**\r |
| 726 | Writes a 16-bit PCI configuration register.\r |
| 727 | \r |
| 728 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 729 | value specified by Value. Value is returned. This function must guarantee\r |
| 730 | that all PCI read and write operations are serialized.\r |
| 731 | \r |
| 732 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 733 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 734 | \r |
| 735 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 736 | Register.\r |
| 737 | @param Value The value to write.\r |
| 738 | \r |
| 739 | @return The value written to the PCI configuration register.\r |
| 740 | \r |
| 741 | **/\r |
| 742 | UINT16\r |
| 743 | EFIAPI\r |
| 744 | PciExpressWrite16 (\r |
| 745 | IN UINTN Address,\r |
| 746 | IN UINT16 Value\r |
| 747 | )\r |
| 748 | {\r |
| 749 | return MmioWrite16 (GetPciExpressAddress (Address), Value);\r |
| 750 | }\r |
| 751 | \r |
| 752 | /**\r |
| 753 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r |
| 754 | a 16-bit value.\r |
| 755 | \r |
| 756 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 757 | bitwise inclusive OR between the read result and the value specified by\r |
| 758 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 759 | specified by Address. The value written to the PCI configuration register is\r |
| 760 | returned. This function must guarantee that all PCI read and write operations\r |
| 761 | are serialized.\r |
| 762 | \r |
| 763 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 764 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 765 | \r |
| 766 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 767 | Register.\r |
| 768 | @param OrData The value to OR with the PCI configuration register.\r |
| 769 | \r |
| 770 | @return The value written back to the PCI configuration register.\r |
| 771 | \r |
| 772 | **/\r |
| 773 | UINT16\r |
| 774 | EFIAPI\r |
| 775 | PciExpressOr16 (\r |
| 776 | IN UINTN Address,\r |
| 777 | IN UINT16 OrData\r |
| 778 | )\r |
| 779 | {\r |
| 780 | return MmioOr16 (GetPciExpressAddress (Address), OrData);\r |
| 781 | }\r |
| 782 | \r |
| 783 | /**\r |
| 784 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 785 | value.\r |
| 786 | \r |
| 787 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 788 | bitwise AND between the read result and the value specified by AndData, and\r |
| 789 | writes the result to the 16-bit PCI configuration register specified by\r |
| 790 | Address. The value written to the PCI configuration register is returned.\r |
| 791 | This function must guarantee that all PCI read and write operations are\r |
| 792 | serialized.\r |
| 793 | \r |
| 794 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 795 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 796 | \r |
| 797 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 798 | Register.\r |
| 799 | @param AndData The value to AND with the PCI configuration register.\r |
| 800 | \r |
| 801 | @return The value written back to the PCI configuration register.\r |
| 802 | \r |
| 803 | **/\r |
| 804 | UINT16\r |
| 805 | EFIAPI\r |
| 806 | PciExpressAnd16 (\r |
| 807 | IN UINTN Address,\r |
| 808 | IN UINT16 AndData\r |
| 809 | )\r |
| 810 | {\r |
| 811 | return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r |
| 812 | }\r |
| 813 | \r |
| 814 | /**\r |
| 815 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 816 | value, followed a bitwise inclusive OR with another 16-bit value.\r |
| 817 | \r |
| 818 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 819 | bitwise AND between the read result and the value specified by AndData,\r |
| 820 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 821 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 822 | configuration register specified by Address. The value written to the PCI\r |
| 823 | configuration register is returned. This function must guarantee that all PCI\r |
| 824 | read and write operations are serialized.\r |
| 825 | \r |
| 826 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 827 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 828 | \r |
| 829 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 830 | Register.\r |
| 831 | @param AndData The value to AND with the PCI configuration register.\r |
| 832 | @param OrData The value to OR with the result of the AND operation.\r |
| 833 | \r |
| 834 | @return The value written back to the PCI configuration register.\r |
| 835 | \r |
| 836 | **/\r |
| 837 | UINT16\r |
| 838 | EFIAPI\r |
| 839 | PciExpressAndThenOr16 (\r |
| 840 | IN UINTN Address,\r |
| 841 | IN UINT16 AndData,\r |
| 842 | IN UINT16 OrData\r |
| 843 | )\r |
| 844 | {\r |
| 845 | return MmioAndThenOr16 (\r |
| 846 | GetPciExpressAddress (Address),\r |
| 847 | AndData,\r |
| 848 | OrData\r |
| 849 | );\r |
| 850 | }\r |
| 851 | \r |
| 852 | /**\r |
| 853 | Reads a bit field of a PCI configuration register.\r |
| 854 | \r |
| 855 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 856 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 857 | returned.\r |
| 858 | \r |
| 859 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 860 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 861 | If StartBit is greater than 15, then ASSERT().\r |
| 862 | If EndBit is greater than 15, then ASSERT().\r |
| 863 | If EndBit is less than StartBit, then ASSERT().\r |
| 864 | \r |
| 865 | @param Address PCI configuration register to read.\r |
| 866 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 867 | Range 0..15.\r |
| 868 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 869 | Range 0..15.\r |
| 870 | \r |
| 871 | @return The value of the bit field read from the PCI configuration register.\r |
| 872 | \r |
| 873 | **/\r |
| 874 | UINT16\r |
| 875 | EFIAPI\r |
| 876 | PciExpressBitFieldRead16 (\r |
| 877 | IN UINTN Address,\r |
| 878 | IN UINTN StartBit,\r |
| 879 | IN UINTN EndBit\r |
| 880 | )\r |
| 881 | {\r |
| 882 | return MmioBitFieldRead16 (\r |
| 883 | GetPciExpressAddress (Address),\r |
| 884 | StartBit,\r |
| 885 | EndBit\r |
| 886 | );\r |
| 887 | }\r |
| 888 | \r |
| 889 | /**\r |
| 890 | Writes a bit field to a PCI configuration register.\r |
| 891 | \r |
| 892 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 893 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 894 | destination PCI configuration register are preserved. The new value of the\r |
| 895 | 16-bit register is returned.\r |
| 896 | \r |
| 897 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 898 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 899 | If StartBit is greater than 15, then ASSERT().\r |
| 900 | If EndBit is greater than 15, then ASSERT().\r |
| 901 | If EndBit is less than StartBit, then ASSERT().\r |
| 902 | \r |
| 903 | @param Address PCI configuration register to write.\r |
| 904 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 905 | Range 0..15.\r |
| 906 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 907 | Range 0..15.\r |
| 908 | @param Value New value of the bit field.\r |
| 909 | \r |
| 910 | @return The value written back to the PCI configuration register.\r |
| 911 | \r |
| 912 | **/\r |
| 913 | UINT16\r |
| 914 | EFIAPI\r |
| 915 | PciExpressBitFieldWrite16 (\r |
| 916 | IN UINTN Address,\r |
| 917 | IN UINTN StartBit,\r |
| 918 | IN UINTN EndBit,\r |
| 919 | IN UINT16 Value\r |
| 920 | )\r |
| 921 | {\r |
| 922 | return MmioBitFieldWrite16 (\r |
| 923 | GetPciExpressAddress (Address),\r |
| 924 | StartBit,\r |
| 925 | EndBit,\r |
| 926 | Value\r |
| 927 | );\r |
| 928 | }\r |
| 929 | \r |
| 930 | /**\r |
| 931 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 932 | writes the result back to the bit field in the 16-bit port.\r |
| 933 | \r |
| 934 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 935 | bitwise inclusive OR between the read result and the value specified by\r |
| 936 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 937 | specified by Address. The value written to the PCI configuration register is\r |
| 938 | returned. This function must guarantee that all PCI read and write operations\r |
| 939 | are serialized. Extra left bits in OrData are stripped.\r |
| 940 | \r |
| 941 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 942 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 943 | If StartBit is greater than 15, then ASSERT().\r |
| 944 | If EndBit is greater than 15, then ASSERT().\r |
| 945 | If EndBit is less than StartBit, then ASSERT().\r |
| 946 | \r |
| 947 | @param Address PCI configuration register to write.\r |
| 948 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 949 | Range 0..15.\r |
| 950 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 951 | Range 0..15.\r |
| 952 | @param OrData The value to OR with the PCI configuration register.\r |
| 953 | \r |
| 954 | @return The value written back to the PCI configuration register.\r |
| 955 | \r |
| 956 | **/\r |
| 957 | UINT16\r |
| 958 | EFIAPI\r |
| 959 | PciExpressBitFieldOr16 (\r |
| 960 | IN UINTN Address,\r |
| 961 | IN UINTN StartBit,\r |
| 962 | IN UINTN EndBit,\r |
| 963 | IN UINT16 OrData\r |
| 964 | )\r |
| 965 | {\r |
| 966 | return MmioBitFieldOr16 (\r |
| 967 | GetPciExpressAddress (Address),\r |
| 968 | StartBit,\r |
| 969 | EndBit,\r |
| 970 | OrData\r |
| 971 | );\r |
| 972 | }\r |
| 973 | \r |
| 974 | /**\r |
| 975 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 976 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 977 | \r |
| 978 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 979 | bitwise AND between the read result and the value specified by AndData, and\r |
| 980 | writes the result to the 16-bit PCI configuration register specified by\r |
| 981 | Address. The value written to the PCI configuration register is returned.\r |
| 982 | This function must guarantee that all PCI read and write operations are\r |
| 983 | serialized. Extra left bits in AndData are stripped.\r |
| 984 | \r |
| 985 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 986 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 987 | If StartBit is greater than 15, then ASSERT().\r |
| 988 | If EndBit is greater than 15, then ASSERT().\r |
| 989 | If EndBit is less than StartBit, then ASSERT().\r |
| 990 | \r |
| 991 | @param Address PCI configuration register to write.\r |
| 992 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 993 | Range 0..15.\r |
| 994 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 995 | Range 0..15.\r |
| 996 | @param AndData The value to AND with the PCI configuration register.\r |
| 997 | \r |
| 998 | @return The value written back to the PCI configuration register.\r |
| 999 | \r |
| 1000 | **/\r |
| 1001 | UINT16\r |
| 1002 | EFIAPI\r |
| 1003 | PciExpressBitFieldAnd16 (\r |
| 1004 | IN UINTN Address,\r |
| 1005 | IN UINTN StartBit,\r |
| 1006 | IN UINTN EndBit,\r |
| 1007 | IN UINT16 AndData\r |
| 1008 | )\r |
| 1009 | {\r |
| 1010 | return MmioBitFieldAnd16 (\r |
| 1011 | GetPciExpressAddress (Address),\r |
| 1012 | StartBit,\r |
| 1013 | EndBit,\r |
| 1014 | AndData\r |
| 1015 | );\r |
| 1016 | }\r |
| 1017 | \r |
| 1018 | /**\r |
| 1019 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 1020 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 1021 | 16-bit port.\r |
| 1022 | \r |
| 1023 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 1024 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 1025 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 1026 | configuration register specified by Address. The value written to the PCI\r |
| 1027 | configuration register is returned. This function must guarantee that all PCI\r |
| 1028 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1029 | OrData are stripped.\r |
| 1030 | \r |
| 1031 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1032 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 1033 | If StartBit is greater than 15, then ASSERT().\r |
| 1034 | If EndBit is greater than 15, then ASSERT().\r |
| 1035 | If EndBit is less than StartBit, then ASSERT().\r |
| 1036 | \r |
| 1037 | @param Address PCI configuration register to write.\r |
| 1038 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1039 | Range 0..15.\r |
| 1040 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1041 | Range 0..15.\r |
| 1042 | @param AndData The value to AND with the PCI configuration register.\r |
| 1043 | @param OrData The value to OR with the result of the AND operation.\r |
| 1044 | \r |
| 1045 | @return The value written back to the PCI configuration register.\r |
| 1046 | \r |
| 1047 | **/\r |
| 1048 | UINT16\r |
| 1049 | EFIAPI\r |
| 1050 | PciExpressBitFieldAndThenOr16 (\r |
| 1051 | IN UINTN Address,\r |
| 1052 | IN UINTN StartBit,\r |
| 1053 | IN UINTN EndBit,\r |
| 1054 | IN UINT16 AndData,\r |
| 1055 | IN UINT16 OrData\r |
| 1056 | )\r |
| 1057 | {\r |
| 1058 | return MmioBitFieldAndThenOr16 (\r |
| 1059 | GetPciExpressAddress (Address),\r |
| 1060 | StartBit,\r |
| 1061 | EndBit,\r |
| 1062 | AndData,\r |
| 1063 | OrData\r |
| 1064 | );\r |
| 1065 | }\r |
| 1066 | \r |
| 1067 | /**\r |
| 1068 | Reads a 32-bit PCI configuration register.\r |
| 1069 | \r |
| 1070 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 1071 | This function must guarantee that all PCI read and write operations are\r |
| 1072 | serialized.\r |
| 1073 | \r |
| 1074 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1075 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1076 | \r |
| 1077 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1078 | Register.\r |
| 1079 | \r |
| 1080 | @return The read value from the PCI configuration register.\r |
| 1081 | \r |
| 1082 | **/\r |
| 1083 | UINT32\r |
| 1084 | EFIAPI\r |
| 1085 | PciExpressRead32 (\r |
| 1086 | IN UINTN Address\r |
| 1087 | )\r |
| 1088 | {\r |
| 1089 | return MmioRead32 (GetPciExpressAddress (Address));\r |
| 1090 | }\r |
| 1091 | \r |
| 1092 | /**\r |
| 1093 | Writes a 32-bit PCI configuration register.\r |
| 1094 | \r |
| 1095 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 1096 | value specified by Value. Value is returned. This function must guarantee\r |
| 1097 | that all PCI read and write operations are serialized.\r |
| 1098 | \r |
| 1099 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1100 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1101 | \r |
| 1102 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1103 | Register.\r |
| 1104 | @param Value The value to write.\r |
| 1105 | \r |
| 1106 | @return The value written to the PCI configuration register.\r |
| 1107 | \r |
| 1108 | **/\r |
| 1109 | UINT32\r |
| 1110 | EFIAPI\r |
| 1111 | PciExpressWrite32 (\r |
| 1112 | IN UINTN Address,\r |
| 1113 | IN UINT32 Value\r |
| 1114 | )\r |
| 1115 | {\r |
| 1116 | return MmioWrite32 (GetPciExpressAddress (Address), Value);\r |
| 1117 | }\r |
| 1118 | \r |
| 1119 | /**\r |
| 1120 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r |
| 1121 | a 32-bit value.\r |
| 1122 | \r |
| 1123 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1124 | bitwise inclusive OR between the read result and the value specified by\r |
| 1125 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 1126 | specified by Address. The value written to the PCI configuration register is\r |
| 1127 | returned. This function must guarantee that all PCI read and write operations\r |
| 1128 | are serialized.\r |
| 1129 | \r |
| 1130 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1131 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1132 | \r |
| 1133 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1134 | Register.\r |
| 1135 | @param OrData The value to OR with the PCI configuration register.\r |
| 1136 | \r |
| 1137 | @return The value written back to the PCI configuration register.\r |
| 1138 | \r |
| 1139 | **/\r |
| 1140 | UINT32\r |
| 1141 | EFIAPI\r |
| 1142 | PciExpressOr32 (\r |
| 1143 | IN UINTN Address,\r |
| 1144 | IN UINT32 OrData\r |
| 1145 | )\r |
| 1146 | {\r |
| 1147 | return MmioOr32 (GetPciExpressAddress (Address), OrData);\r |
| 1148 | }\r |
| 1149 | \r |
| 1150 | /**\r |
| 1151 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 1152 | value.\r |
| 1153 | \r |
| 1154 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1155 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1156 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1157 | Address. The value written to the PCI configuration register is returned.\r |
| 1158 | This function must guarantee that all PCI read and write operations are\r |
| 1159 | serialized.\r |
| 1160 | \r |
| 1161 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1162 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1163 | \r |
| 1164 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1165 | Register.\r |
| 1166 | @param AndData The value to AND with the PCI configuration register.\r |
| 1167 | \r |
| 1168 | @return The value written back to the PCI configuration register.\r |
| 1169 | \r |
| 1170 | **/\r |
| 1171 | UINT32\r |
| 1172 | EFIAPI\r |
| 1173 | PciExpressAnd32 (\r |
| 1174 | IN UINTN Address,\r |
| 1175 | IN UINT32 AndData\r |
| 1176 | )\r |
| 1177 | {\r |
| 1178 | return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r |
| 1179 | }\r |
| 1180 | \r |
| 1181 | /**\r |
| 1182 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 1183 | value, followed a bitwise inclusive OR with another 32-bit value.\r |
| 1184 | \r |
| 1185 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1186 | bitwise AND between the read result and the value specified by AndData,\r |
| 1187 | performs a bitwise inclusive OR between the result of the AND operation and\r |
| 1188 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 1189 | configuration register specified by Address. The value written to the PCI\r |
| 1190 | configuration register is returned. This function must guarantee that all PCI\r |
| 1191 | read and write operations are serialized.\r |
| 1192 | \r |
| 1193 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1194 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1195 | \r |
| 1196 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 1197 | Register.\r |
| 1198 | @param AndData The value to AND with the PCI configuration register.\r |
| 1199 | @param OrData The value to OR with the result of the AND operation.\r |
| 1200 | \r |
| 1201 | @return The value written back to the PCI configuration register.\r |
| 1202 | \r |
| 1203 | **/\r |
| 1204 | UINT32\r |
| 1205 | EFIAPI\r |
| 1206 | PciExpressAndThenOr32 (\r |
| 1207 | IN UINTN Address,\r |
| 1208 | IN UINT32 AndData,\r |
| 1209 | IN UINT32 OrData\r |
| 1210 | )\r |
| 1211 | {\r |
| 1212 | return MmioAndThenOr32 (\r |
| 1213 | GetPciExpressAddress (Address),\r |
| 1214 | AndData,\r |
| 1215 | OrData\r |
| 1216 | );\r |
| 1217 | }\r |
| 1218 | \r |
| 1219 | /**\r |
| 1220 | Reads a bit field of a PCI configuration register.\r |
| 1221 | \r |
| 1222 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 1223 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 1224 | returned.\r |
| 1225 | \r |
| 1226 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1227 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1228 | If StartBit is greater than 31, then ASSERT().\r |
| 1229 | If EndBit is greater than 31, then ASSERT().\r |
| 1230 | If EndBit is less than StartBit, then ASSERT().\r |
| 1231 | \r |
| 1232 | @param Address PCI configuration register to read.\r |
| 1233 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1234 | Range 0..31.\r |
| 1235 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1236 | Range 0..31.\r |
| 1237 | \r |
| 1238 | @return The value of the bit field read from the PCI configuration register.\r |
| 1239 | \r |
| 1240 | **/\r |
| 1241 | UINT32\r |
| 1242 | EFIAPI\r |
| 1243 | PciExpressBitFieldRead32 (\r |
| 1244 | IN UINTN Address,\r |
| 1245 | IN UINTN StartBit,\r |
| 1246 | IN UINTN EndBit\r |
| 1247 | )\r |
| 1248 | {\r |
| 1249 | return MmioBitFieldRead32 (\r |
| 1250 | GetPciExpressAddress (Address),\r |
| 1251 | StartBit,\r |
| 1252 | EndBit\r |
| 1253 | );\r |
| 1254 | }\r |
| 1255 | \r |
| 1256 | /**\r |
| 1257 | Writes a bit field to a PCI configuration register.\r |
| 1258 | \r |
| 1259 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 1260 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 1261 | destination PCI configuration register are preserved. The new value of the\r |
| 1262 | 32-bit register is returned.\r |
| 1263 | \r |
| 1264 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1265 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1266 | If StartBit is greater than 31, then ASSERT().\r |
| 1267 | If EndBit is greater than 31, then ASSERT().\r |
| 1268 | If EndBit is less than StartBit, then ASSERT().\r |
| 1269 | \r |
| 1270 | @param Address PCI configuration register to write.\r |
| 1271 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1272 | Range 0..31.\r |
| 1273 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1274 | Range 0..31.\r |
| 1275 | @param Value New value of the bit field.\r |
| 1276 | \r |
| 1277 | @return The value written back to the PCI configuration register.\r |
| 1278 | \r |
| 1279 | **/\r |
| 1280 | UINT32\r |
| 1281 | EFIAPI\r |
| 1282 | PciExpressBitFieldWrite32 (\r |
| 1283 | IN UINTN Address,\r |
| 1284 | IN UINTN StartBit,\r |
| 1285 | IN UINTN EndBit,\r |
| 1286 | IN UINT32 Value\r |
| 1287 | )\r |
| 1288 | {\r |
| 1289 | return MmioBitFieldWrite32 (\r |
| 1290 | GetPciExpressAddress (Address),\r |
| 1291 | StartBit,\r |
| 1292 | EndBit,\r |
| 1293 | Value\r |
| 1294 | );\r |
| 1295 | }\r |
| 1296 | \r |
| 1297 | /**\r |
| 1298 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 1299 | writes the result back to the bit field in the 32-bit port.\r |
| 1300 | \r |
| 1301 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1302 | bitwise inclusive OR between the read result and the value specified by\r |
| 1303 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 1304 | specified by Address. The value written to the PCI configuration register is\r |
| 1305 | returned. This function must guarantee that all PCI read and write operations\r |
| 1306 | are serialized. Extra left bits in OrData are stripped.\r |
| 1307 | \r |
| 1308 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1309 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1310 | If StartBit is greater than 31, then ASSERT().\r |
| 1311 | If EndBit is greater than 31, then ASSERT().\r |
| 1312 | If EndBit is less than StartBit, then ASSERT().\r |
| 1313 | \r |
| 1314 | @param Address PCI configuration register to write.\r |
| 1315 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1316 | Range 0..31.\r |
| 1317 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1318 | Range 0..31.\r |
| 1319 | @param OrData The value to OR with the PCI configuration register.\r |
| 1320 | \r |
| 1321 | @return The value written back to the PCI configuration register.\r |
| 1322 | \r |
| 1323 | **/\r |
| 1324 | UINT32\r |
| 1325 | EFIAPI\r |
| 1326 | PciExpressBitFieldOr32 (\r |
| 1327 | IN UINTN Address,\r |
| 1328 | IN UINTN StartBit,\r |
| 1329 | IN UINTN EndBit,\r |
| 1330 | IN UINT32 OrData\r |
| 1331 | )\r |
| 1332 | {\r |
| 1333 | return MmioBitFieldOr32 (\r |
| 1334 | GetPciExpressAddress (Address),\r |
| 1335 | StartBit,\r |
| 1336 | EndBit,\r |
| 1337 | OrData\r |
| 1338 | );\r |
| 1339 | }\r |
| 1340 | \r |
| 1341 | /**\r |
| 1342 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 1343 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 1344 | \r |
| 1345 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1346 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1347 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1348 | Address. The value written to the PCI configuration register is returned.\r |
| 1349 | This function must guarantee that all PCI read and write operations are\r |
| 1350 | serialized. Extra left bits in AndData are stripped.\r |
| 1351 | \r |
| 1352 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1353 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1354 | If StartBit is greater than 31, then ASSERT().\r |
| 1355 | If EndBit is greater than 31, then ASSERT().\r |
| 1356 | If EndBit is less than StartBit, then ASSERT().\r |
| 1357 | \r |
| 1358 | @param Address PCI configuration register to write.\r |
| 1359 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1360 | Range 0..31.\r |
| 1361 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1362 | Range 0..31.\r |
| 1363 | @param AndData The value to AND with the PCI configuration register.\r |
| 1364 | \r |
| 1365 | @return The value written back to the PCI configuration register.\r |
| 1366 | \r |
| 1367 | **/\r |
| 1368 | UINT32\r |
| 1369 | EFIAPI\r |
| 1370 | PciExpressBitFieldAnd32 (\r |
| 1371 | IN UINTN Address,\r |
| 1372 | IN UINTN StartBit,\r |
| 1373 | IN UINTN EndBit,\r |
| 1374 | IN UINT32 AndData\r |
| 1375 | )\r |
| 1376 | {\r |
| 1377 | return MmioBitFieldAnd32 (\r |
| 1378 | GetPciExpressAddress (Address),\r |
| 1379 | StartBit,\r |
| 1380 | EndBit,\r |
| 1381 | AndData\r |
| 1382 | );\r |
| 1383 | }\r |
| 1384 | \r |
| 1385 | /**\r |
| 1386 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 1387 | bitwise inclusive OR, and writes the result back to the bit field in the\r |
| 1388 | 32-bit port.\r |
| 1389 | \r |
| 1390 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1391 | bitwise AND followed by a bitwise inclusive OR between the read result and\r |
| 1392 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 1393 | configuration register specified by Address. The value written to the PCI\r |
| 1394 | configuration register is returned. This function must guarantee that all PCI\r |
| 1395 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1396 | OrData are stripped.\r |
| 1397 | \r |
| 1398 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1399 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1400 | If StartBit is greater than 31, then ASSERT().\r |
| 1401 | If EndBit is greater than 31, then ASSERT().\r |
| 1402 | If EndBit is less than StartBit, then ASSERT().\r |
| 1403 | \r |
| 1404 | @param Address PCI configuration register to write.\r |
| 1405 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1406 | Range 0..31.\r |
| 1407 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1408 | Range 0..31.\r |
| 1409 | @param AndData The value to AND with the PCI configuration register.\r |
| 1410 | @param OrData The value to OR with the result of the AND operation.\r |
| 1411 | \r |
| 1412 | @return The value written back to the PCI configuration register.\r |
| 1413 | \r |
| 1414 | **/\r |
| 1415 | UINT32\r |
| 1416 | EFIAPI\r |
| 1417 | PciExpressBitFieldAndThenOr32 (\r |
| 1418 | IN UINTN Address,\r |
| 1419 | IN UINTN StartBit,\r |
| 1420 | IN UINTN EndBit,\r |
| 1421 | IN UINT32 AndData,\r |
| 1422 | IN UINT32 OrData\r |
| 1423 | )\r |
| 1424 | {\r |
| 1425 | return MmioBitFieldAndThenOr32 (\r |
| 1426 | GetPciExpressAddress (Address),\r |
| 1427 | StartBit,\r |
| 1428 | EndBit,\r |
| 1429 | AndData,\r |
| 1430 | OrData\r |
| 1431 | );\r |
| 1432 | }\r |
| 1433 | \r |
| 1434 | /**\r |
| 1435 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1436 | \r |
| 1437 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1438 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1439 | configuration registers from a single PCI function to be read. Size is\r |
| 1440 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1441 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1442 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1443 | end of the range.\r |
| 1444 | \r |
| 1445 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1446 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1447 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1448 | \r |
| 1449 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1450 | Function and Register.\r |
| 1451 | @param Size Size in bytes of the transfer.\r |
| 1452 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1453 | \r |
| 1454 | @return Size\r |
| 1455 | \r |
| 1456 | **/\r |
| 1457 | UINTN\r |
| 1458 | EFIAPI\r |
| 1459 | PciExpressReadBuffer (\r |
| 1460 | IN UINTN StartAddress,\r |
| 1461 | IN UINTN Size,\r |
| 1462 | OUT VOID *Buffer\r |
| 1463 | )\r |
| 1464 | {\r |
| 1465 | UINTN ReturnValue;\r |
| 1466 | \r |
| 1467 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1468 | \r |
| 1469 | if (Size == 0) {\r |
| 1470 | return Size;\r |
| 1471 | }\r |
| 1472 | \r |
| 1473 | ASSERT (Buffer != NULL);\r |
| 1474 | \r |
| 1475 | //\r |
| 1476 | // Save Size for return\r |
| 1477 | //\r |
| 1478 | ReturnValue = Size;\r |
| 1479 | \r |
| 1480 | if ((StartAddress & 1) != 0) {\r |
| 1481 | //\r |
| 1482 | // Read a byte if StartAddress is byte aligned\r |
| 1483 | //\r |
| 1484 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r |
| 1485 | StartAddress += sizeof (UINT8);\r |
| 1486 | Size -= sizeof (UINT8);\r |
| 1487 | Buffer = (UINT8*)Buffer + 1;\r |
| 1488 | }\r |
| 1489 | \r |
| 1490 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1491 | //\r |
| 1492 | // Read a word if StartAddress is word aligned\r |
| 1493 | //\r |
| 1494 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
| 1495 | \r |
| 1496 | StartAddress += sizeof (UINT16);\r |
| 1497 | Size -= sizeof (UINT16);\r |
| 1498 | Buffer = (UINT16*)Buffer + 1;\r |
| 1499 | }\r |
| 1500 | \r |
| 1501 | while (Size >= sizeof (UINT32)) {\r |
| 1502 | //\r |
| 1503 | // Read as many double words as possible\r |
| 1504 | //\r |
| 1505 | WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r |
| 1506 | \r |
| 1507 | StartAddress += sizeof (UINT32);\r |
| 1508 | Size -= sizeof (UINT32);\r |
| 1509 | Buffer = (UINT32*)Buffer + 1;\r |
| 1510 | }\r |
| 1511 | \r |
| 1512 | if (Size >= sizeof (UINT16)) {\r |
| 1513 | //\r |
| 1514 | // Read the last remaining word if exist\r |
| 1515 | //\r |
| 1516 | WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r |
| 1517 | StartAddress += sizeof (UINT16);\r |
| 1518 | Size -= sizeof (UINT16);\r |
| 1519 | Buffer = (UINT16*)Buffer + 1;\r |
| 1520 | }\r |
| 1521 | \r |
| 1522 | if (Size >= sizeof (UINT8)) {\r |
| 1523 | //\r |
| 1524 | // Read the last remaining byte if exist\r |
| 1525 | //\r |
| 1526 | *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r |
| 1527 | }\r |
| 1528 | \r |
| 1529 | return ReturnValue;\r |
| 1530 | }\r |
| 1531 | \r |
| 1532 | /**\r |
| 1533 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1534 | configuration space.\r |
| 1535 | \r |
| 1536 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1537 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1538 | configuration registers from a single PCI function to be written. Size is\r |
| 1539 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1540 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1541 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1542 | and the end of the range.\r |
| 1543 | \r |
| 1544 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1545 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1546 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1547 | \r |
| 1548 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1549 | Function and Register.\r |
| 1550 | @param Size Size in bytes of the transfer.\r |
| 1551 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1552 | \r |
| 1553 | @return Size\r |
| 1554 | \r |
| 1555 | **/\r |
| 1556 | UINTN\r |
| 1557 | EFIAPI\r |
| 1558 | PciExpressWriteBuffer (\r |
| 1559 | IN UINTN StartAddress,\r |
| 1560 | IN UINTN Size,\r |
| 1561 | IN VOID *Buffer\r |
| 1562 | )\r |
| 1563 | {\r |
| 1564 | UINTN ReturnValue;\r |
| 1565 | \r |
| 1566 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1567 | \r |
| 1568 | if (Size == 0) {\r |
| 1569 | return 0;\r |
| 1570 | }\r |
| 1571 | \r |
| 1572 | ASSERT (Buffer != NULL);\r |
| 1573 | \r |
| 1574 | //\r |
| 1575 | // Save Size for return\r |
| 1576 | //\r |
| 1577 | ReturnValue = Size;\r |
| 1578 | \r |
| 1579 | if ((StartAddress & 1) != 0) {\r |
| 1580 | //\r |
| 1581 | // Write a byte if StartAddress is byte aligned\r |
| 1582 | //\r |
| 1583 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1584 | StartAddress += sizeof (UINT8);\r |
| 1585 | Size -= sizeof (UINT8);\r |
| 1586 | Buffer = (UINT8*)Buffer + 1;\r |
| 1587 | }\r |
| 1588 | \r |
| 1589 | if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r |
| 1590 | //\r |
| 1591 | // Write a word if StartAddress is word aligned\r |
| 1592 | //\r |
| 1593 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
| 1594 | StartAddress += sizeof (UINT16);\r |
| 1595 | Size -= sizeof (UINT16);\r |
| 1596 | Buffer = (UINT16*)Buffer + 1;\r |
| 1597 | }\r |
| 1598 | \r |
| 1599 | while (Size >= sizeof (UINT32)) {\r |
| 1600 | //\r |
| 1601 | // Write as many double words as possible\r |
| 1602 | //\r |
| 1603 | PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r |
| 1604 | StartAddress += sizeof (UINT32);\r |
| 1605 | Size -= sizeof (UINT32);\r |
| 1606 | Buffer = (UINT32*)Buffer + 1;\r |
| 1607 | }\r |
| 1608 | \r |
| 1609 | if (Size >= sizeof (UINT16)) {\r |
| 1610 | //\r |
| 1611 | // Write the last remaining word if exist\r |
| 1612 | //\r |
| 1613 | PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r |
| 1614 | StartAddress += sizeof (UINT16);\r |
| 1615 | Size -= sizeof (UINT16);\r |
| 1616 | Buffer = (UINT16*)Buffer + 1;\r |
| 1617 | }\r |
| 1618 | \r |
| 1619 | if (Size >= sizeof (UINT8)) {\r |
| 1620 | //\r |
| 1621 | // Write the last remaining byte if exist\r |
| 1622 | //\r |
| 1623 | PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1624 | }\r |
| 1625 | \r |
| 1626 | return ReturnValue;\r |
| 1627 | }\r |
projects / mirror_edk2.git / blame