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[mirror_edk2.git] / MdePkg / Library / DxeRuntimePciExpressLib / PciExpressLib.c

/** @file\r
  Functions in this library instance make use of MMIO functions in IoLib to\r
  access memory mapped PCI configuration space.\r
\r
  All assertions for I/O operations are handled in MMIO functions in the IoLib\r
  Library.\r
\r
  Copyright (c) 2006 - 2009, Intel Corporation. All rights reserved.<BR>\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
\r
#include <PiDxe.h>\r
\r
#include <Guid/EventGroup.h>\r
\r
#include <Library/BaseLib.h>\r
#include <Library/PciExpressLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/UefiRuntimeLib.h>\r
\r
///\r
/// Define table for mapping PCI Express MMIO physical addresses to virtual addresses at OS runtime\r
///\r
typedef struct {\r
  UINTN  PhysicalAddress;\r
  UINTN  VirtualAddress;\r
} PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE;\r
\r
///\r
/// Set Virtual Address Map Event\r
///\r
EFI_EVENT                               mDxeRuntimePciExpressLibVirtualNotifyEvent = NULL;\r
\r
///\r
/// Module global that contains the base physical address of the PCI Express MMIO range\r
///\r
UINTN                                   mDxeRuntimePciExpressLibPciExpressBaseAddress = 0;\r
\r
///\r
/// The number of PCI devices that have been registered for runtime access\r
///\r
UINTN                                   mDxeRuntimePciExpressLibNumberOfRuntimeRanges = 0;\r
\r
///\r
/// The table of PCI devices that have been registered for runtime access\r
///\r
PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE  *mDxeRuntimePciExpressLibRegistrationTable = NULL;\r
\r
///\r
/// The table index of the most recent virtual address lookup\r
///\r
UINTN                                   mDxeRuntimePciExpressLibLastRuntimeRange = 0;\r
\r
\r
/**\r
  Convert the physical PCI Express MMIO addresses for all registered PCI devices\r
  to virtual addresses.\r
\r
  @param[in]    Event   The Event that is being processed\r
  @param[in]    Context Event Context\r
**/\r
VOID\r
EFIAPI\r
DxeRuntimePciExpressLibVirtualNotify (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  UINTN  Index;\r
\r
  //\r
  // If there have been no runtime registrations, then just return\r
  //\r
  if (mDxeRuntimePciExpressLibRegistrationTable == NULL) {\r
    return;\r
  }\r
\r
  //\r
  // Convert physical addresses associated with the set of registered PCI devices to\r
  // virtual addresses.\r
  //\r
  for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
    EfiConvertPointer (0, (VOID **) &(mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress));\r
  }\r
\r
  //\r
  // Convert table pointer that is allocated from EfiRuntimeServicesData to a virtual address.\r
  //\r
  EfiConvertPointer (0, (VOID **) &mDxeRuntimePciExpressLibRegistrationTable);\r
}\r
\r
/**\r
  The constructor function caches the PCI Express Base Address and creates a \r
  Set Virtual Address Map event to convert physical address to virtual addresses.\r
  \r
  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
  @param  SystemTable   A pointer to the EFI System Table.\r
  \r
  @retval EFI_SUCCESS   The constructor completed successfully.\r
  @retval Other value   The constructor did not complete successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DxeRuntimePciExpressLibConstructor (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // Cache the physical address of the PCI Express MMIO range into a module global variable\r
  //\r
  mDxeRuntimePciExpressLibPciExpressBaseAddress = (UINTN) PcdGet64 (PcdPciExpressBaseAddress);\r
\r
  //\r
  // Register SetVirtualAddressMap () notify function\r
  //\r
  Status = gBS->CreateEventEx (\r
                  EVT_NOTIFY_SIGNAL,\r
                  TPL_NOTIFY,\r
                  DxeRuntimePciExpressLibVirtualNotify,\r
                  NULL,\r
                  &gEfiEventVirtualAddressChangeGuid,\r
                  &mDxeRuntimePciExpressLibVirtualNotifyEvent\r
                  );\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
\r
/**\r
  The destructor function frees any allocated buffers and closes the Set Virtual \r
  Address Map event.\r
  \r
  @param  ImageHandle   The firmware allocated handle for the EFI image.\r
  @param  SystemTable   A pointer to the EFI System Table.\r
  \r
  @retval EFI_SUCCESS   The destructor completed successfully.\r
  @retval Other value   The destructor did not complete successfully.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DxeRuntimePciExpressLibDestructor (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
\r
  //\r
  // If one or more PCI devices have been registered for runtime access, then \r
  // free the registration table.\r
  //\r
  if (mDxeRuntimePciExpressLibRegistrationTable != NULL) {\r
    FreePool (mDxeRuntimePciExpressLibRegistrationTable);\r
  }\r
\r
  //\r
  // Close the Set Virtual Address Map event\r
  //\r
  Status = gBS->CloseEvent (mDxeRuntimePciExpressLibVirtualNotifyEvent);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  return Status;\r
}\r
\r
/**\r
  Gets the base address of PCI Express.\r
  \r
  This internal functions retrieves PCI Express Base Address via a PCD entry\r
  PcdPciExpressBaseAddress.\r
  \r
  @param  Address  Address that encodes the PCI Bus, Device, Function and Register.\r
  @return          The base address of PCI Express.\r
\r
**/\r
UINTN\r
GetPciExpressAddress (\r
  IN UINTN  Address\r
  )\r
{\r
  UINTN  Index;\r
\r
  //\r
  // Make sure Address is valid\r
  //\r
  ASSERT (((Address) & ~0xfffffff) == 0);\r
\r
  //\r
  // Convert Address to a physical address in the MMIO PCI Express range\r
  //\r
  Address += mDxeRuntimePciExpressLibPciExpressBaseAddress;\r
\r
  //\r
  // If SetVirtualAddressMap() has not been called, then just return the physical address\r
  //\r
  if (!EfiGoneVirtual ()) {\r
    return Address;\r
  }\r
\r
  //\r
  // See if there is a physical address match at the exact same index as the last address match\r
  //\r
  if (mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].PhysicalAddress == (Address & (~0x00000fff))) {\r
    //\r
    // Convert the physical address to a virtual address and return the virtual address\r
    //\r
    return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibLastRuntimeRange].VirtualAddress;\r
  }\r
\r
  //\r
  // Search the entire table for a physical address match\r
  //\r
  for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
    if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == (Address & (~0x00000fff))) {\r
      //\r
      // Cache the matching index value\r
      //\r
      mDxeRuntimePciExpressLibLastRuntimeRange = Index;\r
      //\r
      // Convert the physical address to a virtual address and return the virtual address\r
      //\r
      return (Address & 0x00000fff) + mDxeRuntimePciExpressLibRegistrationTable[Index].VirtualAddress;\r
    }\r
  }\r
\r
  //\r
  // No match was found.  This is a critical error at OS runtime, so ASSERT() and force a breakpoint.\r
  //\r
  ASSERT (FALSE);\r
  CpuBreakpoint();\r
\r
  //\r
  // Return the physical address \r
  //\r
  return Address;\r
}\r
\r
/**\r
  Registers a PCI device so PCI configuration registers may be accessed after \r
  SetVirtualAddressMap().\r
  \r
  Registers the PCI device specified by Address so all the PCI configuration \r
  registers associated with that PCI device may be accessed after SetVirtualAddressMap() \r
  is called.\r
  \r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  \r
  @retval RETURN_SUCCESS           The PCI device was registered for runtime access.\r
  @retval RETURN_UNSUPPORTED       An attempt was made to call this function \r
                                   after ExitBootServices().\r
  @retval RETURN_UNSUPPORTED       The resources required to access the PCI device\r
                                   at runtime could not be mapped.\r
  @retval RETURN_OUT_OF_RESOURCES  There are not enough resources available to\r
                                   complete the registration.\r
\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciExpressRegisterForRuntimeAccess (\r
  IN UINTN  Address\r
  )\r
{\r
  EFI_STATUS                       Status;\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  Descriptor;\r
  UINTN                            Index;\r
  VOID                             *NewTable;\r
\r
  //\r
  // Return an error if this function is called after ExitBootServices().\r
  //\r
  if (EfiAtRuntime ()) {\r
    return RETURN_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Make sure Address is valid\r
  //\r
  ASSERT (((Address) & ~0xfffffff) == 0);\r
\r
  //\r
  // Convert Address to a physical address in the MMIO PCI Express range\r
  // at the beginning of the PCI Configuration header for the specified\r
  // PCI Bus/Dev/Func\r
  //\r
  Address = GetPciExpressAddress (Address & 0x0ffff000);\r
\r
  //\r
  // See if Address has already been registerd for runtime access\r
  //\r
  for (Index = 0; Index < mDxeRuntimePciExpressLibNumberOfRuntimeRanges; Index++) {\r
    if (mDxeRuntimePciExpressLibRegistrationTable[Index].PhysicalAddress == Address) {\r
      return RETURN_SUCCESS;\r
    }\r
  }\r
\r
  //\r
  // Get the GCD Memory Descriptor for the PCI Express Bus/Dev/Func specified by Address\r
  //\r
  Status = gDS->GetMemorySpaceDescriptor (Address, &Descriptor);\r
  if (EFI_ERROR (Status)) {\r
    return RETURN_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Mark the 4KB region for the PCI Express Bus/Dev/Func as EFI_RUNTIME_MEMORY so the OS\r
  // will allocate a virtual address range for the 4KB PCI Configuration Header.\r
  //\r
  Status = gDS->SetMemorySpaceAttributes (Address, 0x1000, Descriptor.Attributes | EFI_MEMORY_RUNTIME);\r
  if (EFI_ERROR (Status)) {\r
    return RETURN_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Grow the size of the registration table\r
  //\r
  NewTable = ReallocateRuntimePool (\r
               (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 0) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
               (mDxeRuntimePciExpressLibNumberOfRuntimeRanges + 1) * sizeof (PCI_EXPRESS_RUNTIME_REGISTRATION_TABLE), \r
               mDxeRuntimePciExpressLibRegistrationTable\r
               );\r
  if (NewTable == NULL) {\r
    return RETURN_OUT_OF_RESOURCES;\r
  }\r
  mDxeRuntimePciExpressLibRegistrationTable = NewTable;\r
  mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].PhysicalAddress = Address;\r
  mDxeRuntimePciExpressLibRegistrationTable[mDxeRuntimePciExpressLibNumberOfRuntimeRanges].VirtualAddress  = Address;\r
  mDxeRuntimePciExpressLibNumberOfRuntimeRanges++;\r
\r
  return RETURN_SUCCESS;\r
}\r
\r
\r
/**\r
  Reads an 8-bit PCI configuration register.\r
\r
  Reads and returns the 8-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressRead8 (\r
  IN      UINTN                     Address\r
  )\r
{\r
  return MmioRead8 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
  Writes an 8-bit PCI configuration register.\r
\r
  Writes the 8-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressWrite8 (\r
  IN      UINTN                     Address,\r
  IN      UINT8                     Value\r
  )\r
{\r
  return MmioWrite8 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
  Performs a bitwise OR of an 8-bit PCI configuration register with\r
  an 8-bit value.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 8-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressOr8 (\r
  IN      UINTN                     Address,\r
  IN      UINT8                     OrData\r
  )\r
{\r
  return MmioOr8 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
  value.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 8-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAnd8 (\r
  IN      UINTN                     Address,\r
  IN      UINT8                     AndData\r
  )\r
{\r
  return MmioAnd8 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
  Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r
  value, followed a  bitwise OR with another 8-bit value.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 8-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressAndThenOr8 (\r
  IN      UINTN                     Address,\r
  IN      UINT8                     AndData,\r
  IN      UINT8                     OrData\r
  )\r
{\r
  return MmioAndThenOr8 (\r
           GetPciExpressAddress (Address),\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register.\r
\r
  Reads the bit field in an 8-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldRead8 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit\r
  )\r
{\r
  return MmioBitFieldRead8 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit\r
           );\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  8-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldWrite8 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT8                     Value\r
  )\r
{\r
  return MmioBitFieldWrite8 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           Value\r
           );\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 8-bit port.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 8-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldOr8 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT8                     OrData\r
  )\r
{\r
  return MmioBitFieldOr8 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 8-bit register.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 8-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAnd8 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT8                     AndData\r
  )\r
{\r
  return MmioBitFieldAnd8 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  8-bit port.\r
\r
  Reads the 8-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 8-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If StartBit is greater than 7, then ASSERT().\r
  If EndBit is greater than 7, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..7.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..7.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT8\r
EFIAPI\r
PciExpressBitFieldAndThenOr8 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT8                     AndData,\r
  IN      UINT8                     OrData\r
  )\r
{\r
  return MmioBitFieldAndThenOr8 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a 16-bit PCI configuration register.\r
\r
  Reads and returns the 16-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressRead16 (\r
  IN      UINTN                     Address\r
  )\r
{\r
  return MmioRead16 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
  Writes a 16-bit PCI configuration register.\r
\r
  Writes the 16-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressWrite16 (\r
  IN      UINTN                     Address,\r
  IN      UINT16                    Value\r
  )\r
{\r
  return MmioWrite16 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
  Performs a bitwise OR of a 16-bit PCI configuration register with\r
  a 16-bit value.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 16-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressOr16 (\r
  IN      UINTN                     Address,\r
  IN      UINT16                    OrData\r
  )\r
{\r
  return MmioOr16 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
  value.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 16-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAnd16 (\r
  IN      UINTN                     Address,\r
  IN      UINT16                    AndData\r
  )\r
{\r
  return MmioAnd16 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
  Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r
  value, followed a  bitwise OR with another 16-bit value.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 16-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressAndThenOr16 (\r
  IN      UINTN                     Address,\r
  IN      UINT16                    AndData,\r
  IN      UINT16                    OrData\r
  )\r
{\r
  return MmioAndThenOr16 (\r
           GetPciExpressAddress (Address),\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register.\r
\r
  Reads the bit field in a 16-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldRead16 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit\r
  )\r
{\r
  return MmioBitFieldRead16 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit\r
           );\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  16-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldWrite16 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT16                    Value\r
  )\r
{\r
  return MmioBitFieldWrite16 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           Value\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 16-bit port.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 16-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldOr16 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT16                    OrData\r
  )\r
{\r
  return MmioBitFieldOr16 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 16-bit register.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 16-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAnd16 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT16                    AndData\r
  )\r
{\r
  return MmioBitFieldAnd16 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  16-bit port.\r
\r
  Reads the 16-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 16-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 16-bit boundary, then ASSERT().\r
  If StartBit is greater than 15, then ASSERT().\r
  If EndBit is greater than 15, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..15.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..15.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT16\r
EFIAPI\r
PciExpressBitFieldAndThenOr16 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT16                    AndData,\r
  IN      UINT16                    OrData\r
  )\r
{\r
  return MmioBitFieldAndThenOr16 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a 32-bit PCI configuration register.\r
\r
  Reads and returns the 32-bit PCI configuration register specified by Address.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
\r
  @return The read value from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressRead32 (\r
  IN      UINTN                     Address\r
  )\r
{\r
  return MmioRead32 (GetPciExpressAddress (Address));\r
}\r
\r
/**\r
  Writes a 32-bit PCI configuration register.\r
\r
  Writes the 32-bit PCI configuration register specified by Address with the\r
  value specified by Value. Value is returned. This function must guarantee\r
  that all PCI read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  Value   The value to write.\r
\r
  @return The value written to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressWrite32 (\r
  IN      UINTN                     Address,\r
  IN      UINT32                    Value\r
  )\r
{\r
  return MmioWrite32 (GetPciExpressAddress (Address), Value);\r
}\r
\r
/**\r
  Performs a bitwise OR of a 32-bit PCI configuration register with\r
  a 32-bit value.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 32-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  OrData  The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressOr32 (\r
  IN      UINTN                     Address,\r
  IN      UINT32                    OrData\r
  )\r
{\r
  return MmioOr32 (GetPciExpressAddress (Address), OrData);\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
  value.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 32-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAnd32 (\r
  IN      UINTN                     Address,\r
  IN      UINT32                    AndData\r
  )\r
{\r
  return MmioAnd32 (GetPciExpressAddress (Address), AndData);\r
}\r
\r
/**\r
  Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r
  value, followed a  bitwise OR with another 32-bit value.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData,\r
  performs a bitwise OR between the result of the AND operation and\r
  the value specified by OrData, and writes the result to the 32-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
\r
  @param  Address Address that encodes the PCI Bus, Device, Function and\r
                  Register.\r
  @param  AndData The value to AND with the PCI configuration register.\r
  @param  OrData  The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressAndThenOr32 (\r
  IN      UINTN                     Address,\r
  IN      UINT32                    AndData,\r
  IN      UINT32                    OrData\r
  )\r
{\r
  return MmioAndThenOr32 (\r
           GetPciExpressAddress (Address),\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field of a PCI configuration register.\r
\r
  Reads the bit field in a 32-bit PCI configuration register. The bit field is\r
  specified by the StartBit and the EndBit. The value of the bit field is\r
  returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to read.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
\r
  @return The value of the bit field read from the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldRead32 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit\r
  )\r
{\r
  return MmioBitFieldRead32 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit\r
           );\r
}\r
\r
/**\r
  Writes a bit field to a PCI configuration register.\r
\r
  Writes Value to the bit field of the PCI configuration register. The bit\r
  field is specified by the StartBit and the EndBit. All other bits in the\r
  destination PCI configuration register are preserved. The new value of the\r
  32-bit register is returned.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  Value     New value of the bit field.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldWrite32 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT32                    Value\r
  )\r
{\r
  return MmioBitFieldWrite32 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           Value\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r
  writes the result back to the bit field in the 32-bit port.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise OR between the read result and the value specified by\r
  OrData, and writes the result to the 32-bit PCI configuration register\r
  specified by Address. The value written to the PCI configuration register is\r
  returned. This function must guarantee that all PCI read and write operations\r
  are serialized. Extra left bits in OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  OrData    The value to OR with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldOr32 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT32                    OrData\r
  )\r
{\r
  return MmioBitFieldOr32 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r
  AND, and writes the result back to the bit field in the 32-bit register.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND between the read result and the value specified by AndData, and\r
  writes the result to the 32-bit PCI configuration register specified by\r
  Address. The value written to the PCI configuration register is returned.\r
  This function must guarantee that all PCI read and write operations are\r
  serialized. Extra left bits in AndData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAnd32 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT32                    AndData\r
  )\r
{\r
  return MmioBitFieldAnd32 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData\r
           );\r
}\r
\r
/**\r
  Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r
  bitwise OR, and writes the result back to the bit field in the\r
  32-bit port.\r
\r
  Reads the 32-bit PCI configuration register specified by Address, performs a\r
  bitwise AND followed by a bitwise OR between the read result and\r
  the value specified by AndData, and writes the result to the 32-bit PCI\r
  configuration register specified by Address. The value written to the PCI\r
  configuration register is returned. This function must guarantee that all PCI\r
  read and write operations are serialized. Extra left bits in both AndData and\r
  OrData are stripped.\r
\r
  If Address > 0x0FFFFFFF, then ASSERT().\r
  If Address is not aligned on a 32-bit boundary, then ASSERT().\r
  If StartBit is greater than 31, then ASSERT().\r
  If EndBit is greater than 31, then ASSERT().\r
  If EndBit is less than StartBit, then ASSERT().\r
\r
  @param  Address   PCI configuration register to write.\r
  @param  StartBit  The ordinal of the least significant bit in the bit field.\r
                    Range 0..31.\r
  @param  EndBit    The ordinal of the most significant bit in the bit field.\r
                    Range 0..31.\r
  @param  AndData   The value to AND with the PCI configuration register.\r
  @param  OrData    The value to OR with the result of the AND operation.\r
\r
  @return The value written back to the PCI configuration register.\r
\r
**/\r
UINT32\r
EFIAPI\r
PciExpressBitFieldAndThenOr32 (\r
  IN      UINTN                     Address,\r
  IN      UINTN                     StartBit,\r
  IN      UINTN                     EndBit,\r
  IN      UINT32                    AndData,\r
  IN      UINT32                    OrData\r
  )\r
{\r
  return MmioBitFieldAndThenOr32 (\r
           GetPciExpressAddress (Address),\r
           StartBit,\r
           EndBit,\r
           AndData,\r
           OrData\r
           );\r
}\r
\r
/**\r
  Reads a range of PCI configuration registers into a caller supplied buffer.\r
\r
  Reads the range of PCI configuration registers specified by StartAddress and\r
  Size into the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be read. Size is\r
  returned. When possible 32-bit PCI configuration read cycles are used to read\r
  from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r
  and 16-bit PCI configuration read cycles may be used at the beginning and the\r
  end of the range.\r
\r
  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer receiving the data read.\r
\r
  @return Size read data from StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressReadBuffer (\r
  IN      UINTN                     StartAddress,\r
  IN      UINTN                     Size,\r
  OUT     VOID                      *Buffer\r
  )\r
{\r
  UINTN   ReturnValue;\r
\r
  //\r
  // Make sure Address is valid\r
  //\r
  ASSERT (((StartAddress) & ~0xfffffff) == 0);\r
  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
  if (Size == 0) {\r
    return Size;\r
  }\r
\r
  ASSERT (Buffer != NULL);\r
\r
  //\r
  // Save Size for return\r
  //\r
  ReturnValue = Size;\r
\r
  if ((StartAddress & 1) != 0) {\r
    //\r
    // Read a byte if StartAddress is byte aligned\r
    //\r
    *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
    StartAddress += sizeof (UINT8);\r
    Size -= sizeof (UINT8);\r
    Buffer = (UINT8*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
    //\r
    // Read a word if StartAddress is word aligned\r
    //\r
    WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
\r
    StartAddress += sizeof (UINT16);\r
    Size -= sizeof (UINT16);\r
    Buffer = (UINT16*)Buffer + 1;\r
  }\r
\r
  while (Size >= sizeof (UINT32)) {\r
    //\r
    // Read as many double words as possible\r
    //\r
    WriteUnaligned32 ((UINT32 *) Buffer, (UINT32) PciExpressRead32 (StartAddress));\r
\r
    StartAddress += sizeof (UINT32);\r
    Size -= sizeof (UINT32);\r
    Buffer = (UINT32*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT16)) {\r
    //\r
    // Read the last remaining word if exist\r
    //\r
    WriteUnaligned16 ((UINT16 *) Buffer, (UINT16) PciExpressRead16 (StartAddress));\r
    StartAddress += sizeof (UINT16);\r
    Size -= sizeof (UINT16);\r
    Buffer = (UINT16*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT8)) {\r
    //\r
    // Read the last remaining byte if exist\r
    //\r
    *(volatile UINT8 *)Buffer = PciExpressRead8 (StartAddress);\r
  }\r
\r
  return ReturnValue;\r
}\r
\r
/**\r
  Copies the data in a caller supplied buffer to a specified range of PCI\r
  configuration space.\r
\r
  Writes the range of PCI configuration registers specified by StartAddress and\r
  Size from the buffer specified by Buffer. This function only allows the PCI\r
  configuration registers from a single PCI function to be written. Size is\r
  returned. When possible 32-bit PCI configuration write cycles are used to\r
  write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r
  8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r
  and the end of the range.\r
\r
  If StartAddress > 0x0FFFFFFF, then ASSERT().\r
  If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r
  If Size > 0 and Buffer is NULL, then ASSERT().\r
\r
  @param  StartAddress  Starting address that encodes the PCI Bus, Device,\r
                        Function and Register.\r
  @param  Size          Size in bytes of the transfer.\r
  @param  Buffer        Pointer to a buffer containing the data to write.\r
\r
  @return Size written to StartAddress.\r
\r
**/\r
UINTN\r
EFIAPI\r
PciExpressWriteBuffer (\r
  IN      UINTN                     StartAddress,\r
  IN      UINTN                     Size,\r
  IN      VOID                      *Buffer\r
  )\r
{\r
  UINTN                             ReturnValue;\r
\r
  //\r
  // Make sure Address is valid\r
  //\r
  ASSERT (((StartAddress) & ~0xfffffff) == 0);\r
  ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r
\r
  if (Size == 0) {\r
    return 0;\r
  }\r
\r
  ASSERT (Buffer != NULL);\r
\r
  //\r
  // Save Size for return\r
  //\r
  ReturnValue = Size;\r
\r
  if ((StartAddress & 1) != 0) {\r
    //\r
    // Write a byte if StartAddress is byte aligned\r
    //\r
    PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
    StartAddress += sizeof (UINT8);\r
    Size -= sizeof (UINT8);\r
    Buffer = (UINT8*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT16) && (StartAddress & 2) != 0) {\r
    //\r
    // Write a word if StartAddress is word aligned\r
    //\r
    PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
    StartAddress += sizeof (UINT16);\r
    Size -= sizeof (UINT16);\r
    Buffer = (UINT16*)Buffer + 1;\r
  }\r
\r
  while (Size >= sizeof (UINT32)) {\r
    //\r
    // Write as many double words as possible\r
    //\r
    PciExpressWrite32 (StartAddress, ReadUnaligned32 ((UINT32*)Buffer));\r
    StartAddress += sizeof (UINT32);\r
    Size -= sizeof (UINT32);\r
    Buffer = (UINT32*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT16)) {\r
    //\r
    // Write the last remaining word if exist\r
    //\r
    PciExpressWrite16 (StartAddress, ReadUnaligned16 ((UINT16*)Buffer));\r
    StartAddress += sizeof (UINT16);\r
    Size -= sizeof (UINT16);\r
    Buffer = (UINT16*)Buffer + 1;\r
  }\r
\r
  if (Size >= sizeof (UINT8)) {\r
    //\r
    // Write the last remaining byte if exist\r
    //\r
    PciExpressWrite8 (StartAddress, *(UINT8*)Buffer);\r
  }\r
\r
  return ReturnValue;\r
}\r