| 1a3eaf06 |
1 | /** @file\r |
| 2 | PCI Library using PCI CFG2 PPI.\r |
| 3 | \r |
| 4 | Copyright (c) 2007 - 2008, Intel Corporation All rights\r |
| 5 | reserved. This program and the accompanying materials are\r |
| 6 | licensed and made available under the terms and conditions of\r |
| 7 | the BSD License which accompanies this distribution. The full\r |
| 8 | text of the license may be found at\r |
| 9 | http://opensource.org/licenses/bsd-license.php\r |
| 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 13 | \r |
| 14 | **/\r |
| 15 | \r |
| 16 | #include <PiPei.h>\r |
| 17 | \r |
| 18 | #include <Ppi/PciCfg2.h>\r |
| 19 | \r |
| 20 | #include <Library/PciLib.h>\r |
| 21 | #include <Library/BaseLib.h>\r |
| 22 | #include <Library/PeiServicesTablePointerLib.h>\r |
| 23 | #include <Library/DebugLib.h>\r |
| 24 | #include <Library/PeiServicesLib.h>\r |
| 25 | \r |
| 26 | /**\r |
| 27 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r |
| 28 | only in the low 28 bits.\r |
| 29 | \r |
| 30 | @param A The address to validate.\r |
| 31 | @param M Additional bits to assert to be zero.\r |
| 32 | \r |
| 33 | **/\r |
| 34 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r |
| 35 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r |
| 36 | \r |
| 37 | /**\r |
| 38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r |
| 39 | \r |
| 40 | @param A Address that encodes the PCI Bus, Device, Function and\r |
| 41 | Register.\r |
| 42 | \r |
| 43 | **/\r |
| 44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r |
| e43e4b3e |
45 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
| 1a3eaf06 |
46 | \r |
| 47 | /**\r |
| 48 | Internal worker function to read a PCI configuration register.\r |
| 49 | \r |
| 50 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r |
| 51 | It reads and returns the PCI configuration register specified by Address,\r |
| 52 | the width of data is specified by Width.\r |
| 53 | \r |
| 54 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 55 | Register.\r |
| 56 | @param Width Width of data to read\r |
| 57 | \r |
| 58 | @return The value read from the PCI configuration register.\r |
| 59 | \r |
| 60 | **/\r |
| 61 | UINT32\r |
| 62 | PeiPciLibPciCfg2ReadWorker (\r |
| 63 | IN UINTN Address,\r |
| 64 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r |
| 65 | )\r |
| 66 | {\r |
| 67 | EFI_STATUS Status;\r |
| 68 | UINT32 Data;\r |
| 69 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r |
| 43fe5cdc |
70 | UINT64 PciCfg2Address;\r |
| 1a3eaf06 |
71 | \r |
| 72 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r |
| 73 | ASSERT_EFI_ERROR (Status);\r |
| 74 | ASSERT (PciCfg2Ppi != NULL);\r |
| 75 | \r |
| 43fe5cdc |
76 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
| 1a3eaf06 |
77 | PciCfg2Ppi->Read (\r |
| 78 | GetPeiServicesTablePointer (),\r |
| 79 | PciCfg2Ppi,\r |
| 80 | Width,\r |
| 43fe5cdc |
81 | PciCfg2Address,\r |
| 1a3eaf06 |
82 | &Data\r |
| 83 | );\r |
| 84 | \r |
| 85 | return Data;\r |
| 86 | }\r |
| 87 | \r |
| 88 | /**\r |
| 89 | Internal worker function to writes a PCI configuration register.\r |
| 90 | \r |
| 91 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r |
| 92 | It writes the PCI configuration register specified by Address with the\r |
| 93 | value specified by Data. The width of data is specifed by Width.\r |
| 94 | Data is returned.\r |
| 95 | \r |
| 96 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 97 | Register.\r |
| 98 | @param Width Width of data to write\r |
| 99 | @param Data The value to write.\r |
| 100 | \r |
| 101 | @return The value written to the PCI configuration register.\r |
| 102 | \r |
| 103 | **/\r |
| 104 | UINT32\r |
| 105 | PeiPciLibPciCfg2WriteWorker (\r |
| 106 | IN UINTN Address,\r |
| 107 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r |
| 108 | IN UINT32 Data\r |
| 109 | )\r |
| 110 | {\r |
| 111 | EFI_STATUS Status;\r |
| 112 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r |
| 43fe5cdc |
113 | UINT64 PciCfg2Address;\r |
| 1a3eaf06 |
114 | \r |
| 115 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r |
| 116 | ASSERT_EFI_ERROR (Status);\r |
| 117 | ASSERT (PciCfg2Ppi != NULL);\r |
| 118 | \r |
| 43fe5cdc |
119 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
| 1a3eaf06 |
120 | PciCfg2Ppi->Write (\r |
| 121 | GetPeiServicesTablePointer (),\r |
| 122 | PciCfg2Ppi,\r |
| 123 | Width,\r |
| 43fe5cdc |
124 | PciCfg2Address,\r |
| 1a3eaf06 |
125 | &Data\r |
| 126 | );\r |
| 127 | \r |
| 128 | return Data;\r |
| 129 | }\r |
| 130 | \r |
| 3e3ae634 |
131 | /**\r |
| d11195a3 |
132 | Registers a PCI device so PCI configuration registers may be accessed after \r |
| 3e3ae634 |
133 | SetVirtualAddressMap().\r |
| 134 | \r |
| d11195a3 |
135 | Registers the PCI device specified by Address so all the PCI configuration registers \r |
| 136 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
| 137 | \r |
| 3e3ae634 |
138 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 139 | \r |
| 140 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 141 | Register.\r |
| 142 | \r |
| 143 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 144 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r |
| 145 | after ExitBootServices().\r |
| 146 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r |
| 147 | at runtime could not be mapped.\r |
| 148 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r |
| 149 | complete the registration.\r |
| 150 | \r |
| 151 | **/\r |
| 152 | RETURN_STATUS\r |
| 153 | EFIAPI\r |
| 154 | PciRegisterForRuntimeAccess (\r |
| 155 | IN UINTN Address\r |
| 156 | )\r |
| 157 | {\r |
| 158 | return RETURN_UNSUPPORTED;\r |
| 159 | }\r |
| 160 | \r |
| 1a3eaf06 |
161 | /**\r |
| 162 | Reads an 8-bit PCI configuration register.\r |
| 163 | \r |
| 164 | Reads and returns the 8-bit PCI configuration register specified by Address.\r |
| 165 | This function must guarantee that all PCI read and write operations are\r |
| 166 | serialized.\r |
| 167 | \r |
| 168 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 169 | \r |
| 170 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 171 | Register.\r |
| 172 | \r |
| 0c3437e0 |
173 | @return The read value from the PCI configuration register.\r |
| 1a3eaf06 |
174 | \r |
| 175 | **/\r |
| 176 | UINT8\r |
| 177 | EFIAPI\r |
| 178 | PciRead8 (\r |
| 179 | IN UINTN Address\r |
| 180 | )\r |
| 181 | {\r |
| 182 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 183 | \r |
| 184 | return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r |
| 185 | }\r |
| 186 | \r |
| 187 | /**\r |
| 188 | Writes an 8-bit PCI configuration register.\r |
| 189 | \r |
| 190 | Writes the 8-bit PCI configuration register specified by Address with the\r |
| 191 | value specified by Value. Value is returned. This function must guarantee\r |
| 192 | that all PCI read and write operations are serialized.\r |
| 193 | \r |
| 194 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 195 | \r |
| 196 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 197 | Register.\r |
| 0c3437e0 |
198 | @param Value The value to write.\r |
| 1a3eaf06 |
199 | \r |
| 200 | @return The value written to the PCI configuration register.\r |
| 201 | \r |
| 202 | **/\r |
| 203 | UINT8\r |
| 204 | EFIAPI\r |
| 205 | PciWrite8 (\r |
| 206 | IN UINTN Address,\r |
| 0c3437e0 |
207 | IN UINT8 Value\r |
| 1a3eaf06 |
208 | )\r |
| 209 | {\r |
| 210 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
| 211 | \r |
| 0c3437e0 |
212 | return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
| 1a3eaf06 |
213 | }\r |
| 214 | \r |
| 215 | /**\r |
| 62991af2 |
216 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
| 1a3eaf06 |
217 | an 8-bit value.\r |
| 218 | \r |
| 219 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
220 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
221 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 222 | specified by Address. The value written to the PCI configuration register is\r |
| 223 | returned. This function must guarantee that all PCI read and write operations\r |
| 224 | are serialized.\r |
| 225 | \r |
| 226 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 227 | \r |
| 228 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 229 | Register.\r |
| 230 | @param OrData The value to OR with the PCI configuration register.\r |
| 231 | \r |
| 232 | @return The value written back to the PCI configuration register.\r |
| 233 | \r |
| 234 | **/\r |
| 235 | UINT8\r |
| 236 | EFIAPI\r |
| 237 | PciOr8 (\r |
| 238 | IN UINTN Address,\r |
| 239 | IN UINT8 OrData\r |
| 240 | )\r |
| 241 | {\r |
| 242 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r |
| 243 | }\r |
| 244 | \r |
| 245 | /**\r |
| 246 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 247 | value.\r |
| 248 | \r |
| 249 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 250 | bitwise AND between the read result and the value specified by AndData, and\r |
| 251 | writes the result to the 8-bit PCI configuration register specified by\r |
| 252 | Address. The value written to the PCI configuration register is returned.\r |
| 253 | This function must guarantee that all PCI read and write operations are\r |
| 254 | serialized.\r |
| 255 | \r |
| 256 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 257 | \r |
| 258 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 259 | Register.\r |
| 260 | @param AndData The value to AND with the PCI configuration register.\r |
| 261 | \r |
| 262 | @return The value written back to the PCI configuration register.\r |
| 263 | \r |
| 264 | **/\r |
| 265 | UINT8\r |
| 266 | EFIAPI\r |
| 267 | PciAnd8 (\r |
| 268 | IN UINTN Address,\r |
| 269 | IN UINT8 AndData\r |
| 270 | )\r |
| 271 | {\r |
| 272 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r |
| 273 | }\r |
| 274 | \r |
| 275 | /**\r |
| 276 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r |
| 62991af2 |
277 | value, followed a bitwise OR with another 8-bit value.\r |
| 1a3eaf06 |
278 | \r |
| 279 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 280 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
281 | performs a bitwise OR between the result of the AND operation and\r |
| 1a3eaf06 |
282 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
| 283 | configuration register specified by Address. The value written to the PCI\r |
| 284 | configuration register is returned. This function must guarantee that all PCI\r |
| 285 | read and write operations are serialized.\r |
| 286 | \r |
| 287 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 288 | \r |
| 289 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 290 | Register.\r |
| 291 | @param AndData The value to AND with the PCI configuration register.\r |
| 292 | @param OrData The value to OR with the result of the AND operation.\r |
| 293 | \r |
| 294 | @return The value written back to the PCI configuration register.\r |
| 295 | \r |
| 296 | **/\r |
| 297 | UINT8\r |
| 298 | EFIAPI\r |
| 299 | PciAndThenOr8 (\r |
| 300 | IN UINTN Address,\r |
| 301 | IN UINT8 AndData,\r |
| 302 | IN UINT8 OrData\r |
| 303 | )\r |
| 304 | {\r |
| 305 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r |
| 306 | }\r |
| 307 | \r |
| 308 | /**\r |
| 309 | Reads a bit field of a PCI configuration register.\r |
| 310 | \r |
| 311 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r |
| 312 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 313 | returned.\r |
| 314 | \r |
| 315 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 316 | If StartBit is greater than 7, then ASSERT().\r |
| 317 | If EndBit is greater than 7, then ASSERT().\r |
| 318 | If EndBit is less than StartBit, then ASSERT().\r |
| 319 | \r |
| 320 | @param Address PCI configuration register to read.\r |
| 321 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 322 | Range 0..7.\r |
| 323 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 324 | Range 0..7.\r |
| 325 | \r |
| 326 | @return The value of the bit field read from the PCI configuration register.\r |
| 327 | \r |
| 328 | **/\r |
| 329 | UINT8\r |
| 330 | EFIAPI\r |
| 331 | PciBitFieldRead8 (\r |
| 332 | IN UINTN Address,\r |
| 333 | IN UINTN StartBit,\r |
| 334 | IN UINTN EndBit\r |
| 335 | )\r |
| 336 | {\r |
| 337 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r |
| 338 | }\r |
| 339 | \r |
| 340 | /**\r |
| 341 | Writes a bit field to a PCI configuration register.\r |
| 342 | \r |
| 343 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 344 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 345 | destination PCI configuration register are preserved. The new value of the\r |
| 346 | 8-bit register is returned.\r |
| 347 | \r |
| 348 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 349 | If StartBit is greater than 7, then ASSERT().\r |
| 350 | If EndBit is greater than 7, then ASSERT().\r |
| 351 | If EndBit is less than StartBit, then ASSERT().\r |
| 352 | \r |
| 353 | @param Address PCI configuration register to write.\r |
| 354 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 355 | Range 0..7.\r |
| 356 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 357 | Range 0..7.\r |
| 358 | @param Value New value of the bit field.\r |
| 359 | \r |
| 360 | @return The value written back to the PCI configuration register.\r |
| 361 | \r |
| 362 | **/\r |
| 363 | UINT8\r |
| 364 | EFIAPI\r |
| 365 | PciBitFieldWrite8 (\r |
| 366 | IN UINTN Address,\r |
| 367 | IN UINTN StartBit,\r |
| 368 | IN UINTN EndBit,\r |
| 369 | IN UINT8 Value\r |
| 370 | )\r |
| 371 | {\r |
| 372 | return PciWrite8 (\r |
| 373 | Address,\r |
| 374 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r |
| 375 | );\r |
| 376 | }\r |
| 377 | \r |
| 378 | /**\r |
| 379 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r |
| 380 | writes the result back to the bit field in the 8-bit port.\r |
| 381 | \r |
| 382 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
383 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
384 | OrData, and writes the result to the 8-bit PCI configuration register\r |
| 385 | specified by Address. The value written to the PCI configuration register is\r |
| 386 | returned. This function must guarantee that all PCI read and write operations\r |
| 387 | are serialized. Extra left bits in OrData are stripped.\r |
| 388 | \r |
| 389 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 390 | If StartBit is greater than 7, then ASSERT().\r |
| 391 | If EndBit is greater than 7, then ASSERT().\r |
| 392 | If EndBit is less than StartBit, then ASSERT().\r |
| 393 | \r |
| 394 | @param Address PCI configuration register to write.\r |
| 395 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 396 | Range 0..7.\r |
| 397 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 398 | Range 0..7.\r |
| 399 | @param OrData The value to OR with the PCI configuration register.\r |
| 400 | \r |
| 401 | @return The value written back to the PCI configuration register.\r |
| 402 | \r |
| 403 | **/\r |
| 404 | UINT8\r |
| 405 | EFIAPI\r |
| 406 | PciBitFieldOr8 (\r |
| 407 | IN UINTN Address,\r |
| 408 | IN UINTN StartBit,\r |
| 409 | IN UINTN EndBit,\r |
| 410 | IN UINT8 OrData\r |
| 411 | )\r |
| 412 | {\r |
| 413 | return PciWrite8 (\r |
| 414 | Address,\r |
| 415 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r |
| 416 | );\r |
| 417 | }\r |
| 418 | \r |
| 419 | /**\r |
| 420 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r |
| 421 | AND, and writes the result back to the bit field in the 8-bit register.\r |
| 422 | \r |
| 423 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 424 | bitwise AND between the read result and the value specified by AndData, and\r |
| 425 | writes the result to the 8-bit PCI configuration register specified by\r |
| 426 | Address. The value written to the PCI configuration register is returned.\r |
| 427 | This function must guarantee that all PCI read and write operations are\r |
| 428 | serialized. Extra left bits in AndData are stripped.\r |
| 429 | \r |
| 430 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 431 | If StartBit is greater than 7, then ASSERT().\r |
| 432 | If EndBit is greater than 7, then ASSERT().\r |
| 433 | If EndBit is less than StartBit, then ASSERT().\r |
| 434 | \r |
| 435 | @param Address PCI configuration register to write.\r |
| 436 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 437 | Range 0..7.\r |
| 438 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 439 | Range 0..7.\r |
| 440 | @param AndData The value to AND with the PCI configuration register.\r |
| 441 | \r |
| 442 | @return The value written back to the PCI configuration register.\r |
| 443 | \r |
| 444 | **/\r |
| 445 | UINT8\r |
| 446 | EFIAPI\r |
| 447 | PciBitFieldAnd8 (\r |
| 448 | IN UINTN Address,\r |
| 449 | IN UINTN StartBit,\r |
| 450 | IN UINTN EndBit,\r |
| 451 | IN UINT8 AndData\r |
| 452 | )\r |
| 453 | {\r |
| 454 | return PciWrite8 (\r |
| 455 | Address,\r |
| 456 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r |
| 457 | );\r |
| 458 | }\r |
| 459 | \r |
| 460 | /**\r |
| 461 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
462 | bitwise OR, and writes the result back to the bit field in the\r |
| 1a3eaf06 |
463 | 8-bit port.\r |
| 464 | \r |
| 465 | Reads the 8-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
466 | bitwise AND followed by a bitwise OR between the read result and\r |
| 1a3eaf06 |
467 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
| 468 | configuration register specified by Address. The value written to the PCI\r |
| 469 | configuration register is returned. This function must guarantee that all PCI\r |
| 470 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 471 | OrData are stripped.\r |
| 472 | \r |
| 473 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 474 | If StartBit is greater than 7, then ASSERT().\r |
| 475 | If EndBit is greater than 7, then ASSERT().\r |
| 476 | If EndBit is less than StartBit, then ASSERT().\r |
| 477 | \r |
| 478 | @param Address PCI configuration register to write.\r |
| 479 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 480 | Range 0..7.\r |
| 481 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 482 | Range 0..7.\r |
| 483 | @param AndData The value to AND with the PCI configuration register.\r |
| 484 | @param OrData The value to OR with the result of the AND operation.\r |
| 485 | \r |
| 486 | @return The value written back to the PCI configuration register.\r |
| 487 | \r |
| 488 | **/\r |
| 489 | UINT8\r |
| 490 | EFIAPI\r |
| 491 | PciBitFieldAndThenOr8 (\r |
| 492 | IN UINTN Address,\r |
| 493 | IN UINTN StartBit,\r |
| 494 | IN UINTN EndBit,\r |
| 495 | IN UINT8 AndData,\r |
| 496 | IN UINT8 OrData\r |
| 497 | )\r |
| 498 | {\r |
| 499 | return PciWrite8 (\r |
| 500 | Address,\r |
| 501 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r |
| 502 | );\r |
| 503 | }\r |
| 504 | \r |
| 505 | /**\r |
| 506 | Reads a 16-bit PCI configuration register.\r |
| 507 | \r |
| 508 | Reads and returns the 16-bit PCI configuration register specified by Address.\r |
| 509 | This function must guarantee that all PCI read and write operations are\r |
| 510 | serialized.\r |
| 511 | \r |
| 512 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 513 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 514 | \r |
| 515 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 516 | Register.\r |
| 517 | \r |
| 9638ba6d |
518 | @return The read value from the PCI configuration register.\r |
| 1a3eaf06 |
519 | \r |
| 520 | **/\r |
| 521 | UINT16\r |
| 522 | EFIAPI\r |
| 523 | PciRead16 (\r |
| 524 | IN UINTN Address\r |
| 525 | )\r |
| 526 | {\r |
| 527 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 528 | \r |
| 529 | return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r |
| 530 | }\r |
| 531 | \r |
| 532 | /**\r |
| 533 | Writes a 16-bit PCI configuration register.\r |
| 534 | \r |
| 535 | Writes the 16-bit PCI configuration register specified by Address with the\r |
| 536 | value specified by Value. Value is returned. This function must guarantee\r |
| 537 | that all PCI read and write operations are serialized.\r |
| 538 | \r |
| 539 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 540 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 541 | \r |
| 542 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 543 | Register.\r |
| 9638ba6d |
544 | @param Value The value to write.\r |
| 1a3eaf06 |
545 | \r |
| 546 | @return The value written to the PCI configuration register.\r |
| 547 | \r |
| 548 | **/\r |
| 549 | UINT16\r |
| 550 | EFIAPI\r |
| 551 | PciWrite16 (\r |
| 552 | IN UINTN Address,\r |
| 0c3437e0 |
553 | IN UINT16 Value\r |
| 1a3eaf06 |
554 | )\r |
| 555 | {\r |
| 556 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r |
| 557 | \r |
| 0c3437e0 |
558 | return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
| 1a3eaf06 |
559 | }\r |
| 560 | \r |
| 561 | /**\r |
| 62991af2 |
562 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
| 1a3eaf06 |
563 | a 16-bit value.\r |
| 564 | \r |
| 565 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
566 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
567 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 568 | specified by Address. The value written to the PCI configuration register is\r |
| 569 | returned. This function must guarantee that all PCI read and write operations\r |
| 570 | are serialized.\r |
| 571 | \r |
| 572 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 573 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 574 | \r |
| 575 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 576 | Register.\r |
| 577 | @param OrData The value to OR with the PCI configuration register.\r |
| 578 | \r |
| 579 | @return The value written back to the PCI configuration register.\r |
| 580 | \r |
| 581 | **/\r |
| 582 | UINT16\r |
| 583 | EFIAPI\r |
| 584 | PciOr16 (\r |
| 585 | IN UINTN Address,\r |
| 586 | IN UINT16 OrData\r |
| 587 | )\r |
| 588 | {\r |
| 589 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r |
| 590 | }\r |
| 591 | \r |
| 592 | /**\r |
| 593 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 594 | value.\r |
| 595 | \r |
| 596 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 597 | bitwise AND between the read result and the value specified by AndData, and\r |
| 598 | writes the result to the 16-bit PCI configuration register specified by\r |
| 599 | Address. The value written to the PCI configuration register is returned.\r |
| 600 | This function must guarantee that all PCI read and write operations are\r |
| 601 | serialized.\r |
| 602 | \r |
| 603 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 604 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 605 | \r |
| 606 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 607 | Register.\r |
| 608 | @param AndData The value to AND with the PCI configuration register.\r |
| 609 | \r |
| 610 | @return The value written back to the PCI configuration register.\r |
| 611 | \r |
| 612 | **/\r |
| 613 | UINT16\r |
| 614 | EFIAPI\r |
| 615 | PciAnd16 (\r |
| 616 | IN UINTN Address,\r |
| 617 | IN UINT16 AndData\r |
| 618 | )\r |
| 619 | {\r |
| 620 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r |
| 621 | }\r |
| 622 | \r |
| 623 | /**\r |
| 624 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r |
| 62991af2 |
625 | value, followed a bitwise OR with another 16-bit value.\r |
| 1a3eaf06 |
626 | \r |
| 627 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 628 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
629 | performs a bitwise OR between the result of the AND operation and\r |
| 1a3eaf06 |
630 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
| 631 | configuration register specified by Address. The value written to the PCI\r |
| 632 | configuration register is returned. This function must guarantee that all PCI\r |
| 633 | read and write operations are serialized.\r |
| 634 | \r |
| 635 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 636 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 637 | \r |
| 638 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 639 | Register.\r |
| 640 | @param AndData The value to AND with the PCI configuration register.\r |
| 641 | @param OrData The value to OR with the result of the AND operation.\r |
| 642 | \r |
| 643 | @return The value written back to the PCI configuration register.\r |
| 644 | \r |
| 645 | **/\r |
| 646 | UINT16\r |
| 647 | EFIAPI\r |
| 648 | PciAndThenOr16 (\r |
| 649 | IN UINTN Address,\r |
| 650 | IN UINT16 AndData,\r |
| 651 | IN UINT16 OrData\r |
| 652 | )\r |
| 653 | {\r |
| 654 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r |
| 655 | }\r |
| 656 | \r |
| 657 | /**\r |
| 658 | Reads a bit field of a PCI configuration register.\r |
| 659 | \r |
| 660 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r |
| 661 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 662 | returned.\r |
| 663 | \r |
| 664 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 665 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 666 | If StartBit is greater than 15, then ASSERT().\r |
| 667 | If EndBit is greater than 15, then ASSERT().\r |
| 668 | If EndBit is less than StartBit, then ASSERT().\r |
| 669 | \r |
| 670 | @param Address PCI configuration register to read.\r |
| 671 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 672 | Range 0..15.\r |
| 673 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 674 | Range 0..15.\r |
| 675 | \r |
| 676 | @return The value of the bit field read from the PCI configuration register.\r |
| 677 | \r |
| 678 | **/\r |
| 679 | UINT16\r |
| 680 | EFIAPI\r |
| 681 | PciBitFieldRead16 (\r |
| 682 | IN UINTN Address,\r |
| 683 | IN UINTN StartBit,\r |
| 684 | IN UINTN EndBit\r |
| 685 | )\r |
| 686 | {\r |
| 687 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r |
| 688 | }\r |
| 689 | \r |
| 690 | /**\r |
| 691 | Writes a bit field to a PCI configuration register.\r |
| 692 | \r |
| 693 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 694 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 695 | destination PCI configuration register are preserved. The new value of the\r |
| 696 | 16-bit register is returned.\r |
| 697 | \r |
| 698 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 699 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 700 | If StartBit is greater than 15, then ASSERT().\r |
| 701 | If EndBit is greater than 15, then ASSERT().\r |
| 702 | If EndBit is less than StartBit, then ASSERT().\r |
| 703 | \r |
| 704 | @param Address PCI configuration register to write.\r |
| 705 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 706 | Range 0..15.\r |
| 707 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 708 | Range 0..15.\r |
| 709 | @param Value New value of the bit field.\r |
| 710 | \r |
| 711 | @return The value written back to the PCI configuration register.\r |
| 712 | \r |
| 713 | **/\r |
| 714 | UINT16\r |
| 715 | EFIAPI\r |
| 716 | PciBitFieldWrite16 (\r |
| 717 | IN UINTN Address,\r |
| 718 | IN UINTN StartBit,\r |
| 719 | IN UINTN EndBit,\r |
| 720 | IN UINT16 Value\r |
| 721 | )\r |
| 722 | {\r |
| 723 | return PciWrite16 (\r |
| 724 | Address,\r |
| 725 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r |
| 726 | );\r |
| 727 | }\r |
| 728 | \r |
| 729 | /**\r |
| 730 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r |
| 731 | writes the result back to the bit field in the 16-bit port.\r |
| 732 | \r |
| 733 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
734 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
735 | OrData, and writes the result to the 16-bit PCI configuration register\r |
| 736 | specified by Address. The value written to the PCI configuration register is\r |
| 737 | returned. This function must guarantee that all PCI read and write operations\r |
| 738 | are serialized. Extra left bits in OrData are stripped.\r |
| 739 | \r |
| 740 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 741 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 742 | If StartBit is greater than 15, then ASSERT().\r |
| 743 | If EndBit is greater than 15, then ASSERT().\r |
| 744 | If EndBit is less than StartBit, then ASSERT().\r |
| 745 | \r |
| 746 | @param Address PCI configuration register to write.\r |
| 747 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 748 | Range 0..15.\r |
| 749 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 750 | Range 0..15.\r |
| 751 | @param OrData The value to OR with the PCI configuration register.\r |
| 752 | \r |
| 753 | @return The value written back to the PCI configuration register.\r |
| 754 | \r |
| 755 | **/\r |
| 756 | UINT16\r |
| 757 | EFIAPI\r |
| 758 | PciBitFieldOr16 (\r |
| 759 | IN UINTN Address,\r |
| 760 | IN UINTN StartBit,\r |
| 761 | IN UINTN EndBit,\r |
| 762 | IN UINT16 OrData\r |
| 763 | )\r |
| 764 | {\r |
| 765 | return PciWrite16 (\r |
| 766 | Address,\r |
| 767 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r |
| 768 | );\r |
| 769 | }\r |
| 770 | \r |
| 771 | /**\r |
| 772 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r |
| 773 | AND, and writes the result back to the bit field in the 16-bit register.\r |
| 774 | \r |
| 775 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 776 | bitwise AND between the read result and the value specified by AndData, and\r |
| 777 | writes the result to the 16-bit PCI configuration register specified by\r |
| 778 | Address. The value written to the PCI configuration register is returned.\r |
| 779 | This function must guarantee that all PCI read and write operations are\r |
| 780 | serialized. Extra left bits in AndData are stripped.\r |
| 781 | \r |
| 782 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 783 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 784 | If StartBit is greater than 15, then ASSERT().\r |
| 785 | If EndBit is greater than 15, then ASSERT().\r |
| 786 | If EndBit is less than StartBit, then ASSERT().\r |
| 787 | \r |
| 788 | @param Address PCI configuration register to write.\r |
| 789 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 790 | Range 0..15.\r |
| 791 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 792 | Range 0..15.\r |
| 793 | @param AndData The value to AND with the PCI configuration register.\r |
| 794 | \r |
| 795 | @return The value written back to the PCI configuration register.\r |
| 796 | \r |
| 797 | **/\r |
| 798 | UINT16\r |
| 799 | EFIAPI\r |
| 800 | PciBitFieldAnd16 (\r |
| 801 | IN UINTN Address,\r |
| 802 | IN UINTN StartBit,\r |
| 803 | IN UINTN EndBit,\r |
| 804 | IN UINT16 AndData\r |
| 805 | )\r |
| 806 | {\r |
| 807 | return PciWrite16 (\r |
| 808 | Address,\r |
| 809 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r |
| 810 | );\r |
| 811 | }\r |
| 812 | \r |
| 813 | /**\r |
| 814 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
815 | bitwise OR, and writes the result back to the bit field in the\r |
| 1a3eaf06 |
816 | 16-bit port.\r |
| 817 | \r |
| 818 | Reads the 16-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
819 | bitwise AND followed by a bitwise OR between the read result and\r |
| 1a3eaf06 |
820 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
| 821 | configuration register specified by Address. The value written to the PCI\r |
| 822 | configuration register is returned. This function must guarantee that all PCI\r |
| 823 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 824 | OrData are stripped.\r |
| 825 | \r |
| 826 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 827 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
| 828 | If StartBit is greater than 15, then ASSERT().\r |
| 829 | If EndBit is greater than 15, then ASSERT().\r |
| 830 | If EndBit is less than StartBit, then ASSERT().\r |
| 831 | \r |
| 832 | @param Address PCI configuration register to write.\r |
| 833 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 834 | Range 0..15.\r |
| 835 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 836 | Range 0..15.\r |
| 837 | @param AndData The value to AND with the PCI configuration register.\r |
| 838 | @param OrData The value to OR with the result of the AND operation.\r |
| 839 | \r |
| 840 | @return The value written back to the PCI configuration register.\r |
| 841 | \r |
| 842 | **/\r |
| 843 | UINT16\r |
| 844 | EFIAPI\r |
| 845 | PciBitFieldAndThenOr16 (\r |
| 846 | IN UINTN Address,\r |
| 847 | IN UINTN StartBit,\r |
| 848 | IN UINTN EndBit,\r |
| 849 | IN UINT16 AndData,\r |
| 850 | IN UINT16 OrData\r |
| 851 | )\r |
| 852 | {\r |
| 853 | return PciWrite16 (\r |
| 854 | Address,\r |
| 855 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r |
| 856 | );\r |
| 857 | }\r |
| 858 | \r |
| 859 | /**\r |
| 860 | Reads a 32-bit PCI configuration register.\r |
| 861 | \r |
| 862 | Reads and returns the 32-bit PCI configuration register specified by Address.\r |
| 863 | This function must guarantee that all PCI read and write operations are\r |
| 864 | serialized.\r |
| 865 | \r |
| 866 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 867 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 868 | \r |
| 869 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 870 | Register.\r |
| 871 | \r |
| 9638ba6d |
872 | @return The read value from the PCI configuration register.\r |
| 1a3eaf06 |
873 | \r |
| 874 | **/\r |
| 875 | UINT32\r |
| 876 | EFIAPI\r |
| 877 | PciRead32 (\r |
| 878 | IN UINTN Address\r |
| 879 | )\r |
| 880 | {\r |
| 881 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 882 | \r |
| 883 | return PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r |
| 884 | }\r |
| 885 | \r |
| 886 | /**\r |
| 887 | Writes a 32-bit PCI configuration register.\r |
| 888 | \r |
| 889 | Writes the 32-bit PCI configuration register specified by Address with the\r |
| 890 | value specified by Value. Value is returned. This function must guarantee\r |
| 891 | that all PCI read and write operations are serialized.\r |
| 892 | \r |
| 893 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 894 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 895 | \r |
| 896 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 897 | Register.\r |
| 9638ba6d |
898 | @param Value The value to write.\r |
| 1a3eaf06 |
899 | \r |
| 900 | @return The value written to the PCI configuration register.\r |
| 901 | \r |
| 902 | **/\r |
| 903 | UINT32\r |
| 904 | EFIAPI\r |
| 905 | PciWrite32 (\r |
| 906 | IN UINTN Address,\r |
| 0c3437e0 |
907 | IN UINT32 Value\r |
| 1a3eaf06 |
908 | )\r |
| 909 | {\r |
| 910 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r |
| 911 | \r |
| 0c3437e0 |
912 | return PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
| 1a3eaf06 |
913 | }\r |
| 914 | \r |
| 915 | /**\r |
| 62991af2 |
916 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
| 1a3eaf06 |
917 | a 32-bit value.\r |
| 918 | \r |
| 919 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
920 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
921 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 922 | specified by Address. The value written to the PCI configuration register is\r |
| 923 | returned. This function must guarantee that all PCI read and write operations\r |
| 924 | are serialized.\r |
| 925 | \r |
| 926 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 927 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 928 | \r |
| 929 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 930 | Register.\r |
| 931 | @param OrData The value to OR with the PCI configuration register.\r |
| 932 | \r |
| 933 | @return The value written back to the PCI configuration register.\r |
| 934 | \r |
| 935 | **/\r |
| 936 | UINT32\r |
| 937 | EFIAPI\r |
| 938 | PciOr32 (\r |
| 939 | IN UINTN Address,\r |
| 940 | IN UINT32 OrData\r |
| 941 | )\r |
| 942 | {\r |
| 943 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r |
| 944 | }\r |
| 945 | \r |
| 946 | /**\r |
| 947 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 948 | value.\r |
| 949 | \r |
| 950 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 951 | bitwise AND between the read result and the value specified by AndData, and\r |
| 952 | writes the result to the 32-bit PCI configuration register specified by\r |
| 953 | Address. The value written to the PCI configuration register is returned.\r |
| 954 | This function must guarantee that all PCI read and write operations are\r |
| 955 | serialized.\r |
| 956 | \r |
| 957 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 958 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 959 | \r |
| 960 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 961 | Register.\r |
| 962 | @param AndData The value to AND with the PCI configuration register.\r |
| 963 | \r |
| 964 | @return The value written back to the PCI configuration register.\r |
| 965 | \r |
| 966 | **/\r |
| 967 | UINT32\r |
| 968 | EFIAPI\r |
| 969 | PciAnd32 (\r |
| 970 | IN UINTN Address,\r |
| 971 | IN UINT32 AndData\r |
| 972 | )\r |
| 973 | {\r |
| 974 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r |
| 975 | }\r |
| 976 | \r |
| 977 | /**\r |
| 978 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r |
| 62991af2 |
979 | value, followed a bitwise OR with another 32-bit value.\r |
| 1a3eaf06 |
980 | \r |
| 981 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 982 | bitwise AND between the read result and the value specified by AndData,\r |
| 62991af2 |
983 | performs a bitwise OR between the result of the AND operation and\r |
| 1a3eaf06 |
984 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
| 985 | configuration register specified by Address. The value written to the PCI\r |
| 986 | configuration register is returned. This function must guarantee that all PCI\r |
| 987 | read and write operations are serialized.\r |
| 988 | \r |
| 989 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 990 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 991 | \r |
| 992 | @param Address Address that encodes the PCI Bus, Device, Function and\r |
| 993 | Register.\r |
| 994 | @param AndData The value to AND with the PCI configuration register.\r |
| 995 | @param OrData The value to OR with the result of the AND operation.\r |
| 996 | \r |
| 997 | @return The value written back to the PCI configuration register.\r |
| 998 | \r |
| 999 | **/\r |
| 1000 | UINT32\r |
| 1001 | EFIAPI\r |
| 1002 | PciAndThenOr32 (\r |
| 1003 | IN UINTN Address,\r |
| 1004 | IN UINT32 AndData,\r |
| 1005 | IN UINT32 OrData\r |
| 1006 | )\r |
| 1007 | {\r |
| 1008 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r |
| 1009 | }\r |
| 1010 | \r |
| 1011 | /**\r |
| 1012 | Reads a bit field of a PCI configuration register.\r |
| 1013 | \r |
| 1014 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r |
| 1015 | specified by the StartBit and the EndBit. The value of the bit field is\r |
| 1016 | returned.\r |
| 1017 | \r |
| 1018 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1019 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1020 | If StartBit is greater than 31, then ASSERT().\r |
| 1021 | If EndBit is greater than 31, then ASSERT().\r |
| 1022 | If EndBit is less than StartBit, then ASSERT().\r |
| 1023 | \r |
| 1024 | @param Address PCI configuration register to read.\r |
| 1025 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1026 | Range 0..31.\r |
| 1027 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1028 | Range 0..31.\r |
| 1029 | \r |
| 1030 | @return The value of the bit field read from the PCI configuration register.\r |
| 1031 | \r |
| 1032 | **/\r |
| 1033 | UINT32\r |
| 1034 | EFIAPI\r |
| 1035 | PciBitFieldRead32 (\r |
| 1036 | IN UINTN Address,\r |
| 1037 | IN UINTN StartBit,\r |
| 1038 | IN UINTN EndBit\r |
| 1039 | )\r |
| 1040 | {\r |
| 1041 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r |
| 1042 | }\r |
| 1043 | \r |
| 1044 | /**\r |
| 1045 | Writes a bit field to a PCI configuration register.\r |
| 1046 | \r |
| 1047 | Writes Value to the bit field of the PCI configuration register. The bit\r |
| 1048 | field is specified by the StartBit and the EndBit. All other bits in the\r |
| 1049 | destination PCI configuration register are preserved. The new value of the\r |
| 1050 | 32-bit register is returned.\r |
| 1051 | \r |
| 1052 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1053 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1054 | If StartBit is greater than 31, then ASSERT().\r |
| 1055 | If EndBit is greater than 31, then ASSERT().\r |
| 1056 | If EndBit is less than StartBit, then ASSERT().\r |
| 1057 | \r |
| 1058 | @param Address PCI configuration register to write.\r |
| 1059 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1060 | Range 0..31.\r |
| 1061 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1062 | Range 0..31.\r |
| 1063 | @param Value New value of the bit field.\r |
| 1064 | \r |
| 1065 | @return The value written back to the PCI configuration register.\r |
| 1066 | \r |
| 1067 | **/\r |
| 1068 | UINT32\r |
| 1069 | EFIAPI\r |
| 1070 | PciBitFieldWrite32 (\r |
| 1071 | IN UINTN Address,\r |
| 1072 | IN UINTN StartBit,\r |
| 1073 | IN UINTN EndBit,\r |
| 1074 | IN UINT32 Value\r |
| 1075 | )\r |
| 1076 | {\r |
| 1077 | return PciWrite32 (\r |
| 1078 | Address,\r |
| 1079 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r |
| 1080 | );\r |
| 1081 | }\r |
| 1082 | \r |
| 1083 | /**\r |
| 1084 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r |
| 1085 | writes the result back to the bit field in the 32-bit port.\r |
| 1086 | \r |
| 1087 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
1088 | bitwise OR between the read result and the value specified by\r |
| 1a3eaf06 |
1089 | OrData, and writes the result to the 32-bit PCI configuration register\r |
| 1090 | specified by Address. The value written to the PCI configuration register is\r |
| 1091 | returned. This function must guarantee that all PCI read and write operations\r |
| 1092 | are serialized. Extra left bits in OrData are stripped.\r |
| 1093 | \r |
| 1094 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1095 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1096 | If StartBit is greater than 31, then ASSERT().\r |
| 1097 | If EndBit is greater than 31, then ASSERT().\r |
| 1098 | If EndBit is less than StartBit, then ASSERT().\r |
| 1099 | \r |
| 1100 | @param Address PCI configuration register to write.\r |
| 1101 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1102 | Range 0..31.\r |
| 1103 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1104 | Range 0..31.\r |
| 1105 | @param OrData The value to OR with the PCI configuration register.\r |
| 1106 | \r |
| 1107 | @return The value written back to the PCI configuration register.\r |
| 1108 | \r |
| 1109 | **/\r |
| 1110 | UINT32\r |
| 1111 | EFIAPI\r |
| 1112 | PciBitFieldOr32 (\r |
| 1113 | IN UINTN Address,\r |
| 1114 | IN UINTN StartBit,\r |
| 1115 | IN UINTN EndBit,\r |
| 1116 | IN UINT32 OrData\r |
| 1117 | )\r |
| 1118 | {\r |
| 1119 | return PciWrite32 (\r |
| 1120 | Address,\r |
| 1121 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r |
| 1122 | );\r |
| 1123 | }\r |
| 1124 | \r |
| 1125 | /**\r |
| 1126 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r |
| 1127 | AND, and writes the result back to the bit field in the 32-bit register.\r |
| 1128 | \r |
| 1129 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 1130 | bitwise AND between the read result and the value specified by AndData, and\r |
| 1131 | writes the result to the 32-bit PCI configuration register specified by\r |
| 1132 | Address. The value written to the PCI configuration register is returned.\r |
| 1133 | This function must guarantee that all PCI read and write operations are\r |
| 1134 | serialized. Extra left bits in AndData are stripped.\r |
| 1135 | \r |
| 1136 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1137 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1138 | If StartBit is greater than 31, then ASSERT().\r |
| 1139 | If EndBit is greater than 31, then ASSERT().\r |
| 1140 | If EndBit is less than StartBit, then ASSERT().\r |
| 1141 | \r |
| 1142 | @param Address PCI configuration register to write.\r |
| 1143 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1144 | Range 0..31.\r |
| 1145 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1146 | Range 0..31.\r |
| 1147 | @param AndData The value to AND with the PCI configuration register.\r |
| 1148 | \r |
| 1149 | @return The value written back to the PCI configuration register.\r |
| 1150 | \r |
| 1151 | **/\r |
| 1152 | UINT32\r |
| 1153 | EFIAPI\r |
| 1154 | PciBitFieldAnd32 (\r |
| 1155 | IN UINTN Address,\r |
| 1156 | IN UINTN StartBit,\r |
| 1157 | IN UINTN EndBit,\r |
| 1158 | IN UINT32 AndData\r |
| 1159 | )\r |
| 1160 | {\r |
| 1161 | return PciWrite32 (\r |
| 1162 | Address,\r |
| 1163 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r |
| 1164 | );\r |
| 1165 | }\r |
| 1166 | \r |
| 1167 | /**\r |
| 1168 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r |
| 62991af2 |
1169 | bitwise OR, and writes the result back to the bit field in the\r |
| 1a3eaf06 |
1170 | 32-bit port.\r |
| 1171 | \r |
| 1172 | Reads the 32-bit PCI configuration register specified by Address, performs a\r |
| 62991af2 |
1173 | bitwise AND followed by a bitwise OR between the read result and\r |
| 1a3eaf06 |
1174 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
| 1175 | configuration register specified by Address. The value written to the PCI\r |
| 1176 | configuration register is returned. This function must guarantee that all PCI\r |
| 1177 | read and write operations are serialized. Extra left bits in both AndData and\r |
| 1178 | OrData are stripped.\r |
| 1179 | \r |
| 1180 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 1181 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
| 1182 | If StartBit is greater than 31, then ASSERT().\r |
| 1183 | If EndBit is greater than 31, then ASSERT().\r |
| 1184 | If EndBit is less than StartBit, then ASSERT().\r |
| 1185 | \r |
| 1186 | @param Address PCI configuration register to write.\r |
| 1187 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
| 1188 | Range 0..31.\r |
| 1189 | @param EndBit The ordinal of the most significant bit in the bit field.\r |
| 1190 | Range 0..31.\r |
| 1191 | @param AndData The value to AND with the PCI configuration register.\r |
| 1192 | @param OrData The value to OR with the result of the AND operation.\r |
| 1193 | \r |
| 1194 | @return The value written back to the PCI configuration register.\r |
| 1195 | \r |
| 1196 | **/\r |
| 1197 | UINT32\r |
| 1198 | EFIAPI\r |
| 1199 | PciBitFieldAndThenOr32 (\r |
| 1200 | IN UINTN Address,\r |
| 1201 | IN UINTN StartBit,\r |
| 1202 | IN UINTN EndBit,\r |
| 1203 | IN UINT32 AndData,\r |
| 1204 | IN UINT32 OrData\r |
| 1205 | )\r |
| 1206 | {\r |
| 1207 | return PciWrite32 (\r |
| 1208 | Address,\r |
| 1209 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r |
| 1210 | );\r |
| 1211 | }\r |
| 1212 | \r |
| 1213 | /**\r |
| 1214 | Reads a range of PCI configuration registers into a caller supplied buffer.\r |
| 1215 | \r |
| 1216 | Reads the range of PCI configuration registers specified by StartAddress and\r |
| 1217 | Size into the buffer specified by Buffer. This function only allows the PCI\r |
| 1218 | configuration registers from a single PCI function to be read. Size is\r |
| 1219 | returned. When possible 32-bit PCI configuration read cycles are used to read\r |
| 1220 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 1221 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1222 | end of the range.\r |
| 1223 | \r |
| 1224 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1225 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1226 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1227 | \r |
| 1228 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1229 | Function and Register.\r |
| 1230 | @param Size Size in bytes of the transfer.\r |
| 1231 | @param Buffer Pointer to a buffer receiving the data read.\r |
| 1232 | \r |
| 1233 | @return Size\r |
| 1234 | \r |
| 1235 | **/\r |
| 1236 | UINTN\r |
| 1237 | EFIAPI\r |
| 1238 | PciReadBuffer (\r |
| 1239 | IN UINTN StartAddress,\r |
| 1240 | IN UINTN Size,\r |
| 1241 | OUT VOID *Buffer\r |
| 1242 | )\r |
| 1243 | {\r |
| 1244 | UINTN ReturnValue;\r |
| 1245 | \r |
| 1246 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r |
| e43e4b3e |
1247 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1a3eaf06 |
1248 | \r |
| 1249 | if (Size == 0) {\r |
| 1250 | return Size;\r |
| 1251 | }\r |
| 1252 | \r |
| 1253 | ASSERT (Buffer != NULL);\r |
| 1254 | \r |
| 1255 | //\r |
| 1256 | // Save Size for return\r |
| 1257 | //\r |
| 1258 | ReturnValue = Size;\r |
| 1259 | \r |
| e43e4b3e |
1260 | if ((StartAddress & BIT0) != 0) {\r |
| 1a3eaf06 |
1261 | //\r |
| 1262 | // Read a byte if StartAddress is byte aligned\r |
| 1263 | //\r |
| 1264 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r |
| 1265 | StartAddress += sizeof (UINT8);\r |
| 1266 | Size -= sizeof (UINT8);\r |
| 1267 | Buffer = (UINT8*)Buffer + 1;\r |
| 1268 | }\r |
| 1269 | \r |
| e43e4b3e |
1270 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
| 1a3eaf06 |
1271 | //\r |
| 1272 | // Read a word if StartAddress is word aligned\r |
| 1273 | //\r |
| 1274 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r |
| 1275 | StartAddress += sizeof (UINT16);\r |
| 1276 | Size -= sizeof (UINT16);\r |
| 1277 | Buffer = (UINT16*)Buffer + 1;\r |
| 1278 | }\r |
| 1279 | \r |
| 1280 | while (Size >= sizeof (UINT32)) {\r |
| 1281 | //\r |
| 1282 | // Read as many double words as possible\r |
| 1283 | //\r |
| 1284 | *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);\r |
| 1285 | StartAddress += sizeof (UINT32);\r |
| 1286 | Size -= sizeof (UINT32);\r |
| 1287 | Buffer = (UINT32*)Buffer + 1;\r |
| 1288 | }\r |
| 1289 | \r |
| 1290 | if (Size >= sizeof (UINT16)) {\r |
| 1291 | //\r |
| 1292 | // Read the last remaining word if exist\r |
| 1293 | //\r |
| 1294 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r |
| 1295 | StartAddress += sizeof (UINT16);\r |
| 1296 | Size -= sizeof (UINT16);\r |
| 1297 | Buffer = (UINT16*)Buffer + 1;\r |
| 1298 | }\r |
| 1299 | \r |
| 1300 | if (Size >= sizeof (UINT8)) {\r |
| 1301 | //\r |
| 1302 | // Read the last remaining byte if exist\r |
| 1303 | //\r |
| 1304 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r |
| 1305 | }\r |
| 1306 | \r |
| 1307 | return ReturnValue;\r |
| 1308 | }\r |
| 1309 | \r |
| 1310 | /**\r |
| 1311 | Copies the data in a caller supplied buffer to a specified range of PCI\r |
| 1312 | configuration space.\r |
| 1313 | \r |
| 1314 | Writes the range of PCI configuration registers specified by StartAddress and\r |
| 1315 | Size from the buffer specified by Buffer. This function only allows the PCI\r |
| 1316 | configuration registers from a single PCI function to be written. Size is\r |
| 1317 | returned. When possible 32-bit PCI configuration write cycles are used to\r |
| 1318 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r |
| 1319 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1320 | and the end of the range.\r |
| 1321 | \r |
| 1322 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r |
| 1323 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r |
| 1324 | If Size > 0 and Buffer is NULL, then ASSERT().\r |
| 1325 | \r |
| 1326 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r |
| 1327 | Function and Register.\r |
| 1328 | @param Size Size in bytes of the transfer.\r |
| 1329 | @param Buffer Pointer to a buffer containing the data to write.\r |
| 1330 | \r |
| 0c3437e0 |
1331 | @return Size written to StartAddress.\r |
| 1a3eaf06 |
1332 | \r |
| 1333 | **/\r |
| 1334 | UINTN\r |
| 1335 | EFIAPI\r |
| 1336 | PciWriteBuffer (\r |
| 1337 | IN UINTN StartAddress,\r |
| 1338 | IN UINTN Size,\r |
| 1339 | IN VOID *Buffer\r |
| 1340 | )\r |
| 1341 | {\r |
| 1342 | UINTN ReturnValue;\r |
| 1343 | \r |
| 1344 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r |
| e43e4b3e |
1345 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
| 1a3eaf06 |
1346 | \r |
| 1347 | if (Size == 0) {\r |
| 1348 | return 0;\r |
| 1349 | }\r |
| 1350 | \r |
| 1351 | ASSERT (Buffer != NULL);\r |
| 1352 | \r |
| 1353 | //\r |
| 1354 | // Save Size for return\r |
| 1355 | //\r |
| 1356 | ReturnValue = Size;\r |
| 1357 | \r |
| e43e4b3e |
1358 | if ((StartAddress & BIT0) != 0) {\r |
| 1a3eaf06 |
1359 | //\r |
| 1360 | // Write a byte if StartAddress is byte aligned\r |
| 1361 | //\r |
| 1362 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1363 | StartAddress += sizeof (UINT8);\r |
| 1364 | Size -= sizeof (UINT8);\r |
| 1365 | Buffer = (UINT8*)Buffer + 1;\r |
| 1366 | }\r |
| 1367 | \r |
| e43e4b3e |
1368 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
| 1a3eaf06 |
1369 | //\r |
| 1370 | // Write a word if StartAddress is word aligned\r |
| 1371 | //\r |
| 1372 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r |
| 1373 | StartAddress += sizeof (UINT16);\r |
| 1374 | Size -= sizeof (UINT16);\r |
| 1375 | Buffer = (UINT16*)Buffer + 1;\r |
| 1376 | }\r |
| 1377 | \r |
| 1378 | while (Size >= sizeof (UINT32)) {\r |
| 1379 | //\r |
| 1380 | // Write as many double words as possible\r |
| 1381 | //\r |
| 1382 | PciWrite32 (StartAddress, *(UINT32*)Buffer);\r |
| 1383 | StartAddress += sizeof (UINT32);\r |
| 1384 | Size -= sizeof (UINT32);\r |
| 1385 | Buffer = (UINT32*)Buffer + 1;\r |
| 1386 | }\r |
| 1387 | \r |
| 1388 | if (Size >= sizeof (UINT16)) {\r |
| 1389 | //\r |
| 1390 | // Write the last remaining word if exist\r |
| 1391 | //\r |
| 1392 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r |
| 1393 | StartAddress += sizeof (UINT16);\r |
| 1394 | Size -= sizeof (UINT16);\r |
| 1395 | Buffer = (UINT16*)Buffer + 1;\r |
| 1396 | }\r |
| 1397 | \r |
| 1398 | if (Size >= sizeof (UINT8)) {\r |
| 1399 | //\r |
| 1400 | // Write the last remaining byte if exist\r |
| 1401 | //\r |
| 1402 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r |
| 1403 | }\r |
| 1404 | \r |
| 1405 | return ReturnValue;\r |
| 1406 | }\r |
projects / mirror_edk2.git / blame