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1a3eaf06 | 1 | /** @file\r |
2 | PCI Library using PCI CFG2 PPI.\r | |
3 | \r | |
9095d37b | 4 | Copyright (c) 2007 - 2018, Intel Corporation. All rights reserved.<BR>\r |
9344f092 | 5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
1a3eaf06 | 6 | \r |
7 | **/\r | |
8 | \r | |
9 | #include <PiPei.h>\r | |
10 | \r | |
11 | #include <Ppi/PciCfg2.h>\r | |
12 | \r | |
13 | #include <Library/PciLib.h>\r | |
14 | #include <Library/BaseLib.h>\r | |
15 | #include <Library/PeiServicesTablePointerLib.h>\r | |
16 | #include <Library/DebugLib.h>\r | |
17 | #include <Library/PeiServicesLib.h>\r | |
18 | \r | |
19 | /**\r | |
20 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
21 | only in the low 28 bits.\r | |
22 | \r | |
23 | @param A The address to validate.\r | |
24 | @param M Additional bits to assert to be zero.\r | |
25 | \r | |
26 | **/\r | |
27 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
28 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
29 | \r | |
30 | /**\r | |
31 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
32 | \r | |
2fc59a00 | 33 | @param A The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 34 | Register.\r |
35 | \r | |
36 | **/\r | |
37 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
e43e4b3e | 38 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 39 | \r |
40 | /**\r | |
41 | Internal worker function to read a PCI configuration register.\r | |
42 | \r | |
43 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
44 | It reads and returns the PCI configuration register specified by Address,\r | |
45 | the width of data is specified by Width.\r | |
46 | \r | |
2fc59a00 | 47 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 48 | Register.\r |
58380e9c | 49 | @param Width The width of data to read\r |
1a3eaf06 | 50 | \r |
51 | @return The value read from the PCI configuration register.\r | |
52 | \r | |
53 | **/\r | |
54 | UINT32\r | |
55 | PeiPciLibPciCfg2ReadWorker (\r | |
56 | IN UINTN Address,\r | |
57 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
58 | )\r | |
59 | {\r | |
60 | EFI_STATUS Status;\r | |
61 | UINT32 Data;\r | |
62 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 63 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 64 | \r |
65 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
66 | ASSERT_EFI_ERROR (Status);\r | |
67 | ASSERT (PciCfg2Ppi != NULL);\r | |
68 | \r | |
43fe5cdc | 69 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 70 | PciCfg2Ppi->Read (\r |
71 | GetPeiServicesTablePointer (),\r | |
72 | PciCfg2Ppi,\r | |
73 | Width,\r | |
43fe5cdc | 74 | PciCfg2Address,\r |
1a3eaf06 | 75 | &Data\r |
76 | );\r | |
77 | \r | |
78 | return Data;\r | |
79 | }\r | |
80 | \r | |
81 | /**\r | |
82 | Internal worker function to writes a PCI configuration register.\r | |
83 | \r | |
84 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
85 | It writes the PCI configuration register specified by Address with the\r | |
a750b4ae | 86 | value specified by Data. The width of data is specified by Width.\r |
1a3eaf06 | 87 | Data is returned.\r |
88 | \r | |
2fc59a00 | 89 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 90 | Register.\r |
58380e9c | 91 | @param Width The width of data to write\r |
1a3eaf06 | 92 | @param Data The value to write.\r |
93 | \r | |
94 | @return The value written to the PCI configuration register.\r | |
95 | \r | |
96 | **/\r | |
97 | UINT32\r | |
98 | PeiPciLibPciCfg2WriteWorker (\r | |
99 | IN UINTN Address,\r | |
100 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
101 | IN UINT32 Data\r | |
102 | )\r | |
103 | {\r | |
104 | EFI_STATUS Status;\r | |
105 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 106 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 107 | \r |
108 | Status = PeiServicesLocatePpi (&gEfiPciCfg2PpiGuid, 0, NULL, (VOID **) &PciCfg2Ppi);\r | |
109 | ASSERT_EFI_ERROR (Status);\r | |
110 | ASSERT (PciCfg2Ppi != NULL);\r | |
111 | \r | |
43fe5cdc | 112 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 113 | PciCfg2Ppi->Write (\r |
114 | GetPeiServicesTablePointer (),\r | |
115 | PciCfg2Ppi,\r | |
116 | Width,\r | |
43fe5cdc | 117 | PciCfg2Address,\r |
1a3eaf06 | 118 | &Data\r |
119 | );\r | |
120 | \r | |
121 | return Data;\r | |
122 | }\r | |
123 | \r | |
3e3ae634 | 124 | /**\r |
9095d37b | 125 | Registers a PCI device so PCI configuration registers may be accessed after\r |
3e3ae634 | 126 | SetVirtualAddressMap().\r |
9095d37b LG |
127 | \r |
128 | Registers the PCI device specified by Address so all the PCI configuration registers\r | |
d11195a3 | 129 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
9095d37b | 130 | \r |
3e3ae634 | 131 | If Address > 0x0FFFFFFF, then ASSERT().\r |
132 | \r | |
2fc59a00 | 133 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
3e3ae634 | 134 | Register.\r |
9095d37b | 135 | \r |
3e3ae634 | 136 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
9095d37b | 137 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
3e3ae634 | 138 | after ExitBootServices().\r |
139 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
140 | at runtime could not be mapped.\r | |
141 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
142 | complete the registration.\r | |
143 | \r | |
144 | **/\r | |
145 | RETURN_STATUS\r | |
146 | EFIAPI\r | |
147 | PciRegisterForRuntimeAccess (\r | |
148 | IN UINTN Address\r | |
149 | )\r | |
150 | {\r | |
59ceeabe | 151 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r |
3e3ae634 | 152 | return RETURN_UNSUPPORTED;\r |
153 | }\r | |
154 | \r | |
1a3eaf06 | 155 | /**\r |
156 | Reads an 8-bit PCI configuration register.\r | |
157 | \r | |
158 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
159 | This function must guarantee that all PCI read and write operations are\r | |
160 | serialized.\r | |
161 | \r | |
162 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
163 | \r | |
2fc59a00 | 164 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 165 | Register.\r |
166 | \r | |
0c3437e0 | 167 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 168 | \r |
169 | **/\r | |
170 | UINT8\r | |
171 | EFIAPI\r | |
172 | PciRead8 (\r | |
173 | IN UINTN Address\r | |
174 | )\r | |
175 | {\r | |
176 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
177 | \r | |
178 | return (UINT8) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
179 | }\r | |
180 | \r | |
181 | /**\r | |
182 | Writes an 8-bit PCI configuration register.\r | |
183 | \r | |
184 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
185 | value specified by Value. Value is returned. This function must guarantee\r | |
186 | that all PCI read and write operations are serialized.\r | |
187 | \r | |
188 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
189 | \r | |
2fc59a00 | 190 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 191 | Register.\r |
0c3437e0 | 192 | @param Value The value to write.\r |
1a3eaf06 | 193 | \r |
194 | @return The value written to the PCI configuration register.\r | |
195 | \r | |
196 | **/\r | |
197 | UINT8\r | |
198 | EFIAPI\r | |
199 | PciWrite8 (\r | |
200 | IN UINTN Address,\r | |
0c3437e0 | 201 | IN UINT8 Value\r |
1a3eaf06 | 202 | )\r |
203 | {\r | |
204 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
205 | \r | |
0c3437e0 | 206 | return (UINT8) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Value);\r |
1a3eaf06 | 207 | }\r |
208 | \r | |
209 | /**\r | |
62991af2 | 210 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
1a3eaf06 | 211 | an 8-bit value.\r |
212 | \r | |
213 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 214 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 215 | OrData, and writes the result to the 8-bit PCI configuration register\r |
216 | specified by Address. The value written to the PCI configuration register is\r | |
217 | returned. This function must guarantee that all PCI read and write operations\r | |
218 | are serialized.\r | |
219 | \r | |
220 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
221 | \r | |
2fc59a00 | 222 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 223 | Register.\r |
224 | @param OrData The value to OR with the PCI configuration register.\r | |
225 | \r | |
226 | @return The value written back to the PCI configuration register.\r | |
227 | \r | |
228 | **/\r | |
229 | UINT8\r | |
230 | EFIAPI\r | |
231 | PciOr8 (\r | |
232 | IN UINTN Address,\r | |
233 | IN UINT8 OrData\r | |
234 | )\r | |
235 | {\r | |
236 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r | |
237 | }\r | |
238 | \r | |
239 | /**\r | |
240 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
241 | value.\r | |
242 | \r | |
243 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
244 | bitwise AND between the read result and the value specified by AndData, and\r | |
245 | writes the result to the 8-bit PCI configuration register specified by\r | |
246 | Address. The value written to the PCI configuration register is returned.\r | |
247 | This function must guarantee that all PCI read and write operations are\r | |
248 | serialized.\r | |
249 | \r | |
250 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
251 | \r | |
2fc59a00 | 252 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 253 | Register.\r |
254 | @param AndData The value to AND with the PCI configuration register.\r | |
255 | \r | |
256 | @return The value written back to the PCI configuration register.\r | |
257 | \r | |
258 | **/\r | |
259 | UINT8\r | |
260 | EFIAPI\r | |
261 | PciAnd8 (\r | |
262 | IN UINTN Address,\r | |
263 | IN UINT8 AndData\r | |
264 | )\r | |
265 | {\r | |
266 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r | |
267 | }\r | |
268 | \r | |
269 | /**\r | |
270 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 271 | value, followed a bitwise OR with another 8-bit value.\r |
1a3eaf06 | 272 | \r |
273 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
274 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 275 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 276 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
277 | configuration register specified by Address. The value written to the PCI\r | |
278 | configuration register is returned. This function must guarantee that all PCI\r | |
279 | read and write operations are serialized.\r | |
280 | \r | |
281 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
282 | \r | |
2fc59a00 | 283 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 284 | Register.\r |
285 | @param AndData The value to AND with the PCI configuration register.\r | |
286 | @param OrData The value to OR with the result of the AND operation.\r | |
287 | \r | |
288 | @return The value written back to the PCI configuration register.\r | |
289 | \r | |
290 | **/\r | |
291 | UINT8\r | |
292 | EFIAPI\r | |
293 | PciAndThenOr8 (\r | |
294 | IN UINTN Address,\r | |
295 | IN UINT8 AndData,\r | |
296 | IN UINT8 OrData\r | |
297 | )\r | |
298 | {\r | |
299 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r | |
300 | }\r | |
301 | \r | |
302 | /**\r | |
303 | Reads a bit field of a PCI configuration register.\r | |
304 | \r | |
305 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
306 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
307 | returned.\r | |
308 | \r | |
309 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
310 | If StartBit is greater than 7, then ASSERT().\r | |
311 | If EndBit is greater than 7, then ASSERT().\r | |
312 | If EndBit is less than StartBit, then ASSERT().\r | |
313 | \r | |
2fc59a00 | 314 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 315 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
316 | Range 0..7.\r | |
317 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
318 | Range 0..7.\r | |
319 | \r | |
320 | @return The value of the bit field read from the PCI configuration register.\r | |
321 | \r | |
322 | **/\r | |
323 | UINT8\r | |
324 | EFIAPI\r | |
325 | PciBitFieldRead8 (\r | |
326 | IN UINTN Address,\r | |
327 | IN UINTN StartBit,\r | |
328 | IN UINTN EndBit\r | |
329 | )\r | |
330 | {\r | |
331 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
332 | }\r | |
333 | \r | |
334 | /**\r | |
335 | Writes a bit field to a PCI configuration register.\r | |
336 | \r | |
337 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
338 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
339 | destination PCI configuration register are preserved. The new value of the\r | |
340 | 8-bit register is returned.\r | |
341 | \r | |
342 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
343 | If StartBit is greater than 7, then ASSERT().\r | |
344 | If EndBit is greater than 7, then ASSERT().\r | |
345 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 346 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 347 | \r |
2fc59a00 | 348 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 349 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
350 | Range 0..7.\r | |
351 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
352 | Range 0..7.\r | |
2fc59a00 | 353 | @param Value The new value of the bit field.\r |
1a3eaf06 | 354 | \r |
355 | @return The value written back to the PCI configuration register.\r | |
356 | \r | |
357 | **/\r | |
358 | UINT8\r | |
359 | EFIAPI\r | |
360 | PciBitFieldWrite8 (\r | |
361 | IN UINTN Address,\r | |
362 | IN UINTN StartBit,\r | |
363 | IN UINTN EndBit,\r | |
364 | IN UINT8 Value\r | |
365 | )\r | |
366 | {\r | |
367 | return PciWrite8 (\r | |
368 | Address,\r | |
369 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
370 | );\r | |
371 | }\r | |
372 | \r | |
373 | /**\r | |
374 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
375 | writes the result back to the bit field in the 8-bit port.\r | |
376 | \r | |
377 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 378 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 379 | OrData, and writes the result to the 8-bit PCI configuration register\r |
380 | specified by Address. The value written to the PCI configuration register is\r | |
381 | returned. This function must guarantee that all PCI read and write operations\r | |
382 | are serialized. Extra left bits in OrData are stripped.\r | |
383 | \r | |
384 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
385 | If StartBit is greater than 7, then ASSERT().\r | |
386 | If EndBit is greater than 7, then ASSERT().\r | |
387 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 388 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 389 | \r |
2fc59a00 | 390 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 391 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
392 | Range 0..7.\r | |
393 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
394 | Range 0..7.\r | |
395 | @param OrData The value to OR with the PCI configuration register.\r | |
396 | \r | |
397 | @return The value written back to the PCI configuration register.\r | |
398 | \r | |
399 | **/\r | |
400 | UINT8\r | |
401 | EFIAPI\r | |
402 | PciBitFieldOr8 (\r | |
403 | IN UINTN Address,\r | |
404 | IN UINTN StartBit,\r | |
405 | IN UINTN EndBit,\r | |
406 | IN UINT8 OrData\r | |
407 | )\r | |
408 | {\r | |
409 | return PciWrite8 (\r | |
410 | Address,\r | |
411 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
412 | );\r | |
413 | }\r | |
414 | \r | |
415 | /**\r | |
416 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
417 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
418 | \r | |
419 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
420 | bitwise AND between the read result and the value specified by AndData, and\r | |
421 | writes the result to the 8-bit PCI configuration register specified by\r | |
422 | Address. The value written to the PCI configuration register is returned.\r | |
423 | This function must guarantee that all PCI read and write operations are\r | |
424 | serialized. Extra left bits in AndData are stripped.\r | |
425 | \r | |
426 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
427 | If StartBit is greater than 7, then ASSERT().\r | |
428 | If EndBit is greater than 7, then ASSERT().\r | |
429 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 430 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 431 | \r |
2fc59a00 | 432 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 433 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
434 | Range 0..7.\r | |
435 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
436 | Range 0..7.\r | |
437 | @param AndData The value to AND with the PCI configuration register.\r | |
438 | \r | |
439 | @return The value written back to the PCI configuration register.\r | |
440 | \r | |
441 | **/\r | |
442 | UINT8\r | |
443 | EFIAPI\r | |
444 | PciBitFieldAnd8 (\r | |
445 | IN UINTN Address,\r | |
446 | IN UINTN StartBit,\r | |
447 | IN UINTN EndBit,\r | |
448 | IN UINT8 AndData\r | |
449 | )\r | |
450 | {\r | |
451 | return PciWrite8 (\r | |
452 | Address,\r | |
453 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
454 | );\r | |
455 | }\r | |
456 | \r | |
457 | /**\r | |
458 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 459 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 460 | 8-bit port.\r |
461 | \r | |
462 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 463 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 464 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
465 | configuration register specified by Address. The value written to the PCI\r | |
466 | configuration register is returned. This function must guarantee that all PCI\r | |
467 | read and write operations are serialized. Extra left bits in both AndData and\r | |
468 | OrData are stripped.\r | |
469 | \r | |
470 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
471 | If StartBit is greater than 7, then ASSERT().\r | |
472 | If EndBit is greater than 7, then ASSERT().\r | |
473 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
474 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
475 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 476 | \r |
2fc59a00 | 477 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 478 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
479 | Range 0..7.\r | |
480 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
481 | Range 0..7.\r | |
482 | @param AndData The value to AND with the PCI configuration register.\r | |
483 | @param OrData The value to OR with the result of the AND operation.\r | |
484 | \r | |
485 | @return The value written back to the PCI configuration register.\r | |
486 | \r | |
487 | **/\r | |
488 | UINT8\r | |
489 | EFIAPI\r | |
490 | PciBitFieldAndThenOr8 (\r | |
491 | IN UINTN Address,\r | |
492 | IN UINTN StartBit,\r | |
493 | IN UINTN EndBit,\r | |
494 | IN UINT8 AndData,\r | |
495 | IN UINT8 OrData\r | |
496 | )\r | |
497 | {\r | |
498 | return PciWrite8 (\r | |
499 | Address,\r | |
500 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
501 | );\r | |
502 | }\r | |
503 | \r | |
504 | /**\r | |
505 | Reads a 16-bit PCI configuration register.\r | |
506 | \r | |
507 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
508 | This function must guarantee that all PCI read and write operations are\r | |
509 | serialized.\r | |
510 | \r | |
511 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
512 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
513 | \r | |
2fc59a00 | 514 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 515 | Register.\r |
516 | \r | |
9638ba6d | 517 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 518 | \r |
519 | **/\r | |
520 | UINT16\r | |
521 | EFIAPI\r | |
522 | PciRead16 (\r | |
523 | IN UINTN Address\r | |
524 | )\r | |
525 | {\r | |
526 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
527 | \r | |
528 | return (UINT16) PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
529 | }\r | |
530 | \r | |
531 | /**\r | |
532 | Writes a 16-bit PCI configuration register.\r | |
533 | \r | |
534 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
535 | value specified by Value. Value is returned. This function must guarantee\r | |
536 | that all PCI read and write operations are serialized.\r | |
537 | \r | |
538 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
539 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
540 | \r | |
2fc59a00 | 541 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 542 | Register.\r |
9638ba6d | 543 | @param Value The value to write.\r |
1a3eaf06 | 544 | \r |
545 | @return The value written to the PCI configuration register.\r | |
546 | \r | |
547 | **/\r | |
548 | UINT16\r | |
549 | EFIAPI\r | |
550 | PciWrite16 (\r | |
551 | IN UINTN Address,\r | |
0c3437e0 | 552 | IN UINT16 Value\r |
1a3eaf06 | 553 | )\r |
554 | {\r | |
555 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
556 | \r | |
0c3437e0 | 557 | return (UINT16) PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Value);\r |
1a3eaf06 | 558 | }\r |
559 | \r | |
560 | /**\r | |
62991af2 | 561 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 562 | a 16-bit value.\r |
563 | \r | |
564 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 565 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 566 | OrData, and writes the result to the 16-bit PCI configuration register\r |
567 | specified by Address. The value written to the PCI configuration register is\r | |
568 | returned. This function must guarantee that all PCI read and write operations\r | |
569 | are serialized.\r | |
570 | \r | |
571 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
572 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
573 | \r | |
2fc59a00 | 574 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 575 | Register.\r |
576 | @param OrData The value to OR with the PCI configuration register.\r | |
577 | \r | |
578 | @return The value written back to the PCI configuration register.\r | |
579 | \r | |
580 | **/\r | |
581 | UINT16\r | |
582 | EFIAPI\r | |
583 | PciOr16 (\r | |
584 | IN UINTN Address,\r | |
585 | IN UINT16 OrData\r | |
586 | )\r | |
587 | {\r | |
588 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r | |
589 | }\r | |
590 | \r | |
591 | /**\r | |
592 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
593 | value.\r | |
594 | \r | |
595 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
596 | bitwise AND between the read result and the value specified by AndData, and\r | |
597 | writes the result to the 16-bit PCI configuration register specified by\r | |
598 | Address. The value written to the PCI configuration register is returned.\r | |
599 | This function must guarantee that all PCI read and write operations are\r | |
600 | serialized.\r | |
601 | \r | |
602 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
603 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
604 | \r | |
2fc59a00 | 605 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 606 | Register.\r |
607 | @param AndData The value to AND with the PCI configuration register.\r | |
608 | \r | |
609 | @return The value written back to the PCI configuration register.\r | |
610 | \r | |
611 | **/\r | |
612 | UINT16\r | |
613 | EFIAPI\r | |
614 | PciAnd16 (\r | |
615 | IN UINTN Address,\r | |
616 | IN UINT16 AndData\r | |
617 | )\r | |
618 | {\r | |
619 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r | |
620 | }\r | |
621 | \r | |
622 | /**\r | |
623 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 624 | value, followed a bitwise OR with another 16-bit value.\r |
1a3eaf06 | 625 | \r |
626 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
627 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 628 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 629 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
630 | configuration register specified by Address. The value written to the PCI\r | |
631 | configuration register is returned. This function must guarantee that all PCI\r | |
632 | read and write operations are serialized.\r | |
633 | \r | |
634 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
635 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
636 | \r | |
2fc59a00 | 637 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 638 | Register.\r |
639 | @param AndData The value to AND with the PCI configuration register.\r | |
640 | @param OrData The value to OR with the result of the AND operation.\r | |
641 | \r | |
642 | @return The value written back to the PCI configuration register.\r | |
643 | \r | |
644 | **/\r | |
645 | UINT16\r | |
646 | EFIAPI\r | |
647 | PciAndThenOr16 (\r | |
648 | IN UINTN Address,\r | |
649 | IN UINT16 AndData,\r | |
650 | IN UINT16 OrData\r | |
651 | )\r | |
652 | {\r | |
653 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r | |
654 | }\r | |
655 | \r | |
656 | /**\r | |
657 | Reads a bit field of a PCI configuration register.\r | |
658 | \r | |
659 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
660 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
661 | returned.\r | |
662 | \r | |
663 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
664 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
665 | If StartBit is greater than 15, then ASSERT().\r | |
666 | If EndBit is greater than 15, then ASSERT().\r | |
667 | If EndBit is less than StartBit, then ASSERT().\r | |
668 | \r | |
2fc59a00 | 669 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 670 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
671 | Range 0..15.\r | |
672 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
673 | Range 0..15.\r | |
674 | \r | |
675 | @return The value of the bit field read from the PCI configuration register.\r | |
676 | \r | |
677 | **/\r | |
678 | UINT16\r | |
679 | EFIAPI\r | |
680 | PciBitFieldRead16 (\r | |
681 | IN UINTN Address,\r | |
682 | IN UINTN StartBit,\r | |
683 | IN UINTN EndBit\r | |
684 | )\r | |
685 | {\r | |
686 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
687 | }\r | |
688 | \r | |
689 | /**\r | |
690 | Writes a bit field to a PCI configuration register.\r | |
691 | \r | |
692 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
693 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
694 | destination PCI configuration register are preserved. The new value of the\r | |
695 | 16-bit register is returned.\r | |
696 | \r | |
697 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
698 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
699 | If StartBit is greater than 15, then ASSERT().\r | |
700 | If EndBit is greater than 15, then ASSERT().\r | |
701 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 702 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 703 | \r |
2fc59a00 | 704 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 705 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
706 | Range 0..15.\r | |
707 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
708 | Range 0..15.\r | |
2fc59a00 | 709 | @param Value The new value of the bit field.\r |
1a3eaf06 | 710 | \r |
711 | @return The value written back to the PCI configuration register.\r | |
712 | \r | |
713 | **/\r | |
714 | UINT16\r | |
715 | EFIAPI\r | |
716 | PciBitFieldWrite16 (\r | |
717 | IN UINTN Address,\r | |
718 | IN UINTN StartBit,\r | |
719 | IN UINTN EndBit,\r | |
720 | IN UINT16 Value\r | |
721 | )\r | |
722 | {\r | |
723 | return PciWrite16 (\r | |
724 | Address,\r | |
725 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
726 | );\r | |
727 | }\r | |
728 | \r | |
729 | /**\r | |
730 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
731 | writes the result back to the bit field in the 16-bit port.\r | |
732 | \r | |
733 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 734 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 735 | OrData, and writes the result to the 16-bit PCI configuration register\r |
736 | specified by Address. The value written to the PCI configuration register is\r | |
737 | returned. This function must guarantee that all PCI read and write operations\r | |
738 | are serialized. Extra left bits in OrData are stripped.\r | |
739 | \r | |
740 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
741 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
742 | If StartBit is greater than 15, then ASSERT().\r | |
743 | If EndBit is greater than 15, then ASSERT().\r | |
744 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 745 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 746 | \r |
2fc59a00 | 747 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 748 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
749 | Range 0..15.\r | |
750 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
751 | Range 0..15.\r | |
752 | @param OrData The value to OR with the PCI configuration register.\r | |
753 | \r | |
754 | @return The value written back to the PCI configuration register.\r | |
755 | \r | |
756 | **/\r | |
757 | UINT16\r | |
758 | EFIAPI\r | |
759 | PciBitFieldOr16 (\r | |
760 | IN UINTN Address,\r | |
761 | IN UINTN StartBit,\r | |
762 | IN UINTN EndBit,\r | |
763 | IN UINT16 OrData\r | |
764 | )\r | |
765 | {\r | |
766 | return PciWrite16 (\r | |
767 | Address,\r | |
768 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
769 | );\r | |
770 | }\r | |
771 | \r | |
772 | /**\r | |
773 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
774 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
775 | \r | |
776 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
777 | bitwise AND between the read result and the value specified by AndData, and\r | |
778 | writes the result to the 16-bit PCI configuration register specified by\r | |
779 | Address. The value written to the PCI configuration register is returned.\r | |
780 | This function must guarantee that all PCI read and write operations are\r | |
781 | serialized. Extra left bits in AndData are stripped.\r | |
782 | \r | |
783 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
784 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
785 | If StartBit is greater than 15, then ASSERT().\r | |
786 | If EndBit is greater than 15, then ASSERT().\r | |
787 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 788 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 789 | \r |
2fc59a00 | 790 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 791 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
792 | Range 0..15.\r | |
793 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
794 | Range 0..15.\r | |
795 | @param AndData The value to AND with the PCI configuration register.\r | |
796 | \r | |
797 | @return The value written back to the PCI configuration register.\r | |
798 | \r | |
799 | **/\r | |
800 | UINT16\r | |
801 | EFIAPI\r | |
802 | PciBitFieldAnd16 (\r | |
803 | IN UINTN Address,\r | |
804 | IN UINTN StartBit,\r | |
805 | IN UINTN EndBit,\r | |
806 | IN UINT16 AndData\r | |
807 | )\r | |
808 | {\r | |
809 | return PciWrite16 (\r | |
810 | Address,\r | |
811 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
812 | );\r | |
813 | }\r | |
814 | \r | |
815 | /**\r | |
816 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 817 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 818 | 16-bit port.\r |
819 | \r | |
820 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 821 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 822 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
823 | configuration register specified by Address. The value written to the PCI\r | |
824 | configuration register is returned. This function must guarantee that all PCI\r | |
825 | read and write operations are serialized. Extra left bits in both AndData and\r | |
826 | OrData are stripped.\r | |
827 | \r | |
828 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
829 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
830 | If StartBit is greater than 15, then ASSERT().\r | |
831 | If EndBit is greater than 15, then ASSERT().\r | |
832 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
833 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
834 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 835 | \r |
2fc59a00 | 836 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 837 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
838 | Range 0..15.\r | |
839 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
840 | Range 0..15.\r | |
841 | @param AndData The value to AND with the PCI configuration register.\r | |
842 | @param OrData The value to OR with the result of the AND operation.\r | |
843 | \r | |
844 | @return The value written back to the PCI configuration register.\r | |
845 | \r | |
846 | **/\r | |
847 | UINT16\r | |
848 | EFIAPI\r | |
849 | PciBitFieldAndThenOr16 (\r | |
850 | IN UINTN Address,\r | |
851 | IN UINTN StartBit,\r | |
852 | IN UINTN EndBit,\r | |
853 | IN UINT16 AndData,\r | |
854 | IN UINT16 OrData\r | |
855 | )\r | |
856 | {\r | |
857 | return PciWrite16 (\r | |
858 | Address,\r | |
859 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
860 | );\r | |
861 | }\r | |
862 | \r | |
863 | /**\r | |
864 | Reads a 32-bit PCI configuration register.\r | |
865 | \r | |
866 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
867 | This function must guarantee that all PCI read and write operations are\r | |
868 | serialized.\r | |
869 | \r | |
870 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
871 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
872 | \r | |
2fc59a00 | 873 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 874 | Register.\r |
875 | \r | |
9638ba6d | 876 | @return The read value from the PCI configuration register.\r |
1a3eaf06 | 877 | \r |
878 | **/\r | |
879 | UINT32\r | |
880 | EFIAPI\r | |
881 | PciRead32 (\r | |
882 | IN UINTN Address\r | |
883 | )\r | |
884 | {\r | |
885 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
886 | \r | |
887 | return PeiPciLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
888 | }\r | |
889 | \r | |
890 | /**\r | |
891 | Writes a 32-bit PCI configuration register.\r | |
892 | \r | |
893 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
894 | value specified by Value. Value is returned. This function must guarantee\r | |
895 | that all PCI read and write operations are serialized.\r | |
896 | \r | |
897 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
898 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
899 | \r | |
2fc59a00 | 900 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 901 | Register.\r |
9638ba6d | 902 | @param Value The value to write.\r |
1a3eaf06 | 903 | \r |
904 | @return The value written to the PCI configuration register.\r | |
905 | \r | |
906 | **/\r | |
907 | UINT32\r | |
908 | EFIAPI\r | |
909 | PciWrite32 (\r | |
910 | IN UINTN Address,\r | |
0c3437e0 | 911 | IN UINT32 Value\r |
1a3eaf06 | 912 | )\r |
913 | {\r | |
914 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
915 | \r | |
0c3437e0 | 916 | return PeiPciLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Value);\r |
1a3eaf06 | 917 | }\r |
918 | \r | |
919 | /**\r | |
62991af2 | 920 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
1a3eaf06 | 921 | a 32-bit value.\r |
922 | \r | |
923 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 924 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 925 | OrData, and writes the result to the 32-bit PCI configuration register\r |
926 | specified by Address. The value written to the PCI configuration register is\r | |
927 | returned. This function must guarantee that all PCI read and write operations\r | |
928 | are serialized.\r | |
929 | \r | |
930 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
931 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
932 | \r | |
2fc59a00 | 933 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 934 | Register.\r |
935 | @param OrData The value to OR with the PCI configuration register.\r | |
936 | \r | |
937 | @return The value written back to the PCI configuration register.\r | |
938 | \r | |
939 | **/\r | |
940 | UINT32\r | |
941 | EFIAPI\r | |
942 | PciOr32 (\r | |
943 | IN UINTN Address,\r | |
944 | IN UINT32 OrData\r | |
945 | )\r | |
946 | {\r | |
947 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
948 | }\r | |
949 | \r | |
950 | /**\r | |
951 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
952 | value.\r | |
953 | \r | |
954 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
955 | bitwise AND between the read result and the value specified by AndData, and\r | |
956 | writes the result to the 32-bit PCI configuration register specified by\r | |
957 | Address. The value written to the PCI configuration register is returned.\r | |
958 | This function must guarantee that all PCI read and write operations are\r | |
959 | serialized.\r | |
960 | \r | |
961 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
962 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
963 | \r | |
2fc59a00 | 964 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 965 | Register.\r |
966 | @param AndData The value to AND with the PCI configuration register.\r | |
967 | \r | |
968 | @return The value written back to the PCI configuration register.\r | |
969 | \r | |
970 | **/\r | |
971 | UINT32\r | |
972 | EFIAPI\r | |
973 | PciAnd32 (\r | |
974 | IN UINTN Address,\r | |
975 | IN UINT32 AndData\r | |
976 | )\r | |
977 | {\r | |
978 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
979 | }\r | |
980 | \r | |
981 | /**\r | |
982 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 983 | value, followed a bitwise OR with another 32-bit value.\r |
1a3eaf06 | 984 | \r |
985 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
986 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 987 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 988 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
989 | configuration register specified by Address. The value written to the PCI\r | |
990 | configuration register is returned. This function must guarantee that all PCI\r | |
991 | read and write operations are serialized.\r | |
992 | \r | |
993 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
994 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
995 | \r | |
2fc59a00 | 996 | @param Address The address that encodes the PCI Bus, Device, Function and\r |
1a3eaf06 | 997 | Register.\r |
998 | @param AndData The value to AND with the PCI configuration register.\r | |
999 | @param OrData The value to OR with the result of the AND operation.\r | |
1000 | \r | |
1001 | @return The value written back to the PCI configuration register.\r | |
1002 | \r | |
1003 | **/\r | |
1004 | UINT32\r | |
1005 | EFIAPI\r | |
1006 | PciAndThenOr32 (\r | |
1007 | IN UINTN Address,\r | |
1008 | IN UINT32 AndData,\r | |
1009 | IN UINT32 OrData\r | |
1010 | )\r | |
1011 | {\r | |
1012 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1013 | }\r | |
1014 | \r | |
1015 | /**\r | |
1016 | Reads a bit field of a PCI configuration register.\r | |
1017 | \r | |
1018 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1019 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1020 | returned.\r | |
1021 | \r | |
1022 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1023 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1024 | If StartBit is greater than 31, then ASSERT().\r | |
1025 | If EndBit is greater than 31, then ASSERT().\r | |
1026 | If EndBit is less than StartBit, then ASSERT().\r | |
1027 | \r | |
2fc59a00 | 1028 | @param Address The PCI configuration register to read.\r |
1a3eaf06 | 1029 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1030 | Range 0..31.\r | |
1031 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1032 | Range 0..31.\r | |
1033 | \r | |
1034 | @return The value of the bit field read from the PCI configuration register.\r | |
1035 | \r | |
1036 | **/\r | |
1037 | UINT32\r | |
1038 | EFIAPI\r | |
1039 | PciBitFieldRead32 (\r | |
1040 | IN UINTN Address,\r | |
1041 | IN UINTN StartBit,\r | |
1042 | IN UINTN EndBit\r | |
1043 | )\r | |
1044 | {\r | |
1045 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1046 | }\r | |
1047 | \r | |
1048 | /**\r | |
1049 | Writes a bit field to a PCI configuration register.\r | |
1050 | \r | |
1051 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1052 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1053 | destination PCI configuration register are preserved. The new value of the\r | |
1054 | 32-bit register is returned.\r | |
1055 | \r | |
1056 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1057 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1058 | If StartBit is greater than 31, then ASSERT().\r | |
1059 | If EndBit is greater than 31, then ASSERT().\r | |
1060 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1061 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1062 | \r |
2fc59a00 | 1063 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1064 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1065 | Range 0..31.\r | |
1066 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1067 | Range 0..31.\r | |
2fc59a00 | 1068 | @param Value The new value of the bit field.\r |
1a3eaf06 | 1069 | \r |
1070 | @return The value written back to the PCI configuration register.\r | |
1071 | \r | |
1072 | **/\r | |
1073 | UINT32\r | |
1074 | EFIAPI\r | |
1075 | PciBitFieldWrite32 (\r | |
1076 | IN UINTN Address,\r | |
1077 | IN UINTN StartBit,\r | |
1078 | IN UINTN EndBit,\r | |
1079 | IN UINT32 Value\r | |
1080 | )\r | |
1081 | {\r | |
1082 | return PciWrite32 (\r | |
1083 | Address,\r | |
1084 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1085 | );\r | |
1086 | }\r | |
1087 | \r | |
1088 | /**\r | |
1089 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1090 | writes the result back to the bit field in the 32-bit port.\r | |
1091 | \r | |
1092 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1093 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1094 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1095 | specified by Address. The value written to the PCI configuration register is\r | |
1096 | returned. This function must guarantee that all PCI read and write operations\r | |
1097 | are serialized. Extra left bits in OrData are stripped.\r | |
1098 | \r | |
1099 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1100 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1101 | If StartBit is greater than 31, then ASSERT().\r | |
1102 | If EndBit is greater than 31, then ASSERT().\r | |
1103 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1104 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1105 | \r |
2fc59a00 | 1106 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1107 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1108 | Range 0..31.\r | |
1109 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1110 | Range 0..31.\r | |
1111 | @param OrData The value to OR with the PCI configuration register.\r | |
1112 | \r | |
1113 | @return The value written back to the PCI configuration register.\r | |
1114 | \r | |
1115 | **/\r | |
1116 | UINT32\r | |
1117 | EFIAPI\r | |
1118 | PciBitFieldOr32 (\r | |
1119 | IN UINTN Address,\r | |
1120 | IN UINTN StartBit,\r | |
1121 | IN UINTN EndBit,\r | |
1122 | IN UINT32 OrData\r | |
1123 | )\r | |
1124 | {\r | |
1125 | return PciWrite32 (\r | |
1126 | Address,\r | |
1127 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1128 | );\r | |
1129 | }\r | |
1130 | \r | |
1131 | /**\r | |
1132 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1133 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1134 | \r | |
1135 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1136 | bitwise AND between the read result and the value specified by AndData, and\r | |
1137 | writes the result to the 32-bit PCI configuration register specified by\r | |
1138 | Address. The value written to the PCI configuration register is returned.\r | |
1139 | This function must guarantee that all PCI read and write operations are\r | |
1140 | serialized. Extra left bits in AndData are stripped.\r | |
1141 | \r | |
1142 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1143 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1144 | If StartBit is greater than 31, then ASSERT().\r | |
1145 | If EndBit is greater than 31, then ASSERT().\r | |
1146 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 | 1147 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1a3eaf06 | 1148 | \r |
2fc59a00 | 1149 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1150 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1151 | Range 0..31.\r | |
1152 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1153 | Range 0..31.\r | |
1154 | @param AndData The value to AND with the PCI configuration register.\r | |
1155 | \r | |
1156 | @return The value written back to the PCI configuration register.\r | |
1157 | \r | |
1158 | **/\r | |
1159 | UINT32\r | |
1160 | EFIAPI\r | |
1161 | PciBitFieldAnd32 (\r | |
1162 | IN UINTN Address,\r | |
1163 | IN UINTN StartBit,\r | |
1164 | IN UINTN EndBit,\r | |
1165 | IN UINT32 AndData\r | |
1166 | )\r | |
1167 | {\r | |
1168 | return PciWrite32 (\r | |
1169 | Address,\r | |
1170 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1171 | );\r | |
1172 | }\r | |
1173 | \r | |
1174 | /**\r | |
1175 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1176 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1177 | 32-bit port.\r |
1178 | \r | |
1179 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1180 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1181 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1182 | configuration register specified by Address. The value written to the PCI\r | |
1183 | configuration register is returned. This function must guarantee that all PCI\r | |
1184 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1185 | OrData are stripped.\r | |
1186 | \r | |
1187 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1188 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1189 | If StartBit is greater than 31, then ASSERT().\r | |
1190 | If EndBit is greater than 31, then ASSERT().\r | |
1191 | If EndBit is less than StartBit, then ASSERT().\r | |
94952554 LG |
1192 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r |
1193 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
1a3eaf06 | 1194 | \r |
2fc59a00 | 1195 | @param Address The PCI configuration register to write.\r |
1a3eaf06 | 1196 | @param StartBit The ordinal of the least significant bit in the bit field.\r |
1197 | Range 0..31.\r | |
1198 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1199 | Range 0..31.\r | |
1200 | @param AndData The value to AND with the PCI configuration register.\r | |
1201 | @param OrData The value to OR with the result of the AND operation.\r | |
1202 | \r | |
1203 | @return The value written back to the PCI configuration register.\r | |
1204 | \r | |
1205 | **/\r | |
1206 | UINT32\r | |
1207 | EFIAPI\r | |
1208 | PciBitFieldAndThenOr32 (\r | |
1209 | IN UINTN Address,\r | |
1210 | IN UINTN StartBit,\r | |
1211 | IN UINTN EndBit,\r | |
1212 | IN UINT32 AndData,\r | |
1213 | IN UINT32 OrData\r | |
1214 | )\r | |
1215 | {\r | |
1216 | return PciWrite32 (\r | |
1217 | Address,\r | |
1218 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1219 | );\r | |
1220 | }\r | |
1221 | \r | |
1222 | /**\r | |
1223 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1224 | \r | |
1225 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1226 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1227 | configuration registers from a single PCI function to be read. Size is\r | |
1228 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1229 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1230 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1231 | end of the range.\r | |
1232 | \r | |
1233 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1234 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1235 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1236 | \r | |
2fc59a00 | 1237 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1238 | Function and Register.\r |
2fc59a00 | 1239 | @param Size The size in bytes of the transfer.\r |
1240 | @param Buffer The pointer to a buffer receiving the data read.\r | |
1a3eaf06 | 1241 | \r |
1242 | @return Size\r | |
1243 | \r | |
1244 | **/\r | |
1245 | UINTN\r | |
1246 | EFIAPI\r | |
1247 | PciReadBuffer (\r | |
1248 | IN UINTN StartAddress,\r | |
1249 | IN UINTN Size,\r | |
1250 | OUT VOID *Buffer\r | |
1251 | )\r | |
1252 | {\r | |
1253 | UINTN ReturnValue;\r | |
1254 | \r | |
1255 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1256 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1257 | \r |
1258 | if (Size == 0) {\r | |
1259 | return Size;\r | |
1260 | }\r | |
1261 | \r | |
1262 | ASSERT (Buffer != NULL);\r | |
1263 | \r | |
1264 | //\r | |
1265 | // Save Size for return\r | |
1266 | //\r | |
1267 | ReturnValue = Size;\r | |
1268 | \r | |
e43e4b3e | 1269 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1270 | //\r |
1271 | // Read a byte if StartAddress is byte aligned\r | |
1272 | //\r | |
1273 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1274 | StartAddress += sizeof (UINT8);\r | |
1275 | Size -= sizeof (UINT8);\r | |
1276 | Buffer = (UINT8*)Buffer + 1;\r | |
1277 | }\r | |
1278 | \r | |
e43e4b3e | 1279 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1280 | //\r |
1281 | // Read a word if StartAddress is word aligned\r | |
1282 | //\r | |
5dc4fd78 | 1283 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1284 | StartAddress += sizeof (UINT16);\r |
1285 | Size -= sizeof (UINT16);\r | |
1286 | Buffer = (UINT16*)Buffer + 1;\r | |
1287 | }\r | |
1288 | \r | |
1289 | while (Size >= sizeof (UINT32)) {\r | |
1290 | //\r | |
1291 | // Read as many double words as possible\r | |
1292 | //\r | |
5dc4fd78 | 1293 | WriteUnaligned32 (Buffer, PciRead32 (StartAddress));\r |
1a3eaf06 | 1294 | StartAddress += sizeof (UINT32);\r |
1295 | Size -= sizeof (UINT32);\r | |
1296 | Buffer = (UINT32*)Buffer + 1;\r | |
1297 | }\r | |
1298 | \r | |
1299 | if (Size >= sizeof (UINT16)) {\r | |
1300 | //\r | |
1301 | // Read the last remaining word if exist\r | |
1302 | //\r | |
5dc4fd78 | 1303 | WriteUnaligned16 (Buffer, PciRead16 (StartAddress));\r |
1a3eaf06 | 1304 | StartAddress += sizeof (UINT16);\r |
1305 | Size -= sizeof (UINT16);\r | |
1306 | Buffer = (UINT16*)Buffer + 1;\r | |
1307 | }\r | |
1308 | \r | |
1309 | if (Size >= sizeof (UINT8)) {\r | |
1310 | //\r | |
1311 | // Read the last remaining byte if exist\r | |
1312 | //\r | |
1313 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1314 | }\r | |
1315 | \r | |
1316 | return ReturnValue;\r | |
1317 | }\r | |
1318 | \r | |
1319 | /**\r | |
1320 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1321 | configuration space.\r | |
1322 | \r | |
1323 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1324 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1325 | configuration registers from a single PCI function to be written. Size is\r | |
1326 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1327 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1328 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1329 | and the end of the range.\r | |
1330 | \r | |
1331 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1332 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1333 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1334 | \r | |
2fc59a00 | 1335 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r |
1a3eaf06 | 1336 | Function and Register.\r |
2fc59a00 | 1337 | @param Size The size in bytes of the transfer.\r |
1338 | @param Buffer The pointer to a buffer containing the data to write.\r | |
1a3eaf06 | 1339 | \r |
0c3437e0 | 1340 | @return Size written to StartAddress.\r |
1a3eaf06 | 1341 | \r |
1342 | **/\r | |
1343 | UINTN\r | |
1344 | EFIAPI\r | |
1345 | PciWriteBuffer (\r | |
1346 | IN UINTN StartAddress,\r | |
1347 | IN UINTN Size,\r | |
1348 | IN VOID *Buffer\r | |
1349 | )\r | |
1350 | {\r | |
1351 | UINTN ReturnValue;\r | |
1352 | \r | |
1353 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1354 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1355 | \r |
1356 | if (Size == 0) {\r | |
1357 | return 0;\r | |
1358 | }\r | |
1359 | \r | |
1360 | ASSERT (Buffer != NULL);\r | |
1361 | \r | |
1362 | //\r | |
1363 | // Save Size for return\r | |
1364 | //\r | |
1365 | ReturnValue = Size;\r | |
1366 | \r | |
e43e4b3e | 1367 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1368 | //\r |
1369 | // Write a byte if StartAddress is byte aligned\r | |
1370 | //\r | |
1371 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1372 | StartAddress += sizeof (UINT8);\r | |
1373 | Size -= sizeof (UINT8);\r | |
1374 | Buffer = (UINT8*)Buffer + 1;\r | |
1375 | }\r | |
1376 | \r | |
e43e4b3e | 1377 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1378 | //\r |
1379 | // Write a word if StartAddress is word aligned\r | |
1380 | //\r | |
5dc4fd78 | 1381 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1382 | StartAddress += sizeof (UINT16);\r |
1383 | Size -= sizeof (UINT16);\r | |
1384 | Buffer = (UINT16*)Buffer + 1;\r | |
1385 | }\r | |
1386 | \r | |
1387 | while (Size >= sizeof (UINT32)) {\r | |
1388 | //\r | |
1389 | // Write as many double words as possible\r | |
1390 | //\r | |
5dc4fd78 | 1391 | PciWrite32 (StartAddress, ReadUnaligned32 (Buffer));\r |
1a3eaf06 | 1392 | StartAddress += sizeof (UINT32);\r |
1393 | Size -= sizeof (UINT32);\r | |
1394 | Buffer = (UINT32*)Buffer + 1;\r | |
1395 | }\r | |
1396 | \r | |
1397 | if (Size >= sizeof (UINT16)) {\r | |
1398 | //\r | |
1399 | // Write the last remaining word if exist\r | |
1400 | //\r | |
5dc4fd78 | 1401 | PciWrite16 (StartAddress, ReadUnaligned16 (Buffer));\r |
1a3eaf06 | 1402 | StartAddress += sizeof (UINT16);\r |
1403 | Size -= sizeof (UINT16);\r | |
1404 | Buffer = (UINT16*)Buffer + 1;\r | |
1405 | }\r | |
1406 | \r | |
1407 | if (Size >= sizeof (UINT8)) {\r | |
1408 | //\r | |
1409 | // Write the last remaining byte if exist\r | |
1410 | //\r | |
1411 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1412 | }\r | |
1413 | \r | |
1414 | return ReturnValue;\r | |
1415 | }\r |