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1a3eaf06 | 1 | /** @file\r |
2 | PCI Segment Library implementation using PCI CFG2 PPI.\r | |
3 | \r | |
4 | Copyright (c) 2007 - 2008, Intel Corporation All rights\r | |
5 | reserved. This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of\r | |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiPei.h>\r | |
17 | \r | |
18 | #include <Ppi/PciCfg2.h>\r | |
19 | \r | |
20 | #include <Library/PciSegmentLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/PeiServicesTablePointerLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | #include <Library/PeiServicesLib.h>\r | |
25 | \r | |
26 | /**\r | |
27 | Assert the validity of a PCI Segment address.\r | |
28 | A valid PCI Segment address should not contain 1's in bits 31:28\r | |
29 | \r | |
30 | @param A The address to validate.\r | |
31 | @param M Additional bits to assert to be zero.\r | |
32 | \r | |
33 | **/\r | |
34 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r | |
35 | ASSERT (((A) & (0xf0000000 | (M))) == 0)\r | |
36 | \r | |
37 | /**\r | |
38 | Translate PCI Lib address into format of PCI CFG2 PPI.\r | |
39 | \r | |
40 | @param A Address that encodes the PCI Bus, Device, Function and\r | |
41 | Register.\r | |
42 | \r | |
43 | **/\r | |
44 | #define PCI_TO_PCICFG2_ADDRESS(A) \\r | |
e43e4b3e | 45 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
1a3eaf06 | 46 | \r |
47 | /**\r | |
48 | Gets PCI CFG2 PPI.\r | |
49 | \r | |
50 | This internal function retrieves PCI CFG2 PPI from PPI database.\r | |
51 | \r | |
52 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and Register.\r | |
53 | \r | |
54 | @return The pointer to PCI CFG2 PPI.\r | |
55 | \r | |
56 | **/\r | |
57 | EFI_PEI_PCI_CFG2_PPI *\r | |
58 | InternalGetPciCfg2Ppi (\r | |
59 | IN UINT64 Address\r | |
60 | )\r | |
61 | {\r | |
62 | EFI_STATUS Status;\r | |
63 | UINTN Instance;\r | |
64 | EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
65 | UINT64 SegmentNumber;\r | |
66 | \r | |
67 | Instance = 0;\r | |
68 | PciCfg2Ppi = NULL;\r | |
69 | SegmentNumber = BitFieldRead64 (Address, 32, 63);\r | |
70 | \r | |
71 | //\r | |
72 | // Loop through all instances of the PPI and match segment number\r | |
73 | //\r | |
74 | do {\r | |
75 | Status = PeiServicesLocatePpi(\r | |
76 | &gEfiPciCfg2PpiGuid,\r | |
77 | Instance,\r | |
78 | NULL,\r | |
79 | (VOID**) &PciCfg2Ppi\r | |
80 | );\r | |
81 | ASSERT_EFI_ERROR (Status);\r | |
82 | Instance++;\r | |
83 | } while (PciCfg2Ppi->Segment != SegmentNumber);\r | |
84 | \r | |
85 | return PciCfg2Ppi;\r | |
86 | }\r | |
87 | \r | |
88 | /**\r | |
89 | Internal worker function to read a PCI configuration register.\r | |
90 | \r | |
91 | This function wraps EFI_PEI_PCI_CFG2_PPI.Read() service.\r | |
92 | It reads and returns the PCI configuration register specified by Address,\r | |
93 | the width of data is specified by Width.\r | |
94 | \r | |
95 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
96 | Register.\r | |
97 | @param Width Width of data to read\r | |
98 | \r | |
99 | @return The value read from the PCI configuration register.\r | |
100 | \r | |
101 | **/\r | |
102 | UINT32\r | |
103 | PeiPciSegmentLibPciCfg2ReadWorker (\r | |
104 | IN UINT64 Address,\r | |
105 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width\r | |
106 | )\r | |
107 | {\r | |
108 | UINT32 Data;\r | |
109 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 110 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 111 | \r |
112 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 113 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 114 | PciCfg2Ppi->Read (\r |
115 | GetPeiServicesTablePointer (),\r | |
116 | PciCfg2Ppi,\r | |
117 | Width,\r | |
43fe5cdc | 118 | PciCfg2Address,\r |
1a3eaf06 | 119 | &Data\r |
120 | );\r | |
121 | \r | |
122 | return Data;\r | |
123 | }\r | |
124 | \r | |
125 | /**\r | |
126 | Internal worker function to writes a PCI configuration register.\r | |
127 | \r | |
128 | This function wraps EFI_PEI_PCI_CFG2_PPI.Write() service.\r | |
129 | It writes the PCI configuration register specified by Address with the\r | |
130 | value specified by Data. The width of data is specifed by Width.\r | |
131 | Data is returned.\r | |
132 | \r | |
133 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
134 | Register.\r | |
135 | @param Width Width of data to write\r | |
136 | @param Data The value to write.\r | |
137 | \r | |
138 | @return The value written to the PCI configuration register.\r | |
139 | \r | |
140 | **/\r | |
141 | UINT32\r | |
142 | PeiPciSegmentLibPciCfg2WriteWorker (\r | |
143 | IN UINT64 Address,\r | |
144 | IN EFI_PEI_PCI_CFG_PPI_WIDTH Width,\r | |
145 | IN UINT32 Data\r | |
146 | )\r | |
147 | {\r | |
148 | CONST EFI_PEI_PCI_CFG2_PPI *PciCfg2Ppi;\r | |
43fe5cdc | 149 | UINT64 PciCfg2Address;\r |
1a3eaf06 | 150 | \r |
151 | PciCfg2Ppi = InternalGetPciCfg2Ppi (Address);\r | |
43fe5cdc | 152 | PciCfg2Address = PCI_TO_PCICFG2_ADDRESS (Address);\r |
1a3eaf06 | 153 | PciCfg2Ppi->Write (\r |
154 | GetPeiServicesTablePointer (),\r | |
155 | PciCfg2Ppi,\r | |
156 | Width,\r | |
43fe5cdc | 157 | PciCfg2Address,\r |
1a3eaf06 | 158 | &Data\r |
159 | );\r | |
160 | \r | |
161 | return Data;\r | |
162 | }\r | |
163 | \r | |
3e3ae634 | 164 | /**\r |
165 | Register a PCI device so PCI configuration registers may be accessed after \r | |
166 | SetVirtualAddressMap().\r | |
167 | \r | |
168 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
169 | \r | |
170 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
171 | Register.\r | |
172 | \r | |
173 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
174 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
175 | after ExitBootServices().\r | |
176 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
177 | at runtime could not be mapped.\r | |
178 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
179 | complete the registration.\r | |
180 | \r | |
181 | **/\r | |
182 | RETURN_STATUS\r | |
183 | EFIAPI\r | |
184 | PciSegmentRegisterForRuntimeAccess (\r | |
185 | IN UINTN Address\r | |
186 | )\r | |
187 | {\r | |
188 | return RETURN_UNSUPPORTED;\r | |
189 | }\r | |
190 | \r | |
1a3eaf06 | 191 | /**\r |
192 | Reads an 8-bit PCI configuration register.\r | |
193 | \r | |
194 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
195 | This function must guarantee that all PCI read and write operations are\r | |
196 | serialized.\r | |
197 | \r | |
198 | If any reserved bits in Address are set, then ASSERT().\r | |
199 | \r | |
200 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
201 | Register.\r | |
202 | \r | |
203 | @return The value read from the PCI configuration register.\r | |
204 | \r | |
205 | **/\r | |
206 | UINT8\r | |
207 | EFIAPI\r | |
208 | PciSegmentRead8 (\r | |
209 | IN UINT64 Address\r | |
210 | )\r | |
211 | {\r | |
212 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
213 | \r | |
214 | return (UINT8) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint8);\r | |
215 | }\r | |
216 | \r | |
217 | /**\r | |
218 | Writes an 8-bit PCI configuration register.\r | |
219 | \r | |
220 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
221 | value specified by Value. Value is returned. This function must guarantee\r | |
222 | that all PCI read and write operations are serialized.\r | |
223 | \r | |
224 | If any reserved bits in Address are set, then ASSERT().\r | |
225 | \r | |
226 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
227 | Register.\r | |
228 | @param Data The value to write.\r | |
229 | \r | |
230 | @return The value written to the PCI configuration register.\r | |
231 | \r | |
232 | **/\r | |
233 | UINT8\r | |
234 | EFIAPI\r | |
235 | PciSegmentWrite8 (\r | |
236 | IN UINT64 Address,\r | |
237 | IN UINT8 Data\r | |
238 | )\r | |
239 | {\r | |
240 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 0);\r | |
241 | \r | |
242 | return (UINT8) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint8, Data);\r | |
243 | }\r | |
244 | \r | |
245 | /**\r | |
246 | Performs a bitwise inclusive OR of an 8-bit PCI configuration register with\r | |
247 | an 8-bit value.\r | |
248 | \r | |
249 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
250 | bitwise inclusive OR between the read result and the value specified by\r | |
251 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
252 | specified by Address. The value written to the PCI configuration register is\r | |
253 | returned. This function must guarantee that all PCI read and write operations\r | |
254 | are serialized.\r | |
255 | \r | |
256 | If any reserved bits in Address are set, then ASSERT().\r | |
257 | \r | |
258 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
259 | Register.\r | |
260 | @param OrData The value to OR with the PCI configuration register.\r | |
261 | \r | |
262 | @return The value written back to the PCI configuration register.\r | |
263 | \r | |
264 | **/\r | |
265 | UINT8\r | |
266 | EFIAPI\r | |
267 | PciSegmentOr8 (\r | |
268 | IN UINT64 Address,\r | |
269 | IN UINT8 OrData\r | |
270 | )\r | |
271 | {\r | |
272 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) | OrData));\r | |
273 | }\r | |
274 | \r | |
275 | /**\r | |
122e2191 | 276 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value.\r |
1a3eaf06 | 277 | \r |
122e2191 | 278 | Reads the 8-bit PCI configuration register specified by Address,\r |
279 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
280 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
281 | The value written to the PCI configuration register is returned.\r | |
282 | This function must guarantee that all PCI read and write operations are serialized.\r | |
1a3eaf06 | 283 | If any reserved bits in Address are set, then ASSERT().\r |
284 | \r | |
122e2191 | 285 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
286 | @param AndData The value to AND with the PCI configuration register.\r | |
1a3eaf06 | 287 | \r |
122e2191 | 288 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 289 | \r |
290 | **/\r | |
291 | UINT8\r | |
292 | EFIAPI\r | |
293 | PciSegmentAnd8 (\r | |
294 | IN UINT64 Address,\r | |
295 | IN UINT8 AndData\r | |
296 | )\r | |
297 | {\r | |
298 | return PciSegmentWrite8 (Address, (UINT8) (PciSegmentRead8 (Address) & AndData));\r | |
299 | }\r | |
300 | \r | |
301 | /**\r | |
122e2191 | 302 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit value,\r |
303 | followed a bitwise inclusive OR with another 8-bit value.\r | |
304 | \r | |
305 | Reads the 8-bit PCI configuration register specified by Address,\r | |
306 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
307 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r | |
308 | and writes the result to the 8-bit PCI configuration register specified by Address.\r | |
309 | The value written to the PCI configuration register is returned.\r | |
310 | This function must guarantee that all PCI read and write operations are serialized.\r | |
311 | \r | |
1a3eaf06 | 312 | If any reserved bits in Address are set, then ASSERT().\r |
313 | \r | |
122e2191 | 314 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
315 | @param AndData The value to AND with the PCI configuration register.\r | |
316 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 317 | \r |
122e2191 | 318 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 319 | \r |
320 | **/\r | |
321 | UINT8\r | |
322 | EFIAPI\r | |
323 | PciSegmentAndThenOr8 (\r | |
324 | IN UINT64 Address,\r | |
325 | IN UINT8 AndData,\r | |
326 | IN UINT8 OrData\r | |
327 | )\r | |
328 | {\r | |
329 | return PciSegmentWrite8 (Address, (UINT8) ((PciSegmentRead8 (Address) & AndData) | OrData));\r | |
330 | }\r | |
331 | \r | |
332 | /**\r | |
333 | Reads a bit field of a PCI configuration register.\r | |
334 | \r | |
335 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
336 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
337 | returned.\r | |
338 | \r | |
339 | If any reserved bits in Address are set, then ASSERT().\r | |
340 | If StartBit is greater than 7, then ASSERT().\r | |
341 | If EndBit is greater than 7, then ASSERT().\r | |
342 | If EndBit is less than StartBit, then ASSERT().\r | |
343 | \r | |
344 | @param Address PCI configuration register to read.\r | |
345 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
346 | Range 0..7.\r | |
347 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
348 | Range 0..7.\r | |
349 | \r | |
350 | @return The value of the bit field read from the PCI configuration register.\r | |
351 | \r | |
352 | **/\r | |
353 | UINT8\r | |
354 | EFIAPI\r | |
355 | PciSegmentBitFieldRead8 (\r | |
356 | IN UINT64 Address,\r | |
357 | IN UINTN StartBit,\r | |
358 | IN UINTN EndBit\r | |
359 | )\r | |
360 | {\r | |
361 | return BitFieldRead8 (PciSegmentRead8 (Address), StartBit, EndBit);\r | |
362 | }\r | |
363 | \r | |
364 | /**\r | |
365 | Writes a bit field to a PCI configuration register.\r | |
366 | \r | |
367 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
368 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
369 | destination PCI configuration register are preserved. The new value of the\r | |
370 | 8-bit register is returned.\r | |
371 | \r | |
372 | If any reserved bits in Address are set, then ASSERT().\r | |
373 | If StartBit is greater than 7, then ASSERT().\r | |
374 | If EndBit is greater than 7, then ASSERT().\r | |
375 | If EndBit is less than StartBit, then ASSERT().\r | |
376 | \r | |
377 | @param Address PCI configuration register to write.\r | |
378 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
379 | Range 0..7.\r | |
380 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
381 | Range 0..7.\r | |
382 | @param Value New value of the bit field.\r | |
383 | \r | |
384 | @return The value written back to the PCI configuration register.\r | |
385 | \r | |
386 | **/\r | |
387 | UINT8\r | |
388 | EFIAPI\r | |
389 | PciSegmentBitFieldWrite8 (\r | |
390 | IN UINT64 Address,\r | |
391 | IN UINTN StartBit,\r | |
392 | IN UINTN EndBit,\r | |
393 | IN UINT8 Value\r | |
394 | )\r | |
395 | {\r | |
396 | return PciSegmentWrite8 (\r | |
397 | Address,\r | |
398 | BitFieldWrite8 (PciSegmentRead8 (Address), StartBit, EndBit, Value)\r | |
399 | );\r | |
400 | }\r | |
401 | \r | |
402 | /**\r | |
403 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
404 | writes the result back to the bit field in the 8-bit port.\r | |
405 | \r | |
406 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
407 | bitwise inclusive OR between the read result and the value specified by\r | |
408 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
409 | specified by Address. The value written to the PCI configuration register is\r | |
410 | returned. This function must guarantee that all PCI read and write operations\r | |
411 | are serialized. Extra left bits in OrData are stripped.\r | |
412 | \r | |
413 | If any reserved bits in Address are set, then ASSERT().\r | |
414 | If StartBit is greater than 7, then ASSERT().\r | |
415 | If EndBit is greater than 7, then ASSERT().\r | |
416 | If EndBit is less than StartBit, then ASSERT().\r | |
417 | \r | |
418 | @param Address PCI configuration register to write.\r | |
419 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
420 | Range 0..7.\r | |
421 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
422 | Range 0..7.\r | |
423 | @param OrData The value to OR with the PCI configuration register.\r | |
424 | \r | |
425 | @return The value written back to the PCI configuration register.\r | |
426 | \r | |
427 | **/\r | |
428 | UINT8\r | |
429 | EFIAPI\r | |
430 | PciSegmentBitFieldOr8 (\r | |
431 | IN UINT64 Address,\r | |
432 | IN UINTN StartBit,\r | |
433 | IN UINTN EndBit,\r | |
434 | IN UINT8 OrData\r | |
435 | )\r | |
436 | {\r | |
437 | return PciSegmentWrite8 (\r | |
438 | Address,\r | |
439 | BitFieldOr8 (PciSegmentRead8 (Address), StartBit, EndBit, OrData)\r | |
440 | );\r | |
441 | }\r | |
442 | \r | |
443 | /**\r | |
444 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
445 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
446 | \r | |
447 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
448 | bitwise AND between the read result and the value specified by AndData, and\r | |
449 | writes the result to the 8-bit PCI configuration register specified by\r | |
450 | Address. The value written to the PCI configuration register is returned.\r | |
451 | This function must guarantee that all PCI read and write operations are\r | |
452 | serialized. Extra left bits in AndData are stripped.\r | |
453 | \r | |
454 | If any reserved bits in Address are set, then ASSERT().\r | |
455 | If StartBit is greater than 7, then ASSERT().\r | |
456 | If EndBit is greater than 7, then ASSERT().\r | |
457 | If EndBit is less than StartBit, then ASSERT().\r | |
458 | \r | |
459 | @param Address PCI configuration register to write.\r | |
460 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
461 | Range 0..7.\r | |
462 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
463 | Range 0..7.\r | |
464 | @param AndData The value to AND with the PCI configuration register.\r | |
465 | \r | |
466 | @return The value written back to the PCI configuration register.\r | |
467 | \r | |
468 | **/\r | |
469 | UINT8\r | |
470 | EFIAPI\r | |
471 | PciSegmentBitFieldAnd8 (\r | |
472 | IN UINT64 Address,\r | |
473 | IN UINTN StartBit,\r | |
474 | IN UINTN EndBit,\r | |
475 | IN UINT8 AndData\r | |
476 | )\r | |
477 | {\r | |
478 | return PciSegmentWrite8 (\r | |
479 | Address,\r | |
480 | BitFieldAnd8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData)\r | |
481 | );\r | |
482 | }\r | |
483 | \r | |
484 | /**\r | |
485 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
486 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
487 | 8-bit port.\r | |
488 | \r | |
489 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
490 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
491 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
492 | configuration register specified by Address. The value written to the PCI\r | |
493 | configuration register is returned. This function must guarantee that all PCI\r | |
494 | read and write operations are serialized. Extra left bits in both AndData and\r | |
495 | OrData are stripped.\r | |
496 | \r | |
497 | If any reserved bits in Address are set, then ASSERT().\r | |
498 | If StartBit is greater than 7, then ASSERT().\r | |
499 | If EndBit is greater than 7, then ASSERT().\r | |
500 | If EndBit is less than StartBit, then ASSERT().\r | |
501 | \r | |
502 | @param Address PCI configuration register to write.\r | |
503 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
504 | Range 0..7.\r | |
505 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
506 | Range 0..7.\r | |
507 | @param AndData The value to AND with the PCI configuration register.\r | |
508 | @param OrData The value to OR with the result of the AND operation.\r | |
509 | \r | |
510 | @return The value written back to the PCI configuration register.\r | |
511 | \r | |
512 | **/\r | |
513 | UINT8\r | |
514 | EFIAPI\r | |
515 | PciSegmentBitFieldAndThenOr8 (\r | |
516 | IN UINT64 Address,\r | |
517 | IN UINTN StartBit,\r | |
518 | IN UINTN EndBit,\r | |
519 | IN UINT8 AndData,\r | |
520 | IN UINT8 OrData\r | |
521 | )\r | |
522 | {\r | |
523 | return PciSegmentWrite8 (\r | |
524 | Address,\r | |
525 | BitFieldAndThenOr8 (PciSegmentRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
526 | );\r | |
527 | }\r | |
528 | \r | |
529 | /**\r | |
530 | Reads a 16-bit PCI configuration register.\r | |
531 | \r | |
532 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
533 | This function must guarantee that all PCI read and write operations are\r | |
534 | serialized.\r | |
535 | \r | |
536 | If any reserved bits in Address are set, then ASSERT().\r | |
537 | \r | |
538 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
539 | Register.\r | |
540 | \r | |
541 | @return The value read from the PCI configuration register.\r | |
542 | \r | |
543 | **/\r | |
544 | UINT16\r | |
545 | EFIAPI\r | |
546 | PciSegmentRead16 (\r | |
547 | IN UINT64 Address\r | |
548 | )\r | |
549 | {\r | |
550 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
551 | \r | |
552 | return (UINT16) PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint16);\r | |
553 | }\r | |
554 | \r | |
555 | /**\r | |
556 | Writes a 16-bit PCI configuration register.\r | |
557 | \r | |
558 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
559 | value specified by Value. Value is returned. This function must guarantee\r | |
560 | that all PCI read and write operations are serialized.\r | |
561 | \r | |
562 | If any reserved bits in Address are set, then ASSERT().\r | |
563 | \r | |
564 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
565 | Register.\r | |
566 | @param Data The value to write.\r | |
567 | \r | |
568 | @return The value written to the PCI configuration register.\r | |
569 | \r | |
570 | **/\r | |
571 | UINT16\r | |
572 | EFIAPI\r | |
573 | PciSegmentWrite16 (\r | |
574 | IN UINT64 Address,\r | |
575 | IN UINT16 Data\r | |
576 | )\r | |
577 | {\r | |
578 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 1);\r | |
579 | \r | |
580 | return (UINT16) PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint16, Data);\r | |
581 | }\r | |
582 | \r | |
583 | /**\r | |
584 | Performs a bitwise inclusive OR of a 16-bit PCI configuration register with\r | |
585 | a 16-bit value.\r | |
586 | \r | |
587 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
588 | bitwise inclusive OR between the read result and the value specified by\r | |
589 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
590 | specified by Address. The value written to the PCI configuration register is\r | |
591 | returned. This function must guarantee that all PCI read and write operations\r | |
592 | are serialized.\r | |
593 | \r | |
594 | If any reserved bits in Address are set, then ASSERT().\r | |
595 | \r | |
596 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
597 | Register.\r | |
598 | @param OrData The value to OR with the PCI configuration register.\r | |
599 | \r | |
600 | @return The value written back to the PCI configuration register.\r | |
601 | \r | |
602 | **/\r | |
603 | UINT16\r | |
604 | EFIAPI\r | |
605 | PciSegmentOr16 (\r | |
606 | IN UINT64 Address,\r | |
607 | IN UINT16 OrData\r | |
608 | )\r | |
609 | {\r | |
610 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) | OrData));\r | |
611 | }\r | |
612 | \r | |
613 | /**\r | |
122e2191 | 614 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit value.\r |
1a3eaf06 | 615 | \r |
122e2191 | 616 | Reads the 16-bit PCI configuration register specified by Address,\r |
617 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
618 | and writes the result to the 16-bit PCI configuration register specified by Address.\r | |
619 | The value written to the PCI configuration register is returned.\r | |
620 | This function must guarantee that all PCI read and write operations are serialized.\r | |
621 | \r | |
1a3eaf06 | 622 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 623 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r |
624 | \r | |
625 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r | |
626 | @param AndData The value to AND with the PCI configuration register.\r | |
1a3eaf06 | 627 | \r |
122e2191 | 628 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 629 | \r |
630 | **/\r | |
631 | UINT16\r | |
632 | EFIAPI\r | |
633 | PciSegmentAnd16 (\r | |
634 | IN UINT64 Address,\r | |
635 | IN UINT16 AndData\r | |
636 | )\r | |
637 | {\r | |
638 | return PciSegmentWrite16 (Address, (UINT16) (PciSegmentRead16 (Address) & AndData));\r | |
639 | }\r | |
640 | \r | |
641 | /**\r | |
642 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
643 | value, followed a bitwise inclusive OR with another 16-bit value.\r | |
644 | \r | |
645 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
646 | bitwise AND between the read result and the value specified by AndData,\r | |
647 | performs a bitwise inclusive OR between the result of the AND operation and\r | |
648 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
649 | configuration register specified by Address. The value written to the PCI\r | |
650 | configuration register is returned. This function must guarantee that all PCI\r | |
651 | read and write operations are serialized.\r | |
652 | \r | |
653 | If any reserved bits in Address are set, then ASSERT().\r | |
654 | \r | |
655 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
656 | Register.\r | |
657 | @param AndData The value to AND with the PCI configuration register.\r | |
658 | @param OrData The value to OR with the result of the AND operation.\r | |
659 | \r | |
660 | @return The value written back to the PCI configuration register.\r | |
661 | \r | |
662 | **/\r | |
663 | UINT16\r | |
664 | EFIAPI\r | |
665 | PciSegmentAndThenOr16 (\r | |
666 | IN UINT64 Address,\r | |
667 | IN UINT16 AndData,\r | |
668 | IN UINT16 OrData\r | |
669 | )\r | |
670 | {\r | |
671 | return PciSegmentWrite16 (Address, (UINT16) ((PciSegmentRead16 (Address) & AndData) | OrData));\r | |
672 | }\r | |
673 | \r | |
674 | /**\r | |
675 | Reads a bit field of a PCI configuration register.\r | |
676 | \r | |
677 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
678 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
679 | returned.\r | |
680 | \r | |
681 | If any reserved bits in Address are set, then ASSERT().\r | |
682 | If StartBit is greater than 15, then ASSERT().\r | |
683 | If EndBit is greater than 15, then ASSERT().\r | |
684 | If EndBit is less than StartBit, then ASSERT().\r | |
685 | \r | |
686 | @param Address PCI configuration register to read.\r | |
687 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
688 | Range 0..15.\r | |
689 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
690 | Range 0..15.\r | |
691 | \r | |
692 | @return The value of the bit field read from the PCI configuration register.\r | |
693 | \r | |
694 | **/\r | |
695 | UINT16\r | |
696 | EFIAPI\r | |
697 | PciSegmentBitFieldRead16 (\r | |
698 | IN UINT64 Address,\r | |
699 | IN UINTN StartBit,\r | |
700 | IN UINTN EndBit\r | |
701 | )\r | |
702 | {\r | |
703 | return BitFieldRead16 (PciSegmentRead16 (Address), StartBit, EndBit);\r | |
704 | }\r | |
705 | \r | |
706 | /**\r | |
707 | Writes a bit field to a PCI configuration register.\r | |
708 | \r | |
709 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
710 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
711 | destination PCI configuration register are preserved. The new value of the\r | |
712 | 16-bit register is returned.\r | |
713 | \r | |
714 | If any reserved bits in Address are set, then ASSERT().\r | |
715 | If StartBit is greater than 15, then ASSERT().\r | |
716 | If EndBit is greater than 15, then ASSERT().\r | |
717 | If EndBit is less than StartBit, then ASSERT().\r | |
718 | \r | |
719 | @param Address PCI configuration register to write.\r | |
720 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
721 | Range 0..15.\r | |
722 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
723 | Range 0..15.\r | |
724 | @param Value New value of the bit field.\r | |
725 | \r | |
726 | @return The value written back to the PCI configuration register.\r | |
727 | \r | |
728 | **/\r | |
729 | UINT16\r | |
730 | EFIAPI\r | |
731 | PciSegmentBitFieldWrite16 (\r | |
732 | IN UINT64 Address,\r | |
733 | IN UINTN StartBit,\r | |
734 | IN UINTN EndBit,\r | |
735 | IN UINT16 Value\r | |
736 | )\r | |
737 | {\r | |
738 | return PciSegmentWrite16 (\r | |
739 | Address,\r | |
740 | BitFieldWrite16 (PciSegmentRead16 (Address), StartBit, EndBit, Value)\r | |
741 | );\r | |
742 | }\r | |
743 | \r | |
744 | /**\r | |
745 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
746 | writes the result back to the bit field in the 16-bit port.\r | |
747 | \r | |
748 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
749 | bitwise inclusive OR between the read result and the value specified by\r | |
750 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
751 | specified by Address. The value written to the PCI configuration register is\r | |
752 | returned. This function must guarantee that all PCI read and write operations\r | |
753 | are serialized. Extra left bits in OrData are stripped.\r | |
754 | \r | |
755 | If any reserved bits in Address are set, then ASSERT().\r | |
756 | If StartBit is greater than 15, then ASSERT().\r | |
757 | If EndBit is greater than 15, then ASSERT().\r | |
758 | If EndBit is less than StartBit, then ASSERT().\r | |
759 | \r | |
760 | @param Address PCI configuration register to write.\r | |
761 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
762 | Range 0..15.\r | |
763 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
764 | Range 0..15.\r | |
765 | @param OrData The value to OR with the PCI configuration register.\r | |
766 | \r | |
767 | @return The value written back to the PCI configuration register.\r | |
768 | \r | |
769 | **/\r | |
770 | UINT16\r | |
771 | EFIAPI\r | |
772 | PciSegmentBitFieldOr16 (\r | |
773 | IN UINT64 Address,\r | |
774 | IN UINTN StartBit,\r | |
775 | IN UINTN EndBit,\r | |
776 | IN UINT16 OrData\r | |
777 | )\r | |
778 | {\r | |
779 | return PciSegmentWrite16 (\r | |
780 | Address,\r | |
781 | BitFieldOr16 (PciSegmentRead16 (Address), StartBit, EndBit, OrData)\r | |
782 | );\r | |
783 | }\r | |
784 | \r | |
785 | /**\r | |
786 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
787 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
788 | \r | |
789 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
790 | bitwise AND between the read result and the value specified by AndData, and\r | |
791 | writes the result to the 16-bit PCI configuration register specified by\r | |
792 | Address. The value written to the PCI configuration register is returned.\r | |
793 | This function must guarantee that all PCI read and write operations are\r | |
794 | serialized. Extra left bits in AndData are stripped.\r | |
795 | \r | |
796 | If any reserved bits in Address are set, then ASSERT().\r | |
797 | If StartBit is greater than 15, then ASSERT().\r | |
798 | If EndBit is greater than 15, then ASSERT().\r | |
799 | If EndBit is less than StartBit, then ASSERT().\r | |
800 | \r | |
801 | @param Address PCI configuration register to write.\r | |
802 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
803 | Range 0..15.\r | |
804 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
805 | Range 0..15.\r | |
806 | @param AndData The value to AND with the PCI configuration register.\r | |
807 | \r | |
808 | @return The value written back to the PCI configuration register.\r | |
809 | \r | |
810 | **/\r | |
811 | UINT16\r | |
812 | EFIAPI\r | |
813 | PciSegmentBitFieldAnd16 (\r | |
814 | IN UINT64 Address,\r | |
815 | IN UINTN StartBit,\r | |
816 | IN UINTN EndBit,\r | |
817 | IN UINT16 AndData\r | |
818 | )\r | |
819 | {\r | |
820 | return PciSegmentWrite16 (\r | |
821 | Address,\r | |
822 | BitFieldAnd16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData)\r | |
823 | );\r | |
824 | }\r | |
825 | \r | |
826 | /**\r | |
827 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
828 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
829 | 16-bit port.\r | |
830 | \r | |
831 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
832 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
833 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
834 | configuration register specified by Address. The value written to the PCI\r | |
835 | configuration register is returned. This function must guarantee that all PCI\r | |
836 | read and write operations are serialized. Extra left bits in both AndData and\r | |
837 | OrData are stripped.\r | |
838 | \r | |
839 | If any reserved bits in Address are set, then ASSERT().\r | |
840 | If StartBit is greater than 15, then ASSERT().\r | |
841 | If EndBit is greater than 15, then ASSERT().\r | |
842 | If EndBit is less than StartBit, then ASSERT().\r | |
843 | \r | |
844 | @param Address PCI configuration register to write.\r | |
845 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
846 | Range 0..15.\r | |
847 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
848 | Range 0..15.\r | |
849 | @param AndData The value to AND with the PCI configuration register.\r | |
850 | @param OrData The value to OR with the result of the AND operation.\r | |
851 | \r | |
852 | @return The value written back to the PCI configuration register.\r | |
853 | \r | |
854 | **/\r | |
855 | UINT16\r | |
856 | EFIAPI\r | |
857 | PciSegmentBitFieldAndThenOr16 (\r | |
858 | IN UINT64 Address,\r | |
859 | IN UINTN StartBit,\r | |
860 | IN UINTN EndBit,\r | |
861 | IN UINT16 AndData,\r | |
862 | IN UINT16 OrData\r | |
863 | )\r | |
864 | {\r | |
865 | return PciSegmentWrite16 (\r | |
866 | Address,\r | |
867 | BitFieldAndThenOr16 (PciSegmentRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
868 | );\r | |
869 | }\r | |
870 | \r | |
871 | /**\r | |
872 | Reads a 32-bit PCI configuration register.\r | |
873 | \r | |
874 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
875 | This function must guarantee that all PCI read and write operations are\r | |
876 | serialized.\r | |
877 | \r | |
878 | If any reserved bits in Address are set, then ASSERT().\r | |
879 | \r | |
880 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
881 | Register.\r | |
882 | \r | |
883 | @return The value read from the PCI configuration register.\r | |
884 | \r | |
885 | **/\r | |
886 | UINT32\r | |
887 | EFIAPI\r | |
888 | PciSegmentRead32 (\r | |
889 | IN UINT64 Address\r | |
890 | )\r | |
891 | {\r | |
892 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
893 | \r | |
894 | return PeiPciSegmentLibPciCfg2ReadWorker (Address, EfiPeiPciCfgWidthUint32);\r | |
895 | }\r | |
896 | \r | |
897 | /**\r | |
898 | Writes a 32-bit PCI configuration register.\r | |
899 | \r | |
900 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
901 | value specified by Value. Value is returned. This function must guarantee\r | |
902 | that all PCI read and write operations are serialized.\r | |
903 | \r | |
904 | If any reserved bits in Address are set, then ASSERT().\r | |
905 | \r | |
906 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
907 | Register.\r | |
908 | @param Data The value to write.\r | |
909 | \r | |
910 | @return The value written to the PCI configuration register.\r | |
911 | \r | |
912 | **/\r | |
913 | UINT32\r | |
914 | EFIAPI\r | |
915 | PciSegmentWrite32 (\r | |
916 | IN UINT64 Address,\r | |
917 | IN UINT32 Data\r | |
918 | )\r | |
919 | {\r | |
920 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (Address, 3);\r | |
921 | \r | |
922 | return PeiPciSegmentLibPciCfg2WriteWorker (Address, EfiPeiPciCfgWidthUint32, Data);\r | |
923 | }\r | |
924 | \r | |
925 | /**\r | |
926 | Performs a bitwise inclusive OR of a 32-bit PCI configuration register with\r | |
927 | a 32-bit value.\r | |
928 | \r | |
929 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
930 | bitwise inclusive OR between the read result and the value specified by\r | |
931 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
932 | specified by Address. The value written to the PCI configuration register is\r | |
933 | returned. This function must guarantee that all PCI read and write operations\r | |
934 | are serialized.\r | |
935 | \r | |
936 | If any reserved bits in Address are set, then ASSERT().\r | |
937 | \r | |
938 | @param Address Address that encodes the PCI Segment, Bus, Device, Function and\r | |
939 | Register.\r | |
940 | @param OrData The value to OR with the PCI configuration register.\r | |
941 | \r | |
942 | @return The value written back to the PCI configuration register.\r | |
943 | \r | |
944 | **/\r | |
945 | UINT32\r | |
946 | EFIAPI\r | |
947 | PciSegmentOr32 (\r | |
948 | IN UINT64 Address,\r | |
949 | IN UINT32 OrData\r | |
950 | )\r | |
951 | {\r | |
952 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) | OrData);\r | |
953 | }\r | |
954 | \r | |
955 | /**\r | |
122e2191 | 956 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value.\r |
1a3eaf06 | 957 | \r |
122e2191 | 958 | Reads the 32-bit PCI configuration register specified by Address,\r |
959 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
960 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
961 | The value written to the PCI configuration register is returned.\r | |
962 | This function must guarantee that all PCI read and write operations are serialized.\r | |
963 | \r | |
1a3eaf06 | 964 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 965 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 966 | \r |
122e2191 | 967 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
968 | @param AndData The value to AND with the PCI configuration register.\r | |
1a3eaf06 | 969 | \r |
122e2191 | 970 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 971 | \r |
972 | **/\r | |
973 | UINT32\r | |
974 | EFIAPI\r | |
975 | PciSegmentAnd32 (\r | |
976 | IN UINT64 Address,\r | |
977 | IN UINT32 AndData\r | |
978 | )\r | |
979 | {\r | |
980 | return PciSegmentWrite32 (Address, PciSegmentRead32 (Address) & AndData);\r | |
981 | }\r | |
982 | \r | |
983 | /**\r | |
122e2191 | 984 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit value,\r |
985 | followed a bitwise inclusive OR with another 32-bit value.\r | |
986 | \r | |
987 | Reads the 32-bit PCI configuration register specified by Address,\r | |
988 | performs a bitwise AND between the read result and the value specified by AndData,\r | |
989 | performs a bitwise inclusive OR between the result of the AND operation and the value specified by OrData,\r | |
990 | and writes the result to the 32-bit PCI configuration register specified by Address.\r | |
991 | The value written to the PCI configuration register is returned.\r | |
992 | This function must guarantee that all PCI read and write operations are serialized.\r | |
993 | \r | |
1a3eaf06 | 994 | If any reserved bits in Address are set, then ASSERT().\r |
122e2191 | 995 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r |
1a3eaf06 | 996 | \r |
122e2191 | 997 | @param Address Address that encodes the PCI Segment, Bus, Device, Function, and Register.\r |
998 | @param AndData The value to AND with the PCI configuration register.\r | |
999 | @param OrData The value to OR with the PCI configuration register.\r | |
1a3eaf06 | 1000 | \r |
122e2191 | 1001 | @return The value written to the PCI configuration register.\r |
1a3eaf06 | 1002 | \r |
1003 | **/\r | |
1004 | UINT32\r | |
1005 | EFIAPI\r | |
1006 | PciSegmentAndThenOr32 (\r | |
1007 | IN UINT64 Address,\r | |
1008 | IN UINT32 AndData,\r | |
1009 | IN UINT32 OrData\r | |
1010 | )\r | |
1011 | {\r | |
1012 | return PciSegmentWrite32 (Address, (PciSegmentRead32 (Address) & AndData) | OrData);\r | |
1013 | }\r | |
1014 | \r | |
1015 | /**\r | |
1016 | Reads a bit field of a PCI configuration register.\r | |
1017 | \r | |
1018 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1019 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1020 | returned.\r | |
1021 | \r | |
1022 | If any reserved bits in Address are set, then ASSERT().\r | |
1023 | If StartBit is greater than 31, then ASSERT().\r | |
1024 | If EndBit is greater than 31, then ASSERT().\r | |
1025 | If EndBit is less than StartBit, then ASSERT().\r | |
1026 | \r | |
1027 | @param Address PCI configuration register to read.\r | |
1028 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1029 | Range 0..31.\r | |
1030 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1031 | Range 0..31.\r | |
1032 | \r | |
1033 | @return The value of the bit field read from the PCI configuration register.\r | |
1034 | \r | |
1035 | **/\r | |
1036 | UINT32\r | |
1037 | EFIAPI\r | |
1038 | PciSegmentBitFieldRead32 (\r | |
1039 | IN UINT64 Address,\r | |
1040 | IN UINTN StartBit,\r | |
1041 | IN UINTN EndBit\r | |
1042 | )\r | |
1043 | {\r | |
1044 | return BitFieldRead32 (PciSegmentRead32 (Address), StartBit, EndBit);\r | |
1045 | }\r | |
1046 | \r | |
1047 | /**\r | |
1048 | Writes a bit field to a PCI configuration register.\r | |
1049 | \r | |
1050 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1051 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1052 | destination PCI configuration register are preserved. The new value of the\r | |
1053 | 32-bit register is returned.\r | |
1054 | \r | |
1055 | If any reserved bits in Address are set, then ASSERT().\r | |
1056 | If StartBit is greater than 31, then ASSERT().\r | |
1057 | If EndBit is greater than 31, then ASSERT().\r | |
1058 | If EndBit is less than StartBit, then ASSERT().\r | |
1059 | \r | |
1060 | @param Address PCI configuration register to write.\r | |
1061 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1062 | Range 0..31.\r | |
1063 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1064 | Range 0..31.\r | |
1065 | @param Value New value of the bit field.\r | |
1066 | \r | |
1067 | @return The value written back to the PCI configuration register.\r | |
1068 | \r | |
1069 | **/\r | |
1070 | UINT32\r | |
1071 | EFIAPI\r | |
1072 | PciSegmentBitFieldWrite32 (\r | |
1073 | IN UINT64 Address,\r | |
1074 | IN UINTN StartBit,\r | |
1075 | IN UINTN EndBit,\r | |
1076 | IN UINT32 Value\r | |
1077 | )\r | |
1078 | {\r | |
1079 | return PciSegmentWrite32 (\r | |
1080 | Address,\r | |
1081 | BitFieldWrite32 (PciSegmentRead32 (Address), StartBit, EndBit, Value)\r | |
1082 | );\r | |
1083 | }\r | |
1084 | \r | |
1085 | /**\r | |
1086 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1087 | writes the result back to the bit field in the 32-bit port.\r | |
1088 | \r | |
1089 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1090 | bitwise inclusive OR between the read result and the value specified by\r | |
1091 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
1092 | specified by Address. The value written to the PCI configuration register is\r | |
1093 | returned. This function must guarantee that all PCI read and write operations\r | |
1094 | are serialized. Extra left bits in OrData are stripped.\r | |
1095 | \r | |
1096 | If any reserved bits in Address are set, then ASSERT().\r | |
1097 | If StartBit is greater than 31, then ASSERT().\r | |
1098 | If EndBit is greater than 31, then ASSERT().\r | |
1099 | If EndBit is less than StartBit, then ASSERT().\r | |
1100 | \r | |
1101 | @param Address PCI configuration register to write.\r | |
1102 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1103 | Range 0..31.\r | |
1104 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1105 | Range 0..31.\r | |
1106 | @param OrData The value to OR with the PCI configuration register.\r | |
1107 | \r | |
1108 | @return The value written back to the PCI configuration register.\r | |
1109 | \r | |
1110 | **/\r | |
1111 | UINT32\r | |
1112 | EFIAPI\r | |
1113 | PciSegmentBitFieldOr32 (\r | |
1114 | IN UINT64 Address,\r | |
1115 | IN UINTN StartBit,\r | |
1116 | IN UINTN EndBit,\r | |
1117 | IN UINT32 OrData\r | |
1118 | )\r | |
1119 | {\r | |
1120 | return PciSegmentWrite32 (\r | |
1121 | Address,\r | |
1122 | BitFieldOr32 (PciSegmentRead32 (Address), StartBit, EndBit, OrData)\r | |
1123 | );\r | |
1124 | }\r | |
1125 | \r | |
1126 | /**\r | |
1127 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1128 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1129 | \r | |
1130 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1131 | bitwise AND between the read result and the value specified by AndData, and\r | |
1132 | writes the result to the 32-bit PCI configuration register specified by\r | |
1133 | Address. The value written to the PCI configuration register is returned.\r | |
1134 | This function must guarantee that all PCI read and write operations are\r | |
1135 | serialized. Extra left bits in AndData are stripped.\r | |
1136 | \r | |
1137 | If any reserved bits in Address are set, then ASSERT().\r | |
1138 | If StartBit is greater than 31, then ASSERT().\r | |
1139 | If EndBit is greater than 31, then ASSERT().\r | |
1140 | If EndBit is less than StartBit, then ASSERT().\r | |
1141 | \r | |
1142 | @param Address PCI configuration register to write.\r | |
1143 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1144 | Range 0..31.\r | |
1145 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1146 | Range 0..31.\r | |
1147 | @param AndData The value to AND with the PCI configuration register.\r | |
1148 | \r | |
1149 | @return The value written back to the PCI configuration register.\r | |
1150 | \r | |
1151 | **/\r | |
1152 | UINT32\r | |
1153 | EFIAPI\r | |
1154 | PciSegmentBitFieldAnd32 (\r | |
1155 | IN UINT64 Address,\r | |
1156 | IN UINTN StartBit,\r | |
1157 | IN UINTN EndBit,\r | |
1158 | IN UINT32 AndData\r | |
1159 | )\r | |
1160 | {\r | |
1161 | return PciSegmentWrite32 (\r | |
1162 | Address,\r | |
1163 | BitFieldAnd32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData)\r | |
1164 | );\r | |
1165 | }\r | |
1166 | \r | |
1167 | /**\r | |
1168 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
1169 | bitwise inclusive OR, and writes the result back to the bit field in the\r | |
1170 | 32-bit port.\r | |
1171 | \r | |
1172 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1173 | bitwise AND followed by a bitwise inclusive OR between the read result and\r | |
1174 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
1175 | configuration register specified by Address. The value written to the PCI\r | |
1176 | configuration register is returned. This function must guarantee that all PCI\r | |
1177 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1178 | OrData are stripped.\r | |
1179 | \r | |
1180 | If any reserved bits in Address are set, then ASSERT().\r | |
1181 | If StartBit is greater than 31, then ASSERT().\r | |
1182 | If EndBit is greater than 31, then ASSERT().\r | |
1183 | If EndBit is less than StartBit, then ASSERT().\r | |
1184 | \r | |
1185 | @param Address PCI configuration register to write.\r | |
1186 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1187 | Range 0..31.\r | |
1188 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1189 | Range 0..31.\r | |
1190 | @param AndData The value to AND with the PCI configuration register.\r | |
1191 | @param OrData The value to OR with the result of the AND operation.\r | |
1192 | \r | |
1193 | @return The value written back to the PCI configuration register.\r | |
1194 | \r | |
1195 | **/\r | |
1196 | UINT32\r | |
1197 | EFIAPI\r | |
1198 | PciSegmentBitFieldAndThenOr32 (\r | |
1199 | IN UINT64 Address,\r | |
1200 | IN UINTN StartBit,\r | |
1201 | IN UINTN EndBit,\r | |
1202 | IN UINT32 AndData,\r | |
1203 | IN UINT32 OrData\r | |
1204 | )\r | |
1205 | {\r | |
1206 | return PciSegmentWrite32 (\r | |
1207 | Address,\r | |
1208 | BitFieldAndThenOr32 (PciSegmentRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1209 | );\r | |
1210 | }\r | |
1211 | \r | |
1212 | /**\r | |
1213 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1214 | \r | |
1215 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1216 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1217 | configuration registers from a single PCI function to be read. Size is\r | |
1218 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1219 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1220 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1221 | end of the range.\r | |
1222 | \r | |
1223 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1224 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1225 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1226 | \r | |
e43e4b3e | 1227 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
1a3eaf06 | 1228 | Function and Register.\r |
1229 | @param Size Size in bytes of the transfer.\r | |
1230 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1231 | \r | |
1232 | @return Size\r | |
1233 | \r | |
1234 | **/\r | |
1235 | UINTN\r | |
1236 | EFIAPI\r | |
1237 | PciSegmentReadBuffer (\r | |
1238 | IN UINT64 StartAddress,\r | |
1239 | IN UINTN Size,\r | |
1240 | OUT VOID *Buffer\r | |
1241 | )\r | |
1242 | {\r | |
1243 | UINTN ReturnValue;\r | |
1244 | \r | |
1245 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1246 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1247 | \r | |
1248 | if (Size == 0) {\r | |
1249 | return Size;\r | |
1250 | }\r | |
1251 | \r | |
1252 | ASSERT (Buffer != NULL);\r | |
1253 | \r | |
1254 | //\r | |
1255 | // Save Size for return\r | |
1256 | //\r | |
1257 | ReturnValue = Size;\r | |
1258 | \r | |
e43e4b3e | 1259 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1260 | //\r |
1261 | // Read a byte if StartAddress is byte aligned\r | |
1262 | //\r | |
1263 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1264 | StartAddress += sizeof (UINT8);\r | |
1265 | Size -= sizeof (UINT8);\r | |
1266 | Buffer = (UINT8*)Buffer + 1;\r | |
1267 | }\r | |
1268 | \r | |
e43e4b3e | 1269 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1270 | //\r |
1271 | // Read a word if StartAddress is word aligned\r | |
1272 | //\r | |
1273 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r | |
1274 | StartAddress += sizeof (UINT16);\r | |
1275 | Size -= sizeof (UINT16);\r | |
1276 | Buffer = (UINT16*)Buffer + 1;\r | |
1277 | }\r | |
1278 | \r | |
1279 | while (Size >= sizeof (UINT32)) {\r | |
1280 | //\r | |
1281 | // Read as many double words as possible\r | |
1282 | //\r | |
1283 | *(volatile UINT32 *)Buffer = PciSegmentRead32 (StartAddress);\r | |
1284 | StartAddress += sizeof (UINT32);\r | |
1285 | Size -= sizeof (UINT32);\r | |
1286 | Buffer = (UINT32*)Buffer + 1;\r | |
1287 | }\r | |
1288 | \r | |
1289 | if (Size >= sizeof (UINT16)) {\r | |
1290 | //\r | |
1291 | // Read the last remaining word if exist\r | |
1292 | //\r | |
1293 | *(volatile UINT16 *)Buffer = PciSegmentRead16 (StartAddress);\r | |
1294 | StartAddress += sizeof (UINT16);\r | |
1295 | Size -= sizeof (UINT16);\r | |
1296 | Buffer = (UINT16*)Buffer + 1;\r | |
1297 | }\r | |
1298 | \r | |
1299 | if (Size >= sizeof (UINT8)) {\r | |
1300 | //\r | |
1301 | // Read the last remaining byte if exist\r | |
1302 | //\r | |
1303 | *(volatile UINT8 *)Buffer = PciSegmentRead8 (StartAddress);\r | |
1304 | }\r | |
1305 | \r | |
1306 | return ReturnValue;\r | |
1307 | }\r | |
1308 | \r | |
1309 | /**\r | |
1310 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1311 | configuration space.\r | |
1312 | \r | |
1313 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1314 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1315 | configuration registers from a single PCI function to be written. Size is\r | |
1316 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1317 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1318 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1319 | and the end of the range.\r | |
1320 | \r | |
1321 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1322 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1323 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1324 | \r | |
e43e4b3e | 1325 | @param StartAddress Starting address that encodes the PCI Segment, Bus, Device,\r |
1a3eaf06 | 1326 | Function and Register.\r |
1327 | @param Size Size in bytes of the transfer.\r | |
1328 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1329 | \r | |
1330 | @return Size\r | |
1331 | \r | |
1332 | **/\r | |
1333 | UINTN\r | |
1334 | EFIAPI\r | |
1335 | PciSegmentWriteBuffer (\r | |
1336 | IN UINT64 StartAddress,\r | |
1337 | IN UINTN Size,\r | |
1338 | IN VOID *Buffer\r | |
1339 | )\r | |
1340 | {\r | |
1341 | UINTN ReturnValue;\r | |
1342 | \r | |
1343 | ASSERT_INVALID_PCI_SEGMENT_ADDRESS (StartAddress, 0);\r | |
1344 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r | |
1345 | \r | |
1346 | if (Size == 0) {\r | |
1347 | return 0;\r | |
1348 | }\r | |
1349 | \r | |
1350 | ASSERT (Buffer != NULL);\r | |
1351 | \r | |
1352 | //\r | |
1353 | // Save Size for return\r | |
1354 | //\r | |
1355 | ReturnValue = Size;\r | |
1356 | \r | |
e43e4b3e | 1357 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1358 | //\r |
1359 | // Write a byte if StartAddress is byte aligned\r | |
1360 | //\r | |
1361 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1362 | StartAddress += sizeof (UINT8);\r | |
1363 | Size -= sizeof (UINT8);\r | |
1364 | Buffer = (UINT8*)Buffer + 1;\r | |
1365 | }\r | |
1366 | \r | |
e43e4b3e | 1367 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1368 | //\r |
1369 | // Write a word if StartAddress is word aligned\r | |
1370 | //\r | |
1371 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1372 | StartAddress += sizeof (UINT16);\r | |
1373 | Size -= sizeof (UINT16);\r | |
1374 | Buffer = (UINT16*)Buffer + 1;\r | |
1375 | }\r | |
1376 | \r | |
1377 | while (Size >= sizeof (UINT32)) {\r | |
1378 | //\r | |
1379 | // Write as many double words as possible\r | |
1380 | //\r | |
1381 | PciSegmentWrite32 (StartAddress, *(UINT32*)Buffer);\r | |
1382 | StartAddress += sizeof (UINT32);\r | |
1383 | Size -= sizeof (UINT32);\r | |
1384 | Buffer = (UINT32*)Buffer + 1;\r | |
1385 | }\r | |
1386 | \r | |
1387 | if (Size >= sizeof (UINT16)) {\r | |
1388 | //\r | |
1389 | // Write the last remaining word if exist\r | |
1390 | //\r | |
1391 | PciSegmentWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1392 | StartAddress += sizeof (UINT16);\r | |
1393 | Size -= sizeof (UINT16);\r | |
1394 | Buffer = (UINT16*)Buffer + 1;\r | |
1395 | }\r | |
1396 | \r | |
1397 | if (Size >= sizeof (UINT8)) {\r | |
1398 | //\r | |
1399 | // Write the last remaining byte if exist\r | |
1400 | //\r | |
1401 | PciSegmentWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1402 | }\r | |
1403 | \r | |
1404 | return ReturnValue;\r | |
1405 | }\r |