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1a3eaf06 | 1 | /** @file\r |
2 | PCI Library using PCI Root Bridge I/O Protocol.\r | |
3 | \r | |
4 | Copyright (c) 2007 - 2008, Intel Corporation All rights\r | |
5 | reserved. This program and the accompanying materials are\r | |
6 | licensed and made available under the terms and conditions of\r | |
7 | the BSD License which accompanies this distribution. The full\r | |
8 | text of the license may be found at\r | |
9 | http://opensource.org/licenses/bsd-license.php\r | |
10 | \r | |
11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
13 | \r | |
14 | **/\r | |
15 | \r | |
16 | #include <PiDxe.h>\r | |
17 | \r | |
18 | #include <Protocol/PciRootBridgeIo.h>\r | |
19 | \r | |
20 | #include <Library/PciLib.h>\r | |
21 | #include <Library/BaseLib.h>\r | |
22 | #include <Library/UefiBootServicesTableLib.h>\r | |
23 | #include <Library/DebugLib.h>\r | |
24 | \r | |
25 | /**\r | |
26 | Assert the validity of a PCI address. A valid PCI address should contain 1's\r | |
27 | only in the low 28 bits.\r | |
28 | \r | |
29 | @param A The address to validate.\r | |
30 | @param M Additional bits to assert to be zero.\r | |
31 | \r | |
32 | **/\r | |
33 | #define ASSERT_INVALID_PCI_ADDRESS(A,M) \\r | |
34 | ASSERT (((A) & (~0xfffffff | (M))) == 0)\r | |
35 | \r | |
36 | /**\r | |
e43e4b3e | 37 | Translate PCI Lib address into format of PCI Root Bridge I/O Protocol.\r |
1a3eaf06 | 38 | \r |
39 | @param A Address that encodes the PCI Bus, Device, Function and\r | |
40 | Register.\r | |
41 | \r | |
42 | **/\r | |
e43e4b3e | 43 | #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r |
44 | ((((A) << 4) & 0xff000000) | (((A) >> 4) & 0x00000700) | (((A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r | |
1a3eaf06 | 45 | \r |
46 | //\r | |
47 | // Global varible to cache pointer to PCI Root Bridge I/O protocol.\r | |
48 | //\r | |
49 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *mPciRootBridgeIo = NULL; \r | |
50 | \r | |
51 | /**\r | |
52 | The constructor function caches the pointer to PCI Root Bridge I/O protocol.\r | |
53 | \r | |
54 | The constructor function locates PCI Root Bridge I/O protocol from protocol database.\r | |
55 | It will ASSERT() if that operation fails and it will always return EFI_SUCCESS. \r | |
56 | \r | |
57 | @param ImageHandle The firmware allocated handle for the EFI image.\r | |
58 | @param SystemTable A pointer to the EFI System Table.\r | |
59 | \r | |
60 | @retval EFI_SUCCESS The constructor always returns EFI_SUCCESS.\r | |
61 | \r | |
62 | **/\r | |
63 | EFI_STATUS\r | |
64 | EFIAPI\r | |
65 | PciLibConstructor (\r | |
66 | IN EFI_HANDLE ImageHandle,\r | |
67 | IN EFI_SYSTEM_TABLE *SystemTable\r | |
68 | )\r | |
69 | {\r | |
70 | EFI_STATUS Status;\r | |
71 | \r | |
72 | Status = gBS->LocateProtocol (&gEfiPciRootBridgeIoProtocolGuid, NULL, (VOID**) &mPciRootBridgeIo);\r | |
73 | ASSERT_EFI_ERROR (Status);\r | |
74 | ASSERT (mPciRootBridgeIo != NULL);\r | |
75 | \r | |
76 | return EFI_SUCCESS;\r | |
77 | }\r | |
78 | \r | |
79 | /**\r | |
80 | Internal worker function to read a PCI configuration register.\r | |
81 | \r | |
82 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Read() service.\r | |
83 | It reads and returns the PCI configuration register specified by Address,\r | |
84 | the width of data is specified by Width.\r | |
85 | \r | |
86 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
87 | Register.\r | |
88 | @param Width Width of data to read\r | |
89 | \r | |
90 | @return The value read from the PCI configuration register.\r | |
91 | \r | |
92 | **/\r | |
93 | UINT32\r | |
94 | DxePciLibPciRootBridgeIoReadWorker (\r | |
95 | IN UINTN Address,\r | |
96 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width\r | |
97 | )\r | |
98 | {\r | |
99 | UINT32 Data;\r | |
100 | \r | |
101 | mPciRootBridgeIo->Pci.Read (\r | |
102 | mPciRootBridgeIo,\r | |
103 | Width,\r | |
e43e4b3e | 104 | PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r |
1a3eaf06 | 105 | 1,\r |
106 | &Data\r | |
107 | );\r | |
108 | \r | |
109 | return Data;\r | |
110 | }\r | |
111 | \r | |
112 | /**\r | |
113 | Internal worker function to writes a PCI configuration register.\r | |
114 | \r | |
115 | This function wraps EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL.Pci.Write() service.\r | |
116 | It writes the PCI configuration register specified by Address with the\r | |
117 | value specified by Data. The width of data is specifed by Width.\r | |
118 | Data is returned.\r | |
119 | \r | |
120 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
121 | Register.\r | |
122 | @param Width Width of data to write\r | |
123 | @param Data The value to write.\r | |
124 | \r | |
125 | @return The value written to the PCI configuration register.\r | |
126 | \r | |
127 | **/\r | |
128 | UINT32\r | |
129 | DxePciLibPciRootBridgeIoWriteWorker (\r | |
130 | IN UINTN Address,\r | |
131 | IN EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH Width,\r | |
132 | IN UINT32 Data\r | |
133 | )\r | |
134 | {\r | |
135 | mPciRootBridgeIo->Pci.Write (\r | |
136 | mPciRootBridgeIo,\r | |
137 | Width,\r | |
e43e4b3e | 138 | PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS (Address),\r |
1a3eaf06 | 139 | 1,\r |
140 | &Data\r | |
141 | );\r | |
142 | return Data;\r | |
143 | }\r | |
144 | \r | |
3e3ae634 | 145 | /**\r |
146 | Register a PCI device so PCI configuration registers may be accessed after \r | |
147 | SetVirtualAddressMap().\r | |
148 | \r | |
149 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
150 | \r | |
151 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
152 | Register.\r | |
153 | \r | |
154 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
155 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
156 | after ExitBootServices().\r | |
157 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
158 | at runtime could not be mapped.\r | |
159 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
160 | complete the registration.\r | |
161 | \r | |
162 | **/\r | |
163 | RETURN_STATUS\r | |
164 | EFIAPI\r | |
165 | PciRegisterForRuntimeAccess (\r | |
166 | IN UINTN Address\r | |
167 | )\r | |
168 | {\r | |
169 | return RETURN_UNSUPPORTED;\r | |
170 | }\r | |
171 | \r | |
1a3eaf06 | 172 | /**\r |
173 | Reads an 8-bit PCI configuration register.\r | |
174 | \r | |
175 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
176 | This function must guarantee that all PCI read and write operations are\r | |
177 | serialized.\r | |
178 | \r | |
179 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
180 | \r | |
181 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
182 | Register.\r | |
183 | \r | |
184 | @return The value read from the PCI configuration register.\r | |
185 | \r | |
186 | **/\r | |
187 | UINT8\r | |
188 | EFIAPI\r | |
189 | PciRead8 (\r | |
190 | IN UINTN Address\r | |
191 | )\r | |
192 | {\r | |
193 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
194 | \r | |
195 | return (UINT8) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint8);\r | |
196 | }\r | |
197 | \r | |
198 | /**\r | |
199 | Writes an 8-bit PCI configuration register.\r | |
200 | \r | |
201 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
202 | value specified by Value. Value is returned. This function must guarantee\r | |
203 | that all PCI read and write operations are serialized.\r | |
204 | \r | |
205 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
206 | \r | |
207 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
208 | Register.\r | |
209 | @param Data The value to write.\r | |
210 | \r | |
211 | @return The value written to the PCI configuration register.\r | |
212 | \r | |
213 | **/\r | |
214 | UINT8\r | |
215 | EFIAPI\r | |
216 | PciWrite8 (\r | |
217 | IN UINTN Address,\r | |
218 | IN UINT8 Data\r | |
219 | )\r | |
220 | {\r | |
221 | ASSERT_INVALID_PCI_ADDRESS (Address, 0);\r | |
222 | \r | |
223 | return (UINT8) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint8, Data);\r | |
224 | }\r | |
225 | \r | |
226 | /**\r | |
62991af2 | 227 | Performs a bitwise OR of an 8-bit PCI configuration register with\r |
1a3eaf06 | 228 | an 8-bit value.\r |
229 | \r | |
230 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 231 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 232 | OrData, and writes the result to the 8-bit PCI configuration register\r |
233 | specified by Address. The value written to the PCI configuration register is\r | |
234 | returned. This function must guarantee that all PCI read and write operations\r | |
235 | are serialized.\r | |
236 | \r | |
237 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
238 | \r | |
239 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
240 | Register.\r | |
241 | @param OrData The value to OR with the PCI configuration register.\r | |
242 | \r | |
243 | @return The value written back to the PCI configuration register.\r | |
244 | \r | |
245 | **/\r | |
246 | UINT8\r | |
247 | EFIAPI\r | |
248 | PciOr8 (\r | |
249 | IN UINTN Address,\r | |
250 | IN UINT8 OrData\r | |
251 | )\r | |
252 | {\r | |
253 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) | OrData));\r | |
254 | }\r | |
255 | \r | |
256 | /**\r | |
257 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
258 | value.\r | |
259 | \r | |
260 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
261 | bitwise AND between the read result and the value specified by AndData, and\r | |
262 | writes the result to the 8-bit PCI configuration register specified by\r | |
263 | Address. The value written to the PCI configuration register is returned.\r | |
264 | This function must guarantee that all PCI read and write operations are\r | |
265 | serialized.\r | |
266 | \r | |
267 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
268 | \r | |
269 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
270 | Register.\r | |
271 | @param AndData The value to AND with the PCI configuration register.\r | |
272 | \r | |
273 | @return The value written back to the PCI configuration register.\r | |
274 | \r | |
275 | **/\r | |
276 | UINT8\r | |
277 | EFIAPI\r | |
278 | PciAnd8 (\r | |
279 | IN UINTN Address,\r | |
280 | IN UINT8 AndData\r | |
281 | )\r | |
282 | {\r | |
283 | return PciWrite8 (Address, (UINT8) (PciRead8 (Address) & AndData));\r | |
284 | }\r | |
285 | \r | |
286 | /**\r | |
287 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
62991af2 | 288 | value, followed a bitwise OR with another 8-bit value.\r |
1a3eaf06 | 289 | \r |
290 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
291 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 292 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 293 | the value specified by OrData, and writes the result to the 8-bit PCI\r |
294 | configuration register specified by Address. The value written to the PCI\r | |
295 | configuration register is returned. This function must guarantee that all PCI\r | |
296 | read and write operations are serialized.\r | |
297 | \r | |
298 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
299 | \r | |
300 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
301 | Register.\r | |
302 | @param AndData The value to AND with the PCI configuration register.\r | |
303 | @param OrData The value to OR with the result of the AND operation.\r | |
304 | \r | |
305 | @return The value written back to the PCI configuration register.\r | |
306 | \r | |
307 | **/\r | |
308 | UINT8\r | |
309 | EFIAPI\r | |
310 | PciAndThenOr8 (\r | |
311 | IN UINTN Address,\r | |
312 | IN UINT8 AndData,\r | |
313 | IN UINT8 OrData\r | |
314 | )\r | |
315 | {\r | |
316 | return PciWrite8 (Address, (UINT8) ((PciRead8 (Address) & AndData) | OrData));\r | |
317 | }\r | |
318 | \r | |
319 | /**\r | |
320 | Reads a bit field of a PCI configuration register.\r | |
321 | \r | |
322 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
323 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
324 | returned.\r | |
325 | \r | |
326 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
327 | If StartBit is greater than 7, then ASSERT().\r | |
328 | If EndBit is greater than 7, then ASSERT().\r | |
329 | If EndBit is less than StartBit, then ASSERT().\r | |
330 | \r | |
331 | @param Address PCI configuration register to read.\r | |
332 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
333 | Range 0..7.\r | |
334 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
335 | Range 0..7.\r | |
336 | \r | |
337 | @return The value of the bit field read from the PCI configuration register.\r | |
338 | \r | |
339 | **/\r | |
340 | UINT8\r | |
341 | EFIAPI\r | |
342 | PciBitFieldRead8 (\r | |
343 | IN UINTN Address,\r | |
344 | IN UINTN StartBit,\r | |
345 | IN UINTN EndBit\r | |
346 | )\r | |
347 | {\r | |
348 | return BitFieldRead8 (PciRead8 (Address), StartBit, EndBit);\r | |
349 | }\r | |
350 | \r | |
351 | /**\r | |
352 | Writes a bit field to a PCI configuration register.\r | |
353 | \r | |
354 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
355 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
356 | destination PCI configuration register are preserved. The new value of the\r | |
357 | 8-bit register is returned.\r | |
358 | \r | |
359 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
360 | If StartBit is greater than 7, then ASSERT().\r | |
361 | If EndBit is greater than 7, then ASSERT().\r | |
362 | If EndBit is less than StartBit, then ASSERT().\r | |
363 | \r | |
364 | @param Address PCI configuration register to write.\r | |
365 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
366 | Range 0..7.\r | |
367 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
368 | Range 0..7.\r | |
369 | @param Value New value of the bit field.\r | |
370 | \r | |
371 | @return The value written back to the PCI configuration register.\r | |
372 | \r | |
373 | **/\r | |
374 | UINT8\r | |
375 | EFIAPI\r | |
376 | PciBitFieldWrite8 (\r | |
377 | IN UINTN Address,\r | |
378 | IN UINTN StartBit,\r | |
379 | IN UINTN EndBit,\r | |
380 | IN UINT8 Value\r | |
381 | )\r | |
382 | {\r | |
383 | return PciWrite8 (\r | |
384 | Address,\r | |
385 | BitFieldWrite8 (PciRead8 (Address), StartBit, EndBit, Value)\r | |
386 | );\r | |
387 | }\r | |
388 | \r | |
389 | /**\r | |
390 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
391 | writes the result back to the bit field in the 8-bit port.\r | |
392 | \r | |
393 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 394 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 395 | OrData, and writes the result to the 8-bit PCI configuration register\r |
396 | specified by Address. The value written to the PCI configuration register is\r | |
397 | returned. This function must guarantee that all PCI read and write operations\r | |
398 | are serialized. Extra left bits in OrData are stripped.\r | |
399 | \r | |
400 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
401 | If StartBit is greater than 7, then ASSERT().\r | |
402 | If EndBit is greater than 7, then ASSERT().\r | |
403 | If EndBit is less than StartBit, then ASSERT().\r | |
404 | \r | |
405 | @param Address PCI configuration register to write.\r | |
406 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
407 | Range 0..7.\r | |
408 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
409 | Range 0..7.\r | |
410 | @param OrData The value to OR with the PCI configuration register.\r | |
411 | \r | |
412 | @return The value written back to the PCI configuration register.\r | |
413 | \r | |
414 | **/\r | |
415 | UINT8\r | |
416 | EFIAPI\r | |
417 | PciBitFieldOr8 (\r | |
418 | IN UINTN Address,\r | |
419 | IN UINTN StartBit,\r | |
420 | IN UINTN EndBit,\r | |
421 | IN UINT8 OrData\r | |
422 | )\r | |
423 | {\r | |
424 | return PciWrite8 (\r | |
425 | Address,\r | |
426 | BitFieldOr8 (PciRead8 (Address), StartBit, EndBit, OrData)\r | |
427 | );\r | |
428 | }\r | |
429 | \r | |
430 | /**\r | |
431 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
432 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
433 | \r | |
434 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
435 | bitwise AND between the read result and the value specified by AndData, and\r | |
436 | writes the result to the 8-bit PCI configuration register specified by\r | |
437 | Address. The value written to the PCI configuration register is returned.\r | |
438 | This function must guarantee that all PCI read and write operations are\r | |
439 | serialized. Extra left bits in AndData are stripped.\r | |
440 | \r | |
441 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
442 | If StartBit is greater than 7, then ASSERT().\r | |
443 | If EndBit is greater than 7, then ASSERT().\r | |
444 | If EndBit is less than StartBit, then ASSERT().\r | |
445 | \r | |
446 | @param Address PCI configuration register to write.\r | |
447 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
448 | Range 0..7.\r | |
449 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
450 | Range 0..7.\r | |
451 | @param AndData The value to AND with the PCI configuration register.\r | |
452 | \r | |
453 | @return The value written back to the PCI configuration register.\r | |
454 | \r | |
455 | **/\r | |
456 | UINT8\r | |
457 | EFIAPI\r | |
458 | PciBitFieldAnd8 (\r | |
459 | IN UINTN Address,\r | |
460 | IN UINTN StartBit,\r | |
461 | IN UINTN EndBit,\r | |
462 | IN UINT8 AndData\r | |
463 | )\r | |
464 | {\r | |
465 | return PciWrite8 (\r | |
466 | Address,\r | |
467 | BitFieldAnd8 (PciRead8 (Address), StartBit, EndBit, AndData)\r | |
468 | );\r | |
469 | }\r | |
470 | \r | |
471 | /**\r | |
472 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 473 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 474 | 8-bit port.\r |
475 | \r | |
476 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 477 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 478 | the value specified by AndData, and writes the result to the 8-bit PCI\r |
479 | configuration register specified by Address. The value written to the PCI\r | |
480 | configuration register is returned. This function must guarantee that all PCI\r | |
481 | read and write operations are serialized. Extra left bits in both AndData and\r | |
482 | OrData are stripped.\r | |
483 | \r | |
484 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
485 | If StartBit is greater than 7, then ASSERT().\r | |
486 | If EndBit is greater than 7, then ASSERT().\r | |
487 | If EndBit is less than StartBit, then ASSERT().\r | |
488 | \r | |
489 | @param Address PCI configuration register to write.\r | |
490 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
491 | Range 0..7.\r | |
492 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
493 | Range 0..7.\r | |
494 | @param AndData The value to AND with the PCI configuration register.\r | |
495 | @param OrData The value to OR with the result of the AND operation.\r | |
496 | \r | |
497 | @return The value written back to the PCI configuration register.\r | |
498 | \r | |
499 | **/\r | |
500 | UINT8\r | |
501 | EFIAPI\r | |
502 | PciBitFieldAndThenOr8 (\r | |
503 | IN UINTN Address,\r | |
504 | IN UINTN StartBit,\r | |
505 | IN UINTN EndBit,\r | |
506 | IN UINT8 AndData,\r | |
507 | IN UINT8 OrData\r | |
508 | )\r | |
509 | {\r | |
510 | return PciWrite8 (\r | |
511 | Address,\r | |
512 | BitFieldAndThenOr8 (PciRead8 (Address), StartBit, EndBit, AndData, OrData)\r | |
513 | );\r | |
514 | }\r | |
515 | \r | |
516 | /**\r | |
517 | Reads a 16-bit PCI configuration register.\r | |
518 | \r | |
519 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
520 | This function must guarantee that all PCI read and write operations are\r | |
521 | serialized.\r | |
522 | \r | |
523 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
524 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
525 | \r | |
526 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
527 | Register.\r | |
528 | \r | |
529 | @return The value read from the PCI configuration register.\r | |
530 | \r | |
531 | **/\r | |
532 | UINT16\r | |
533 | EFIAPI\r | |
534 | PciRead16 (\r | |
535 | IN UINTN Address\r | |
536 | )\r | |
537 | {\r | |
538 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
539 | \r | |
540 | return (UINT16) DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint16);\r | |
541 | }\r | |
542 | \r | |
543 | /**\r | |
544 | Writes a 16-bit PCI configuration register.\r | |
545 | \r | |
546 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
547 | value specified by Value. Value is returned. This function must guarantee\r | |
548 | that all PCI read and write operations are serialized.\r | |
549 | \r | |
550 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
551 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
552 | \r | |
553 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
554 | Register.\r | |
555 | @param Data The value to write.\r | |
556 | \r | |
557 | @return The value written to the PCI configuration register.\r | |
558 | \r | |
559 | **/\r | |
560 | UINT16\r | |
561 | EFIAPI\r | |
562 | PciWrite16 (\r | |
563 | IN UINTN Address,\r | |
564 | IN UINT16 Data\r | |
565 | )\r | |
566 | {\r | |
567 | ASSERT_INVALID_PCI_ADDRESS (Address, 1);\r | |
568 | \r | |
569 | return (UINT16) DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint16, Data);\r | |
570 | }\r | |
571 | \r | |
572 | /**\r | |
62991af2 | 573 | Performs a bitwise OR of a 16-bit PCI configuration register with\r |
1a3eaf06 | 574 | a 16-bit value.\r |
575 | \r | |
576 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 577 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 578 | OrData, and writes the result to the 16-bit PCI configuration register\r |
579 | specified by Address. The value written to the PCI configuration register is\r | |
580 | returned. This function must guarantee that all PCI read and write operations\r | |
581 | are serialized.\r | |
582 | \r | |
583 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
584 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
585 | \r | |
586 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
587 | Register.\r | |
588 | @param OrData The value to OR with the PCI configuration register.\r | |
589 | \r | |
590 | @return The value written back to the PCI configuration register.\r | |
591 | \r | |
592 | **/\r | |
593 | UINT16\r | |
594 | EFIAPI\r | |
595 | PciOr16 (\r | |
596 | IN UINTN Address,\r | |
597 | IN UINT16 OrData\r | |
598 | )\r | |
599 | {\r | |
600 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) | OrData));\r | |
601 | }\r | |
602 | \r | |
603 | /**\r | |
604 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
605 | value.\r | |
606 | \r | |
607 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
608 | bitwise AND between the read result and the value specified by AndData, and\r | |
609 | writes the result to the 16-bit PCI configuration register specified by\r | |
610 | Address. The value written to the PCI configuration register is returned.\r | |
611 | This function must guarantee that all PCI read and write operations are\r | |
612 | serialized.\r | |
613 | \r | |
614 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
615 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
616 | \r | |
617 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
618 | Register.\r | |
619 | @param AndData The value to AND with the PCI configuration register.\r | |
620 | \r | |
621 | @return The value written back to the PCI configuration register.\r | |
622 | \r | |
623 | **/\r | |
624 | UINT16\r | |
625 | EFIAPI\r | |
626 | PciAnd16 (\r | |
627 | IN UINTN Address,\r | |
628 | IN UINT16 AndData\r | |
629 | )\r | |
630 | {\r | |
631 | return PciWrite16 (Address, (UINT16) (PciRead16 (Address) & AndData));\r | |
632 | }\r | |
633 | \r | |
634 | /**\r | |
635 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
62991af2 | 636 | value, followed a bitwise OR with another 16-bit value.\r |
1a3eaf06 | 637 | \r |
638 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
639 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 640 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 641 | the value specified by OrData, and writes the result to the 16-bit PCI\r |
642 | configuration register specified by Address. The value written to the PCI\r | |
643 | configuration register is returned. This function must guarantee that all PCI\r | |
644 | read and write operations are serialized.\r | |
645 | \r | |
646 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
647 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
648 | \r | |
649 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
650 | Register.\r | |
651 | @param AndData The value to AND with the PCI configuration register.\r | |
652 | @param OrData The value to OR with the result of the AND operation.\r | |
653 | \r | |
654 | @return The value written back to the PCI configuration register.\r | |
655 | \r | |
656 | **/\r | |
657 | UINT16\r | |
658 | EFIAPI\r | |
659 | PciAndThenOr16 (\r | |
660 | IN UINTN Address,\r | |
661 | IN UINT16 AndData,\r | |
662 | IN UINT16 OrData\r | |
663 | )\r | |
664 | {\r | |
665 | return PciWrite16 (Address, (UINT16) ((PciRead16 (Address) & AndData) | OrData));\r | |
666 | }\r | |
667 | \r | |
668 | /**\r | |
669 | Reads a bit field of a PCI configuration register.\r | |
670 | \r | |
671 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
672 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
673 | returned.\r | |
674 | \r | |
675 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
676 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
677 | If StartBit is greater than 15, then ASSERT().\r | |
678 | If EndBit is greater than 15, then ASSERT().\r | |
679 | If EndBit is less than StartBit, then ASSERT().\r | |
680 | \r | |
681 | @param Address PCI configuration register to read.\r | |
682 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
683 | Range 0..15.\r | |
684 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
685 | Range 0..15.\r | |
686 | \r | |
687 | @return The value of the bit field read from the PCI configuration register.\r | |
688 | \r | |
689 | **/\r | |
690 | UINT16\r | |
691 | EFIAPI\r | |
692 | PciBitFieldRead16 (\r | |
693 | IN UINTN Address,\r | |
694 | IN UINTN StartBit,\r | |
695 | IN UINTN EndBit\r | |
696 | )\r | |
697 | {\r | |
698 | return BitFieldRead16 (PciRead16 (Address), StartBit, EndBit);\r | |
699 | }\r | |
700 | \r | |
701 | /**\r | |
702 | Writes a bit field to a PCI configuration register.\r | |
703 | \r | |
704 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
705 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
706 | destination PCI configuration register are preserved. The new value of the\r | |
707 | 16-bit register is returned.\r | |
708 | \r | |
709 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
710 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
711 | If StartBit is greater than 15, then ASSERT().\r | |
712 | If EndBit is greater than 15, then ASSERT().\r | |
713 | If EndBit is less than StartBit, then ASSERT().\r | |
714 | \r | |
715 | @param Address PCI configuration register to write.\r | |
716 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
717 | Range 0..15.\r | |
718 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
719 | Range 0..15.\r | |
720 | @param Value New value of the bit field.\r | |
721 | \r | |
722 | @return The value written back to the PCI configuration register.\r | |
723 | \r | |
724 | **/\r | |
725 | UINT16\r | |
726 | EFIAPI\r | |
727 | PciBitFieldWrite16 (\r | |
728 | IN UINTN Address,\r | |
729 | IN UINTN StartBit,\r | |
730 | IN UINTN EndBit,\r | |
731 | IN UINT16 Value\r | |
732 | )\r | |
733 | {\r | |
734 | return PciWrite16 (\r | |
735 | Address,\r | |
736 | BitFieldWrite16 (PciRead16 (Address), StartBit, EndBit, Value)\r | |
737 | );\r | |
738 | }\r | |
739 | \r | |
740 | /**\r | |
741 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
742 | writes the result back to the bit field in the 16-bit port.\r | |
743 | \r | |
744 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 745 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 746 | OrData, and writes the result to the 16-bit PCI configuration register\r |
747 | specified by Address. The value written to the PCI configuration register is\r | |
748 | returned. This function must guarantee that all PCI read and write operations\r | |
749 | are serialized. Extra left bits in OrData are stripped.\r | |
750 | \r | |
751 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
752 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
753 | If StartBit is greater than 15, then ASSERT().\r | |
754 | If EndBit is greater than 15, then ASSERT().\r | |
755 | If EndBit is less than StartBit, then ASSERT().\r | |
756 | \r | |
757 | @param Address PCI configuration register to write.\r | |
758 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
759 | Range 0..15.\r | |
760 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
761 | Range 0..15.\r | |
762 | @param OrData The value to OR with the PCI configuration register.\r | |
763 | \r | |
764 | @return The value written back to the PCI configuration register.\r | |
765 | \r | |
766 | **/\r | |
767 | UINT16\r | |
768 | EFIAPI\r | |
769 | PciBitFieldOr16 (\r | |
770 | IN UINTN Address,\r | |
771 | IN UINTN StartBit,\r | |
772 | IN UINTN EndBit,\r | |
773 | IN UINT16 OrData\r | |
774 | )\r | |
775 | {\r | |
776 | return PciWrite16 (\r | |
777 | Address,\r | |
778 | BitFieldOr16 (PciRead16 (Address), StartBit, EndBit, OrData)\r | |
779 | );\r | |
780 | }\r | |
781 | \r | |
782 | /**\r | |
783 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
784 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
785 | \r | |
786 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
787 | bitwise AND between the read result and the value specified by AndData, and\r | |
788 | writes the result to the 16-bit PCI configuration register specified by\r | |
789 | Address. The value written to the PCI configuration register is returned.\r | |
790 | This function must guarantee that all PCI read and write operations are\r | |
791 | serialized. Extra left bits in AndData are stripped.\r | |
792 | \r | |
793 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
794 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
795 | If StartBit is greater than 15, then ASSERT().\r | |
796 | If EndBit is greater than 15, then ASSERT().\r | |
797 | If EndBit is less than StartBit, then ASSERT().\r | |
798 | \r | |
799 | @param Address PCI configuration register to write.\r | |
800 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
801 | Range 0..15.\r | |
802 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
803 | Range 0..15.\r | |
804 | @param AndData The value to AND with the PCI configuration register.\r | |
805 | \r | |
806 | @return The value written back to the PCI configuration register.\r | |
807 | \r | |
808 | **/\r | |
809 | UINT16\r | |
810 | EFIAPI\r | |
811 | PciBitFieldAnd16 (\r | |
812 | IN UINTN Address,\r | |
813 | IN UINTN StartBit,\r | |
814 | IN UINTN EndBit,\r | |
815 | IN UINT16 AndData\r | |
816 | )\r | |
817 | {\r | |
818 | return PciWrite16 (\r | |
819 | Address,\r | |
820 | BitFieldAnd16 (PciRead16 (Address), StartBit, EndBit, AndData)\r | |
821 | );\r | |
822 | }\r | |
823 | \r | |
824 | /**\r | |
825 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 826 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 827 | 16-bit port.\r |
828 | \r | |
829 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 830 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 831 | the value specified by AndData, and writes the result to the 16-bit PCI\r |
832 | configuration register specified by Address. The value written to the PCI\r | |
833 | configuration register is returned. This function must guarantee that all PCI\r | |
834 | read and write operations are serialized. Extra left bits in both AndData and\r | |
835 | OrData are stripped.\r | |
836 | \r | |
837 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
838 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
839 | If StartBit is greater than 15, then ASSERT().\r | |
840 | If EndBit is greater than 15, then ASSERT().\r | |
841 | If EndBit is less than StartBit, then ASSERT().\r | |
842 | \r | |
843 | @param Address PCI configuration register to write.\r | |
844 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
845 | Range 0..15.\r | |
846 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
847 | Range 0..15.\r | |
848 | @param AndData The value to AND with the PCI configuration register.\r | |
849 | @param OrData The value to OR with the result of the AND operation.\r | |
850 | \r | |
851 | @return The value written back to the PCI configuration register.\r | |
852 | \r | |
853 | **/\r | |
854 | UINT16\r | |
855 | EFIAPI\r | |
856 | PciBitFieldAndThenOr16 (\r | |
857 | IN UINTN Address,\r | |
858 | IN UINTN StartBit,\r | |
859 | IN UINTN EndBit,\r | |
860 | IN UINT16 AndData,\r | |
861 | IN UINT16 OrData\r | |
862 | )\r | |
863 | {\r | |
864 | return PciWrite16 (\r | |
865 | Address,\r | |
866 | BitFieldAndThenOr16 (PciRead16 (Address), StartBit, EndBit, AndData, OrData)\r | |
867 | );\r | |
868 | }\r | |
869 | \r | |
870 | /**\r | |
871 | Reads a 32-bit PCI configuration register.\r | |
872 | \r | |
873 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
874 | This function must guarantee that all PCI read and write operations are\r | |
875 | serialized.\r | |
876 | \r | |
877 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
878 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
879 | \r | |
880 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
881 | Register.\r | |
882 | \r | |
883 | @return The value read from the PCI configuration register.\r | |
884 | \r | |
885 | **/\r | |
886 | UINT32\r | |
887 | EFIAPI\r | |
888 | PciRead32 (\r | |
889 | IN UINTN Address\r | |
890 | )\r | |
891 | {\r | |
892 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
893 | \r | |
894 | return DxePciLibPciRootBridgeIoReadWorker (Address, EfiPciWidthUint32);\r | |
895 | }\r | |
896 | \r | |
897 | /**\r | |
898 | Writes a 32-bit PCI configuration register.\r | |
899 | \r | |
900 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
901 | value specified by Value. Value is returned. This function must guarantee\r | |
902 | that all PCI read and write operations are serialized.\r | |
903 | \r | |
904 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
905 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
906 | \r | |
907 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
908 | Register.\r | |
909 | @param Data The value to write.\r | |
910 | \r | |
911 | @return The value written to the PCI configuration register.\r | |
912 | \r | |
913 | **/\r | |
914 | UINT32\r | |
915 | EFIAPI\r | |
916 | PciWrite32 (\r | |
917 | IN UINTN Address,\r | |
918 | IN UINT32 Data\r | |
919 | )\r | |
920 | {\r | |
921 | ASSERT_INVALID_PCI_ADDRESS (Address, 3);\r | |
922 | \r | |
923 | return DxePciLibPciRootBridgeIoWriteWorker (Address, EfiPciWidthUint32, Data);\r | |
924 | }\r | |
925 | \r | |
926 | /**\r | |
62991af2 | 927 | Performs a bitwise OR of a 32-bit PCI configuration register with\r |
1a3eaf06 | 928 | a 32-bit value.\r |
929 | \r | |
930 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 931 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 932 | OrData, and writes the result to the 32-bit PCI configuration register\r |
933 | specified by Address. The value written to the PCI configuration register is\r | |
934 | returned. This function must guarantee that all PCI read and write operations\r | |
935 | are serialized.\r | |
936 | \r | |
937 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
938 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
939 | \r | |
940 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
941 | Register.\r | |
942 | @param OrData The value to OR with the PCI configuration register.\r | |
943 | \r | |
944 | @return The value written back to the PCI configuration register.\r | |
945 | \r | |
946 | **/\r | |
947 | UINT32\r | |
948 | EFIAPI\r | |
949 | PciOr32 (\r | |
950 | IN UINTN Address,\r | |
951 | IN UINT32 OrData\r | |
952 | )\r | |
953 | {\r | |
954 | return PciWrite32 (Address, PciRead32 (Address) | OrData);\r | |
955 | }\r | |
956 | \r | |
957 | /**\r | |
958 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
959 | value.\r | |
960 | \r | |
961 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
962 | bitwise AND between the read result and the value specified by AndData, and\r | |
963 | writes the result to the 32-bit PCI configuration register specified by\r | |
964 | Address. The value written to the PCI configuration register is returned.\r | |
965 | This function must guarantee that all PCI read and write operations are\r | |
966 | serialized.\r | |
967 | \r | |
968 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
969 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
970 | \r | |
971 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
972 | Register.\r | |
973 | @param AndData The value to AND with the PCI configuration register.\r | |
974 | \r | |
975 | @return The value written back to the PCI configuration register.\r | |
976 | \r | |
977 | **/\r | |
978 | UINT32\r | |
979 | EFIAPI\r | |
980 | PciAnd32 (\r | |
981 | IN UINTN Address,\r | |
982 | IN UINT32 AndData\r | |
983 | )\r | |
984 | {\r | |
985 | return PciWrite32 (Address, PciRead32 (Address) & AndData);\r | |
986 | }\r | |
987 | \r | |
988 | /**\r | |
989 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
62991af2 | 990 | value, followed a bitwise OR with another 32-bit value.\r |
1a3eaf06 | 991 | \r |
992 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
993 | bitwise AND between the read result and the value specified by AndData,\r | |
62991af2 | 994 | performs a bitwise OR between the result of the AND operation and\r |
1a3eaf06 | 995 | the value specified by OrData, and writes the result to the 32-bit PCI\r |
996 | configuration register specified by Address. The value written to the PCI\r | |
997 | configuration register is returned. This function must guarantee that all PCI\r | |
998 | read and write operations are serialized.\r | |
999 | \r | |
1000 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1001 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1002 | \r | |
1003 | @param Address Address that encodes the PCI Bus, Device, Function and\r | |
1004 | Register.\r | |
1005 | @param AndData The value to AND with the PCI configuration register.\r | |
1006 | @param OrData The value to OR with the result of the AND operation.\r | |
1007 | \r | |
1008 | @return The value written back to the PCI configuration register.\r | |
1009 | \r | |
1010 | **/\r | |
1011 | UINT32\r | |
1012 | EFIAPI\r | |
1013 | PciAndThenOr32 (\r | |
1014 | IN UINTN Address,\r | |
1015 | IN UINT32 AndData,\r | |
1016 | IN UINT32 OrData\r | |
1017 | )\r | |
1018 | {\r | |
1019 | return PciWrite32 (Address, (PciRead32 (Address) & AndData) | OrData);\r | |
1020 | }\r | |
1021 | \r | |
1022 | /**\r | |
1023 | Reads a bit field of a PCI configuration register.\r | |
1024 | \r | |
1025 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
1026 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
1027 | returned.\r | |
1028 | \r | |
1029 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1030 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1031 | If StartBit is greater than 31, then ASSERT().\r | |
1032 | If EndBit is greater than 31, then ASSERT().\r | |
1033 | If EndBit is less than StartBit, then ASSERT().\r | |
1034 | \r | |
1035 | @param Address PCI configuration register to read.\r | |
1036 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1037 | Range 0..31.\r | |
1038 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1039 | Range 0..31.\r | |
1040 | \r | |
1041 | @return The value of the bit field read from the PCI configuration register.\r | |
1042 | \r | |
1043 | **/\r | |
1044 | UINT32\r | |
1045 | EFIAPI\r | |
1046 | PciBitFieldRead32 (\r | |
1047 | IN UINTN Address,\r | |
1048 | IN UINTN StartBit,\r | |
1049 | IN UINTN EndBit\r | |
1050 | )\r | |
1051 | {\r | |
1052 | return BitFieldRead32 (PciRead32 (Address), StartBit, EndBit);\r | |
1053 | }\r | |
1054 | \r | |
1055 | /**\r | |
1056 | Writes a bit field to a PCI configuration register.\r | |
1057 | \r | |
1058 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
1059 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
1060 | destination PCI configuration register are preserved. The new value of the\r | |
1061 | 32-bit register is returned.\r | |
1062 | \r | |
1063 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1064 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1065 | If StartBit is greater than 31, then ASSERT().\r | |
1066 | If EndBit is greater than 31, then ASSERT().\r | |
1067 | If EndBit is less than StartBit, then ASSERT().\r | |
1068 | \r | |
1069 | @param Address PCI configuration register to write.\r | |
1070 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1071 | Range 0..31.\r | |
1072 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1073 | Range 0..31.\r | |
1074 | @param Value New value of the bit field.\r | |
1075 | \r | |
1076 | @return The value written back to the PCI configuration register.\r | |
1077 | \r | |
1078 | **/\r | |
1079 | UINT32\r | |
1080 | EFIAPI\r | |
1081 | PciBitFieldWrite32 (\r | |
1082 | IN UINTN Address,\r | |
1083 | IN UINTN StartBit,\r | |
1084 | IN UINTN EndBit,\r | |
1085 | IN UINT32 Value\r | |
1086 | )\r | |
1087 | {\r | |
1088 | return PciWrite32 (\r | |
1089 | Address,\r | |
1090 | BitFieldWrite32 (PciRead32 (Address), StartBit, EndBit, Value)\r | |
1091 | );\r | |
1092 | }\r | |
1093 | \r | |
1094 | /**\r | |
1095 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
1096 | writes the result back to the bit field in the 32-bit port.\r | |
1097 | \r | |
1098 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1099 | bitwise OR between the read result and the value specified by\r |
1a3eaf06 | 1100 | OrData, and writes the result to the 32-bit PCI configuration register\r |
1101 | specified by Address. The value written to the PCI configuration register is\r | |
1102 | returned. This function must guarantee that all PCI read and write operations\r | |
1103 | are serialized. Extra left bits in OrData are stripped.\r | |
1104 | \r | |
1105 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1106 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1107 | If StartBit is greater than 31, then ASSERT().\r | |
1108 | If EndBit is greater than 31, then ASSERT().\r | |
1109 | If EndBit is less than StartBit, then ASSERT().\r | |
1110 | \r | |
1111 | @param Address PCI configuration register to write.\r | |
1112 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1113 | Range 0..31.\r | |
1114 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1115 | Range 0..31.\r | |
1116 | @param OrData The value to OR with the PCI configuration register.\r | |
1117 | \r | |
1118 | @return The value written back to the PCI configuration register.\r | |
1119 | \r | |
1120 | **/\r | |
1121 | UINT32\r | |
1122 | EFIAPI\r | |
1123 | PciBitFieldOr32 (\r | |
1124 | IN UINTN Address,\r | |
1125 | IN UINTN StartBit,\r | |
1126 | IN UINTN EndBit,\r | |
1127 | IN UINT32 OrData\r | |
1128 | )\r | |
1129 | {\r | |
1130 | return PciWrite32 (\r | |
1131 | Address,\r | |
1132 | BitFieldOr32 (PciRead32 (Address), StartBit, EndBit, OrData)\r | |
1133 | );\r | |
1134 | }\r | |
1135 | \r | |
1136 | /**\r | |
1137 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
1138 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
1139 | \r | |
1140 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
1141 | bitwise AND between the read result and the value specified by AndData, and\r | |
1142 | writes the result to the 32-bit PCI configuration register specified by\r | |
1143 | Address. The value written to the PCI configuration register is returned.\r | |
1144 | This function must guarantee that all PCI read and write operations are\r | |
1145 | serialized. Extra left bits in AndData are stripped.\r | |
1146 | \r | |
1147 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1148 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1149 | If StartBit is greater than 31, then ASSERT().\r | |
1150 | If EndBit is greater than 31, then ASSERT().\r | |
1151 | If EndBit is less than StartBit, then ASSERT().\r | |
1152 | \r | |
1153 | @param Address PCI configuration register to write.\r | |
1154 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1155 | Range 0..31.\r | |
1156 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1157 | Range 0..31.\r | |
1158 | @param AndData The value to AND with the PCI configuration register.\r | |
1159 | \r | |
1160 | @return The value written back to the PCI configuration register.\r | |
1161 | \r | |
1162 | **/\r | |
1163 | UINT32\r | |
1164 | EFIAPI\r | |
1165 | PciBitFieldAnd32 (\r | |
1166 | IN UINTN Address,\r | |
1167 | IN UINTN StartBit,\r | |
1168 | IN UINTN EndBit,\r | |
1169 | IN UINT32 AndData\r | |
1170 | )\r | |
1171 | {\r | |
1172 | return PciWrite32 (\r | |
1173 | Address,\r | |
1174 | BitFieldAnd32 (PciRead32 (Address), StartBit, EndBit, AndData)\r | |
1175 | );\r | |
1176 | }\r | |
1177 | \r | |
1178 | /**\r | |
1179 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
62991af2 | 1180 | bitwise OR, and writes the result back to the bit field in the\r |
1a3eaf06 | 1181 | 32-bit port.\r |
1182 | \r | |
1183 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
62991af2 | 1184 | bitwise AND followed by a bitwise OR between the read result and\r |
1a3eaf06 | 1185 | the value specified by AndData, and writes the result to the 32-bit PCI\r |
1186 | configuration register specified by Address. The value written to the PCI\r | |
1187 | configuration register is returned. This function must guarantee that all PCI\r | |
1188 | read and write operations are serialized. Extra left bits in both AndData and\r | |
1189 | OrData are stripped.\r | |
1190 | \r | |
1191 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
1192 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
1193 | If StartBit is greater than 31, then ASSERT().\r | |
1194 | If EndBit is greater than 31, then ASSERT().\r | |
1195 | If EndBit is less than StartBit, then ASSERT().\r | |
1196 | \r | |
1197 | @param Address PCI configuration register to write.\r | |
1198 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
1199 | Range 0..31.\r | |
1200 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
1201 | Range 0..31.\r | |
1202 | @param AndData The value to AND with the PCI configuration register.\r | |
1203 | @param OrData The value to OR with the result of the AND operation.\r | |
1204 | \r | |
1205 | @return The value written back to the PCI configuration register.\r | |
1206 | \r | |
1207 | **/\r | |
1208 | UINT32\r | |
1209 | EFIAPI\r | |
1210 | PciBitFieldAndThenOr32 (\r | |
1211 | IN UINTN Address,\r | |
1212 | IN UINTN StartBit,\r | |
1213 | IN UINTN EndBit,\r | |
1214 | IN UINT32 AndData,\r | |
1215 | IN UINT32 OrData\r | |
1216 | )\r | |
1217 | {\r | |
1218 | return PciWrite32 (\r | |
1219 | Address,\r | |
1220 | BitFieldAndThenOr32 (PciRead32 (Address), StartBit, EndBit, AndData, OrData)\r | |
1221 | );\r | |
1222 | }\r | |
1223 | \r | |
1224 | /**\r | |
1225 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
1226 | \r | |
1227 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
1228 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
1229 | configuration registers from a single PCI function to be read. Size is\r | |
1230 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
1231 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
1232 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
1233 | end of the range.\r | |
1234 | \r | |
1235 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1236 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1237 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1238 | \r | |
1239 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1240 | Function and Register.\r | |
1241 | @param Size Size in bytes of the transfer.\r | |
1242 | @param Buffer Pointer to a buffer receiving the data read.\r | |
1243 | \r | |
1244 | @return Size\r | |
1245 | \r | |
1246 | **/\r | |
1247 | UINTN\r | |
1248 | EFIAPI\r | |
1249 | PciReadBuffer (\r | |
1250 | IN UINTN StartAddress,\r | |
1251 | IN UINTN Size,\r | |
1252 | OUT VOID *Buffer\r | |
1253 | )\r | |
1254 | {\r | |
1255 | UINTN ReturnValue;\r | |
1256 | \r | |
1257 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1258 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1259 | \r |
1260 | if (Size == 0) {\r | |
1261 | return Size;\r | |
1262 | }\r | |
1263 | \r | |
1264 | ASSERT (Buffer != NULL);\r | |
1265 | \r | |
1266 | //\r | |
1267 | // Save Size for return\r | |
1268 | //\r | |
1269 | ReturnValue = Size;\r | |
1270 | \r | |
e43e4b3e | 1271 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1272 | //\r |
1273 | // Read a byte if StartAddress is byte aligned\r | |
1274 | //\r | |
1275 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1276 | StartAddress += sizeof (UINT8);\r | |
1277 | Size -= sizeof (UINT8);\r | |
1278 | Buffer = (UINT8*)Buffer + 1;\r | |
1279 | }\r | |
1280 | \r | |
e43e4b3e | 1281 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1282 | //\r |
1283 | // Read a word if StartAddress is word aligned\r | |
1284 | //\r | |
1285 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r | |
1286 | StartAddress += sizeof (UINT16);\r | |
1287 | Size -= sizeof (UINT16);\r | |
1288 | Buffer = (UINT16*)Buffer + 1;\r | |
1289 | }\r | |
1290 | \r | |
1291 | while (Size >= sizeof (UINT32)) {\r | |
1292 | //\r | |
1293 | // Read as many double words as possible\r | |
1294 | //\r | |
1295 | *(volatile UINT32 *)Buffer = PciRead32 (StartAddress);\r | |
1296 | StartAddress += sizeof (UINT32);\r | |
1297 | Size -= sizeof (UINT32);\r | |
1298 | Buffer = (UINT32*)Buffer + 1;\r | |
1299 | }\r | |
1300 | \r | |
1301 | if (Size >= sizeof (UINT16)) {\r | |
1302 | //\r | |
1303 | // Read the last remaining word if exist\r | |
1304 | //\r | |
1305 | *(volatile UINT16 *)Buffer = PciRead16 (StartAddress);\r | |
1306 | StartAddress += sizeof (UINT16);\r | |
1307 | Size -= sizeof (UINT16);\r | |
1308 | Buffer = (UINT16*)Buffer + 1;\r | |
1309 | }\r | |
1310 | \r | |
1311 | if (Size >= sizeof (UINT8)) {\r | |
1312 | //\r | |
1313 | // Read the last remaining byte if exist\r | |
1314 | //\r | |
1315 | *(volatile UINT8 *)Buffer = PciRead8 (StartAddress);\r | |
1316 | }\r | |
1317 | \r | |
1318 | return ReturnValue;\r | |
1319 | }\r | |
1320 | \r | |
1321 | /**\r | |
1322 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
1323 | configuration space.\r | |
1324 | \r | |
1325 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
1326 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
1327 | configuration registers from a single PCI function to be written. Size is\r | |
1328 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
1329 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
1330 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
1331 | and the end of the range.\r | |
1332 | \r | |
1333 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
1334 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
1335 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
1336 | \r | |
1337 | @param StartAddress Starting address that encodes the PCI Bus, Device,\r | |
1338 | Function and Register.\r | |
1339 | @param Size Size in bytes of the transfer.\r | |
1340 | @param Buffer Pointer to a buffer containing the data to write.\r | |
1341 | \r | |
1342 | @return Size\r | |
1343 | \r | |
1344 | **/\r | |
1345 | UINTN\r | |
1346 | EFIAPI\r | |
1347 | PciWriteBuffer (\r | |
1348 | IN UINTN StartAddress,\r | |
1349 | IN UINTN Size,\r | |
1350 | IN VOID *Buffer\r | |
1351 | )\r | |
1352 | {\r | |
1353 | UINTN ReturnValue;\r | |
1354 | \r | |
1355 | ASSERT_INVALID_PCI_ADDRESS (StartAddress, 0);\r | |
e43e4b3e | 1356 | ASSERT (((StartAddress & 0xFFF) + Size) <= 0x1000);\r |
1a3eaf06 | 1357 | \r |
1358 | if (Size == 0) {\r | |
1359 | return 0;\r | |
1360 | }\r | |
1361 | \r | |
1362 | ASSERT (Buffer != NULL);\r | |
1363 | \r | |
1364 | //\r | |
1365 | // Save Size for return\r | |
1366 | //\r | |
1367 | ReturnValue = Size;\r | |
1368 | \r | |
e43e4b3e | 1369 | if ((StartAddress & BIT0) != 0) {\r |
1a3eaf06 | 1370 | //\r |
1371 | // Write a byte if StartAddress is byte aligned\r | |
1372 | //\r | |
1373 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1374 | StartAddress += sizeof (UINT8);\r | |
1375 | Size -= sizeof (UINT8);\r | |
1376 | Buffer = (UINT8*)Buffer + 1;\r | |
1377 | }\r | |
1378 | \r | |
e43e4b3e | 1379 | if (Size >= sizeof (UINT16) && (StartAddress & BIT1) != 0) {\r |
1a3eaf06 | 1380 | //\r |
1381 | // Write a word if StartAddress is word aligned\r | |
1382 | //\r | |
1383 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1384 | StartAddress += sizeof (UINT16);\r | |
1385 | Size -= sizeof (UINT16);\r | |
1386 | Buffer = (UINT16*)Buffer + 1;\r | |
1387 | }\r | |
1388 | \r | |
1389 | while (Size >= sizeof (UINT32)) {\r | |
1390 | //\r | |
1391 | // Write as many double words as possible\r | |
1392 | //\r | |
1393 | PciWrite32 (StartAddress, *(UINT32*)Buffer);\r | |
1394 | StartAddress += sizeof (UINT32);\r | |
1395 | Size -= sizeof (UINT32);\r | |
1396 | Buffer = (UINT32*)Buffer + 1;\r | |
1397 | }\r | |
1398 | \r | |
1399 | if (Size >= sizeof (UINT16)) {\r | |
1400 | //\r | |
1401 | // Write the last remaining word if exist\r | |
1402 | //\r | |
1403 | PciWrite16 (StartAddress, *(UINT16*)Buffer);\r | |
1404 | StartAddress += sizeof (UINT16);\r | |
1405 | Size -= sizeof (UINT16);\r | |
1406 | Buffer = (UINT16*)Buffer + 1;\r | |
1407 | }\r | |
1408 | \r | |
1409 | if (Size >= sizeof (UINT8)) {\r | |
1410 | //\r | |
1411 | // Write the last remaining byte if exist\r | |
1412 | //\r | |
1413 | PciWrite8 (StartAddress, *(UINT8*)Buffer);\r | |
1414 | }\r | |
1415 | \r | |
1416 | return ReturnValue;\r | |
1417 | }\r |