projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 1a3eaf06 | 1 | /** @file\r |
| 2 | Include file of PciSegmentPciRootBridgeIo Library.\r | |
| 3 | \r | |
| 19388d29 HT |
4 | Copyright (c) 2007 - 2009, Intel Corporation. All rights reserved.<BR>\r |
| 5 | This program and the accompanying materials are\r | |
| 1a3eaf06 | 6 | licensed and made available under the terms and conditions of\r |
| 7 | the BSD License which accompanies this distribution. The full\r | |
| 8 | text of the license may be found at\r | |
| 2fc59a00 | 9 | http://opensource.org/licenses/bsd-license.php.\r |
| 1a3eaf06 | 10 | \r |
| 11 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 12 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 13 | \r | |
| 14 | **/\r | |
| 15 | \r | |
| 16 | #ifndef __DXE_PCI_SEGMENT_LIB__\r | |
| 17 | #define __DXE_PCI_SEGMENT_LIB__\r | |
| 18 | \r | |
| 19 | #include <PiDxe.h>\r | |
| 20 | \r | |
| 21 | #include <Protocol/PciRootBridgeIo.h>\r | |
| 22 | \r | |
| 23 | #include <Library/PciSegmentLib.h>\r | |
| 24 | #include <Library/BaseLib.h>\r | |
| 25 | #include <Library/MemoryAllocationLib.h>\r | |
| 26 | #include <Library/UefiBootServicesTableLib.h>\r | |
| 27 | #include <Library/DebugLib.h>\r | |
| 28 | \r | |
| 29 | #include <IndustryStandard/Acpi.h>\r | |
| 30 | \r | |
| 31 | typedef struct {\r | |
| 32 | EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL *PciRootBridgeIo;\r | |
| 33 | UINT32 SegmentNumber;\r | |
| 34 | UINT64 MinBusNumber;\r | |
| 35 | UINT64 MaxBusNumber;\r | |
| 36 | } PCI_ROOT_BRIDGE_DATA;\r | |
| 37 | \r | |
| 38 | /**\r | |
| 39 | Assert the validity of a PCI Segment address.\r | |
| 59ceeabe | 40 | A valid PCI Segment address should not contain 1's in bits 28..31 and 48..63\r |
| 1a3eaf06 | 41 | \r |
| 42 | @param A The address to validate.\r | |
| 43 | @param M Additional bits to assert to be zero.\r | |
| 44 | \r | |
| 45 | **/\r | |
| 46 | #define ASSERT_INVALID_PCI_SEGMENT_ADDRESS(A,M) \\r | |
| 59ceeabe | 47 | ASSERT (((A) & (0xffff0000f0000000ULL | (M))) == 0)\r |
| 1a3eaf06 | 48 | \r |
| 49 | /**\r | |
| e43e4b3e | 50 | Translate PCI Lib address into format of PCI Root Bridge I/O Protocol\r |
| 1a3eaf06 | 51 | \r |
| 2fc59a00 | 52 | @param A The address that encodes the PCI Bus, Device, Function and\r |
| 1a3eaf06 | 53 | Register.\r |
| 54 | \r | |
| 55 | **/\r | |
| e43e4b3e | 56 | #define PCI_TO_PCI_ROOT_BRIDGE_IO_ADDRESS(A) \\r |
| f5305d5a | 57 | ((((UINT32)(A) << 4) & 0xff000000) | (((UINT32)(A) >> 4) & 0x00000700) | (((UINT32)(A) << 1) & 0x001f0000) | (LShiftU64((A) & 0xfff, 32)))\r |
| 1a3eaf06 | 58 | \r |
| 59 | #endif\r |