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540fd45f
MK		 1/** @file\r
2 Unit Test Host BaseLib hooks.\r
3\r
4 Copyright (c) 2020, Intel Corporation. All rights reserved.<BR>\r
5 SPDX-License-Identifier: BSD-2-Clause-Patent\r
6\r
7**/\r
8\r
9#ifndef __UNIT_TEST_HOST_BASE_LIB_H__\r
10#define __UNIT_TEST_HOST_BASE_LIB_H__\r
11\r
12/**\r
13 Prototype of service with no parameters and no return value.\r
14**/\r
15typedef\r
16VOID\r
17(EFIAPI *UNIT_TEST_HOST_BASE_LIB_VOID)(\r
18 VOID\r
19 );\r
20\r
21/**\r
22 Prototype of service that reads and returns a BOOLEAN value.\r
23\r
24 @return The value read.\r
25**/\r
26typedef\r
27BOOLEAN\r
28(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN)(\r
29 VOID\r
30 );\r
31\r
32/**\r
33 Prototype of service that reads and returns a UINT16 value.\r
34\r
35 @return The value read.\r
36**/\r
37typedef\r
38UINT16\r
39(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINT16)(\r
40 VOID\r
41 );\r
42\r
43/**\r
44 Prototype of service that reads and returns a UINTN value.\r
45\r
46 @return The value read.\r
47**/\r
48typedef\r
49UINTN\r
50(EFIAPI *UNIT_TEST_HOST_BASE_LIB_READ_UINTN)(\r
51 VOID\r
52 );\r
53\r
54/**\r
55 Prototype of service that writes and returns a UINT16 value.\r
56\r
57 @param[in] Value The value to write.\r
58\r
59 @return The value written.\r
60**/\r
61typedef\r
62VOID\r
63(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16)(\r
64 IN UINT16 Value\r
65 );\r
66\r
67/**\r
68 Prototype of service that writes and returns a UINTN value.\r
69\r
70 @param[in] Value The value to write.\r
71\r
72 @return The value written.\r
73**/\r
74typedef\r
75UINTN\r
76(EFIAPI *UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN)(\r
77 IN UINTN Value\r
78 );\r
79\r
80/**\r
81 Prototype of service that reads and returns an IA32_DESCRIPTOR.\r
82\r
83 @param[out] Ia32Descriptor Pointer to the descriptor read.\r
84**/\r
85typedef\r
86VOID\r
87(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR)(\r
88 OUT IA32_DESCRIPTOR *Ia32Descriptor\r
89 );\r
90\r
91/**\r
92 Prototype of service that writes an IA32_DESCRIPTOR.\r
93\r
94 @param[in] Ia32Descriptor Pointer to the descriptor to write.\r
95**/\r
96typedef\r
97VOID\r
98(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR)(\r
99 IN CONST IA32_DESCRIPTOR *Ia32Descriptor\r
100 );\r
101\r
102/**\r
103 Retrieves CPUID information.\r
104\r
105 Executes the CPUID instruction with EAX set to the value specified by Index.\r
106 This function always returns Index.\r
107 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r
108 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
109 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
110 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
111 This function is only available on IA-32 and x64.\r
112\r
113 @param Index The 32-bit value to load into EAX prior to invoking the CPUID\r
114 instruction.\r
115 @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r
116 instruction. This is an optional parameter that may be NULL.\r
117 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r
118 instruction. This is an optional parameter that may be NULL.\r
119 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r
120 instruction. This is an optional parameter that may be NULL.\r
121 @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r
122 instruction. This is an optional parameter that may be NULL.\r
123\r
124 @return Index.\r
125\r
126**/\r
127typedef\r
128UINT32\r
129(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID)(\r
130 IN UINT32 Index,\r
d0e2f823
MK		 131 OUT UINT32 *Eax OPTIONAL,\r
132 OUT UINT32 *Ebx OPTIONAL,\r
133 OUT UINT32 *Ecx OPTIONAL,\r
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MK		 134 OUT UINT32 *Edx OPTIONAL\r
135 );\r
136\r
137/**\r
138 Retrieves CPUID information using an extended leaf identifier.\r
139\r
140 Executes the CPUID instruction with EAX set to the value specified by Index\r
141 and ECX set to the value specified by SubIndex. This function always returns\r
142 Index. This function is only available on IA-32 and x64.\r
143\r
144 If Eax is not NULL, then the value of EAX after CPUID is returned in Eax.\r
145 If Ebx is not NULL, then the value of EBX after CPUID is returned in Ebx.\r
146 If Ecx is not NULL, then the value of ECX after CPUID is returned in Ecx.\r
147 If Edx is not NULL, then the value of EDX after CPUID is returned in Edx.\r
148\r
149 @param Index The 32-bit value to load into EAX prior to invoking the\r
150 CPUID instruction.\r
151 @param SubIndex The 32-bit value to load into ECX prior to invoking the\r
152 CPUID instruction.\r
153 @param Eax The pointer to the 32-bit EAX value returned by the CPUID\r
154 instruction. This is an optional parameter that may be\r
155 NULL.\r
156 @param Ebx The pointer to the 32-bit EBX value returned by the CPUID\r
157 instruction. This is an optional parameter that may be\r
158 NULL.\r
159 @param Ecx The pointer to the 32-bit ECX value returned by the CPUID\r
160 instruction. This is an optional parameter that may be\r
161 NULL.\r
162 @param Edx The pointer to the 32-bit EDX value returned by the CPUID\r
163 instruction. This is an optional parameter that may be\r
164 NULL.\r
165\r
166 @return Index.\r
167\r
168**/\r
169typedef\r
170UINT32\r
171(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX)(\r
172 IN UINT32 Index,\r
173 IN UINT32 SubIndex,\r
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MK		 174 OUT UINT32 *Eax OPTIONAL,\r
175 OUT UINT32 *Ebx OPTIONAL,\r
176 OUT UINT32 *Ecx OPTIONAL,\r
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MK		 177 OUT UINT32 *Edx OPTIONAL\r
178 );\r
179\r
180/**\r
181 Returns a 64-bit Machine Specific Register(MSR).\r
182\r
183 Reads and returns the 64-bit MSR specified by Index. No parameter checking is\r
184 performed on Index, and some Index values may cause CPU exceptions. The\r
185 caller must either guarantee that Index is valid, or the caller must set up\r
186 exception handlers to catch the exceptions. This function is only available\r
187 on IA-32 and x64.\r
188\r
189 @param Index The 32-bit MSR index to read.\r
190\r
191 @return The value of the MSR identified by Index.\r
192\r
193**/\r
194typedef\r
195UINT64\r
196(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64)(\r
197 IN UINT32 Index\r
198 );\r
199\r
200/**\r
201 Writes a 64-bit value to a Machine Specific Register(MSR), and returns the\r
202 value.\r
203\r
204 Writes the 64-bit value specified by Value to the MSR specified by Index. The\r
205 64-bit value written to the MSR is returned. No parameter checking is\r
206 performed on Index or Value, and some of these may cause CPU exceptions. The\r
207 caller must either guarantee that Index and Value are valid, or the caller\r
208 must establish proper exception handlers. This function is only available on\r
209 IA-32 and x64.\r
210\r
211 @param Index The 32-bit MSR index to write.\r
212 @param Value The 64-bit value to write to the MSR.\r
213\r
214 @return Value\r
215\r
216**/\r
217typedef\r
218UINT64\r
219(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64)(\r
220 IN UINT32 Index,\r
221 IN UINT64 Value\r
222 );\r
223\r
224/**\r
225 Reads the current value of a Performance Counter (PMC).\r
226\r
227 Reads and returns the current value of performance counter specified by\r
228 Index. This function is only available on IA-32 and x64.\r
229\r
230 @param Index The 32-bit Performance Counter index to read.\r
231\r
232 @return The value of the PMC specified by Index.\r
233\r
234**/\r
235typedef\r
236UINT64\r
237(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC)(\r
238 IN UINT32 Index\r
239 );\r
240\r
241/**\r
242 Sets up a monitor buffer that is used by AsmMwait().\r
243\r
244 Executes a MONITOR instruction with the register state specified by Eax, Ecx\r
245 and Edx. Returns Eax. This function is only available on IA-32 and x64.\r
246\r
247 @param Eax The value to load into EAX or RAX before executing the MONITOR\r
248 instruction.\r
249 @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
250 instruction.\r
251 @param Edx The value to load into EDX or RDX before executing the MONITOR\r
252 instruction.\r
253\r
254 @return Eax\r
255\r
256**/\r
257typedef\r
258UINTN\r
259(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR)(\r
260 IN UINTN Eax,\r
261 IN UINTN Ecx,\r
262 IN UINTN Edx\r
263 );\r
264\r
265/**\r
266 Executes an MWAIT instruction.\r
267\r
268 Executes an MWAIT instruction with the register state specified by Eax and\r
269 Ecx. Returns Eax. This function is only available on IA-32 and x64.\r
270\r
271 @param Eax The value to load into EAX or RAX before executing the MONITOR\r
272 instruction.\r
273 @param Ecx The value to load into ECX or RCX before executing the MONITOR\r
274 instruction.\r
275\r
276 @return Eax\r
277\r
278**/\r
279typedef\r
280UINTN\r
281(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT)(\r
282 IN UINTN Eax,\r
283 IN UINTN Ecx\r
284 );\r
285\r
286/**\r
287 Flushes a cache line from all the instruction and data caches within the\r
288 coherency domain of the CPU.\r
289\r
290 Flushed the cache line specified by LinearAddress, and returns LinearAddress.\r
291 This function is only available on IA-32 and x64.\r
292\r
293 @param LinearAddress The address of the cache line to flush. If the CPU is\r
294 in a physical addressing mode, then LinearAddress is a\r
295 physical address. If the CPU is in a virtual\r
296 addressing mode, then LinearAddress is a virtual\r
297 address.\r
298\r
299 @return LinearAddress.\r
300**/\r
301typedef\r
302VOID *\r
303(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE)(\r
304 IN VOID *LinearAddress\r
305 );\r
306\r
307/**\r
308 Prototype of service that enables ot disables 32-bit paging modes.\r
309\r
310 @param EntryPoint A pointer to function to call with the new stack after\r
311 paging is enabled.\r
312 @param Context1 A pointer to the context to pass into the EntryPoint\r
313 function as the first parameter after paging is enabled.\r
314 @param Context2 A pointer to the context to pass into the EntryPoint\r
315 function as the second parameter after paging is enabled.\r
316 @param NewStack A pointer to the new stack to use for the EntryPoint\r
317 function after paging is enabled.\r
318\r
319**/\r
320typedef\r
321VOID\r
322(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32)(\r
323 IN SWITCH_STACK_ENTRY_POINT EntryPoint,\r
d0e2f823
MK		 324 IN VOID *Context1 OPTIONAL,\r
325 IN VOID *Context2 OPTIONAL,\r
540fd45f
MK		 326 IN VOID *NewStack\r
327 );\r
328\r
329/**\r
330 Enables the 64-bit paging mode on the CPU.\r
331\r
332 Enables the 64-bit paging mode on the CPU. CR0, CR3, CR4, and the page tables\r
333 must be properly initialized prior to calling this service. This function\r
334 assumes the current execution mode is 32-bit protected mode with flat\r
335 descriptors. This function is only available on IA-32. After the 64-bit\r
336 paging mode is enabled, control is transferred to the function specified by\r
337 EntryPoint using the new stack specified by NewStack and passing in the\r
338 parameters specified by Context1 and Context2. Context1 and Context2 are\r
339 optional and may be 0. The function EntryPoint must never return.\r
340\r
341 If the current execution mode is not 32-bit protected mode with flat\r
342 descriptors, then ASSERT().\r
343 If EntryPoint is 0, then ASSERT().\r
344 If NewStack is 0, then ASSERT().\r
345\r
346 @param Cs The 16-bit selector to load in the CS before EntryPoint\r
347 is called. The descriptor in the GDT that this selector\r
348 references must be setup for long mode.\r
349 @param EntryPoint The 64-bit virtual address of the function to call with\r
350 the new stack after paging is enabled.\r
351 @param Context1 The 64-bit virtual address of the context to pass into\r
352 the EntryPoint function as the first parameter after\r
353 paging is enabled.\r
354 @param Context2 The 64-bit virtual address of the context to pass into\r
355 the EntryPoint function as the second parameter after\r
356 paging is enabled.\r
357 @param NewStack The 64-bit virtual address of the new stack to use for\r
358 the EntryPoint function after paging is enabled.\r
359\r
360**/\r
361typedef\r
362VOID\r
363(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64)(\r
364 IN UINT16 Cs,\r
365 IN UINT64 EntryPoint,\r
d0e2f823
MK		 366 IN UINT64 Context1 OPTIONAL,\r
367 IN UINT64 Context2 OPTIONAL,\r
540fd45f
MK		 368 IN UINT64 NewStack\r
369 );\r
370\r
371/**\r
372 Disables the 64-bit paging mode on the CPU.\r
373\r
374 Disables the 64-bit paging mode on the CPU and returns to 32-bit protected\r
375 mode. This function assumes the current execution mode is 64-paging mode.\r
376 This function is only available on x64. After the 64-bit paging mode is\r
377 disabled, control is transferred to the function specified by EntryPoint\r
378 using the new stack specified by NewStack and passing in the parameters\r
379 specified by Context1 and Context2. Context1 and Context2 are optional and\r
380 may be 0. The function EntryPoint must never return.\r
381\r
382 If the current execution mode is not 64-bit paged mode, then ASSERT().\r
383 If EntryPoint is 0, then ASSERT().\r
384 If NewStack is 0, then ASSERT().\r
385\r
386 @param Cs The 16-bit selector to load in the CS before EntryPoint\r
387 is called. The descriptor in the GDT that this selector\r
388 references must be setup for 32-bit protected mode.\r
389 @param EntryPoint The 64-bit virtual address of the function to call with\r
390 the new stack after paging is disabled.\r
391 @param Context1 The 64-bit virtual address of the context to pass into\r
392 the EntryPoint function as the first parameter after\r
393 paging is disabled.\r
394 @param Context2 The 64-bit virtual address of the context to pass into\r
395 the EntryPoint function as the second parameter after\r
396 paging is disabled.\r
397 @param NewStack The 64-bit virtual address of the new stack to use for\r
398 the EntryPoint function after paging is disabled.\r
399\r
400**/\r
401typedef\r
402VOID\r
403(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64)(\r
404 IN UINT16 Cs,\r
405 IN UINT32 EntryPoint,\r
d0e2f823
MK		 406 IN UINT32 Context1 OPTIONAL,\r
407 IN UINT32 Context2 OPTIONAL,\r
540fd45f
MK		 408 IN UINT32 NewStack\r
409 );\r
410\r
411/**\r
412 Retrieves the properties for 16-bit thunk functions.\r
413\r
414 Computes the size of the buffer and stack below 1MB required to use the\r
415 AsmPrepareThunk16(), AsmThunk16() and AsmPrepareAndThunk16() functions. This\r
416 buffer size is returned in RealModeBufferSize, and the stack size is returned\r
417 in ExtraStackSize. If parameters are passed to the 16-bit real mode code,\r
418 then the actual minimum stack size is ExtraStackSize plus the maximum number\r
419 of bytes that need to be passed to the 16-bit real mode code.\r
420\r
421 If RealModeBufferSize is NULL, then ASSERT().\r
422 If ExtraStackSize is NULL, then ASSERT().\r
423\r
424 @param RealModeBufferSize A pointer to the size of the buffer below 1MB\r
425 required to use the 16-bit thunk functions.\r
426 @param ExtraStackSize A pointer to the extra size of stack below 1MB\r
427 that the 16-bit thunk functions require for\r
428 temporary storage in the transition to and from\r
429 16-bit real mode.\r
430\r
431**/\r
432typedef\r
433VOID\r
434(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES)(\r
435 OUT UINT32 *RealModeBufferSize,\r
436 OUT UINT32 *ExtraStackSize\r
437 );\r
438\r
439/**\r
440 Prototype of services that operates on a THUNK_CONTEXT structure.\r
441\r
442 @param ThunkContext A pointer to the context structure that describes the\r
443 16-bit real mode code to call.\r
444\r
445**/\r
446typedef\r
447VOID\r
448(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16)(\r
449 IN OUT THUNK_CONTEXT *ThunkContext\r
450 );\r
451\r
452/**\r
453 Patch the immediate operand of an IA32 or X64 instruction such that the byte,\r
454 word, dword or qword operand is encoded at the end of the instruction's\r
455 binary representation.\r
456\r
457 This function should be used to update object code that was compiled with\r
458 NASM from assembly source code. Example:\r
459\r
460 NASM source code:\r
461\r
462 mov eax, strict dword 0 ; the imm32 zero operand will be patched\r
463 ASM_PFX(gPatchCr3):\r
464 mov cr3, eax\r
465\r
466 C source code:\r
467\r
468 X86_ASSEMBLY_PATCH_LABEL gPatchCr3;\r
469 PatchInstructionX86 (gPatchCr3, AsmReadCr3 (), 4);\r
470\r
471 @param[out] InstructionEnd Pointer right past the instruction to patch. The\r
472 immediate operand to patch is expected to\r
473 comprise the trailing bytes of the instruction.\r
474 If InstructionEnd is closer to address 0 than\r
475 ValueSize permits, then ASSERT().\r
476\r
477 @param[in] PatchValue The constant to write to the immediate operand.\r
478 The caller is responsible for ensuring that\r
479 PatchValue can be represented in the byte, word,\r
480 dword or qword operand (as indicated through\r
481 ValueSize); otherwise ASSERT().\r
482\r
483 @param[in] ValueSize The size of the operand in bytes; must be 1, 2,\r
484 4, or 8. ASSERT() otherwise.\r
485**/\r
486typedef\r
487VOID\r
488(EFIAPI *UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86)(\r
489 OUT X86_ASSEMBLY_PATCH_LABEL *InstructionEnd,\r
490 IN UINT64 PatchValue,\r
491 IN UINTN ValueSize\r
492 );\r
493\r
494///\r
495/// Common services\r
496///\r
497typedef struct {\r
2f88bd3a
MK		 498 UNIT_TEST_HOST_BASE_LIB_VOID EnableInterrupts;\r
499 UNIT_TEST_HOST_BASE_LIB_VOID DisableInterrupts;\r
500 UNIT_TEST_HOST_BASE_LIB_VOID EnableDisableInterrupts;\r
501 UNIT_TEST_HOST_BASE_LIB_READ_BOOLEAN GetInterruptState;\r
540fd45f
MK		 502} UNIT_TEST_HOST_BASE_LIB_COMMON;\r
503\r
504///\r
505/// IA32/X64 services\r
506///\r
507typedef struct {\r
2f88bd3a
MK		 508 UNIT_TEST_HOST_BASE_LIB_ASM_CPUID AsmCpuid;\r
509 UNIT_TEST_HOST_BASE_LIB_ASM_CPUID_EX AsmCpuidEx;\r
510 UNIT_TEST_HOST_BASE_LIB_VOID AsmDisableCache;\r
511 UNIT_TEST_HOST_BASE_LIB_VOID AsmEnableCache;\r
512 UNIT_TEST_HOST_BASE_LIB_ASM_READ_MSR_64 AsmReadMsr64;\r
513 UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_MSR_64 AsmWriteMsr64;\r
514 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr0;\r
515 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr2;\r
516 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr3;\r
517 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadCr4;\r
518 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr0;\r
519 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr2;\r
520 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr3;\r
521 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteCr4;\r
522 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr0;\r
523 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr1;\r
524 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr2;\r
525 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr3;\r
526 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr4;\r
527 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr5;\r
528 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr6;\r
529 UNIT_TEST_HOST_BASE_LIB_READ_UINTN AsmReadDr7;\r
530 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr0;\r
531 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr1;\r
532 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr2;\r
533 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr3;\r
534 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr4;\r
535 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr5;\r
536 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr6;\r
537 UNIT_TEST_HOST_BASE_LIB_WRITE_UINTN AsmWriteDr7;\r
538 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadCs;\r
539 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadDs;\r
540 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadEs;\r
541 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadFs;\r
542 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadGs;\r
543 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadSs;\r
544 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadTr;\r
545 UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadGdtr;\r
546 UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteGdtr;\r
547 UNIT_TEST_HOST_BASE_LIB_ASM_READ_IA32_DESCRIPTOR AsmReadIdtr;\r
548 UNIT_TEST_HOST_BASE_LIB_ASM_WRITE_IA32_DESCRIPTOR AsmWriteIdtr;\r
549 UNIT_TEST_HOST_BASE_LIB_READ_UINT16 AsmReadLdtr;\r
550 UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteLdtr;\r
551 UNIT_TEST_HOST_BASE_LIB_ASM_READ_PMC AsmReadPmc;\r
552 UNIT_TEST_HOST_BASE_LIB_ASM_MONITOR AsmMonitor;\r
553 UNIT_TEST_HOST_BASE_LIB_ASM_MWAIT AsmMwait;\r
554 UNIT_TEST_HOST_BASE_LIB_VOID AsmWbinvd;\r
555 UNIT_TEST_HOST_BASE_LIB_VOID AsmInvd;\r
556 UNIT_TEST_HOST_BASE_LIB_ASM_FLUSH_CACHE_LINE AsmFlushCacheLine;\r
557 UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmEnablePaging32;\r
558 UNIT_TEST_HOST_BASE_LIB_ASM_PAGING_32 AsmDisablePaging32;\r
559 UNIT_TEST_HOST_BASE_LIB_ASM_ENABLE_PAGING_64 AsmEnablePaging64;\r
560 UNIT_TEST_HOST_BASE_LIB_ASM_DISABLE_PAGING_64 AsmDisablePaging64;\r
561 UNIT_TEST_HOST_BASE_LIB_ASM_GET_THUNK_16_PROPERTIES AsmGetThunk16Properties;\r
562 UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareThunk16;\r
563 UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmThunk16;\r
564 UNIT_TEST_HOST_BASE_LIB_ASM_THUNK_16 AsmPrepareAndThunk16;\r
565 UNIT_TEST_HOST_BASE_LIB_WRITE_UINT16 AsmWriteTr;\r
566 UNIT_TEST_HOST_BASE_LIB_VOID AsmLfence;\r
567 UNIT_TEST_HOST_BASE_LIB_ASM_PATCH_INSTRUCTION_X86 PatchInstructionX86;\r
540fd45f
MK		 568} UNIT_TEST_HOST_BASE_LIB_X86;\r
569\r
570///\r
571/// Data structure that contains pointers structures of common services and CPU\r
572/// architctuire specific services. Support for additional CPU architectures\r
573/// can be added to the end of this structure.\r
574///\r
575typedef struct {\r
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MK		 576 UNIT_TEST_HOST_BASE_LIB_COMMON *Common;\r
577 UNIT_TEST_HOST_BASE_LIB_X86 *X86;\r
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MK		 578} UNIT_TEST_HOST_BASE_LIB;\r
579\r
580extern UNIT_TEST_HOST_BASE_LIB gUnitTestHostBaseLib;\r
581\r
582#endif\r
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