added couple of PAL proc related constants
[mirror_edk2.git] / OldMdePkg / Include / Library / PalCallLib.h
CommitLineData
63afc360 1/** @file\r
2 PAL Call Services\r
3\r
de4eb1da 4 Copyright (c) 2006 -2007, Intel Corporation All rights\r
5 reserved. This program and the accompanying materials are\r
6 licensed and made available under the terms and conditions of\r
7 the BSD License which accompanies this distribution. The full\r
8 text of the license may be found at\r
63afc360 9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14 Module Name: PalCallLib.h\r
15\r
16**/\r
17\r
18#ifndef __PAL_CALL_LIB_H__\r
19#define __PAL_CALL_LIB_H__\r
20\r
de4eb1da 21//\r
22// CacheType of PAL_CACHE_FLUSH.\r
23//\r
24#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
25#define PAL_CACHE_FLUSH_DATA_ALL 2\r
26#define PAL_CACHE_FLUSH_ALL 3\r
27#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
28\r
29\r
30//\r
31// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
32// \r
2b5f1d9f 33#define PAL_CACHE_FLUSH_INVALIDATE_LINES BIT0\r
34#define PAL_CACHE_FLUSH_NO_INVALIDATE_LINES 0\r
35#define PAL_CACHE_FLUSH_POLL_INTERRUPT BIT1\r
36#define PAL_CACHE_FLUSH_NO_INTERRUPT 0\r
de4eb1da 37\r
38/**\r
39 \r
40 PAL Procedure - PAL_CACHE_FLUSH.\r
41 \r
42 Flush the instruction or data caches. It is required by IPF.\r
43 The PAL procedure supports the Static Registers calling\r
44 convention. It could be called at virtual mode and physical\r
45 mode.\r
46\r
47 @param Index Index of PAL_CACHE_FLUSH within the\r
48 list of PAL procedures.\r
49 \r
50 @param CacheType Unsigned 64-bit integer indicating\r
51 which cache to flush.\r
52\r
53 @param Operation Formatted bit vector indicating the\r
54 operation of this call.\r
55\r
56 @param ProgressIndicator Unsigned 64-bit integer specifying\r
57 the starting position of the flush\r
58 operation.\r
59 \r
60 @return R9 Unsigned 64-bit integer specifying the vector\r
61 number of the pending interrupt.\r
62 \r
63 @return R10 Unsigned 64-bit integer specifying the\r
64 starting position of the flush operation.\r
65 \r
66 @return R11 Unsigned 64-bit integer specifying the vector\r
67 number of the pending interrupt.\r
68 \r
69 @return Status 2 - Call completed without error, but a PMI\r
70 was taken during the execution of this\r
71 procedure.\r
72\r
73 @return Status 1 - Call has not completed flushing due to\r
74 a pending interrupt.\r
75\r
76 @return Status 0 - Call completed without error\r
77\r
78 @return Status -2 - Invalid argument\r
79\r
80 @return Status -3 - Call completed with error\r
81 \r
82**/\r
83#define PAL_CACHE_FLUSH 1\r
84\r
85\r
86//\r
87// Attributes of PAL_CACHE_CONFIG_INFO1\r
88// \r
89#define PAL_CACHE_ATTR_WT 0\r
90#define PAL_CACHE_ATTR_WB 1\r
91\r
92//\r
93// PAL_CACHE_CONFIG_INFO1.StoreHint\r
94// \r
95#define PAL_CACHE_STORE_TEMPORAL 0\r
96#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
97\r
98//\r
99// PAL_CACHE_CONFIG_INFO1.StoreHint\r
100// \r
101#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
102#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
103\r
104//\r
105// PAL_CACHE_CONFIG_INFO1.StoreHint\r
106// \r
107#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
108#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
109#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
110\r
111//\r
112// Detail the characteristics of a given processor controlled\r
113// cache in the cache hierarchy.\r
114// \r
115typedef struct {\r
116 UINT64 IsUnified : 1;\r
117 UINT64 Attributes : 2;\r
118 UINT64 Associativity:8;\r
119 UINT64 LineSize:8;\r
120 UINT64 Stride:8;\r
121 UINT64 StoreLatency:8;\r
122 UINT64 StoreHint:8;\r
123 UINT64 LoadHint:8;\r
124} PAL_CACHE_INFO_RETURN1;\r
125\r
126//\r
127// Detail the characteristics of a given processor controlled\r
128// cache in the cache hierarchy.\r
129// \r
130typedef struct {\r
131 UINT64 CacheSize:32;\r
132 UINT64 AliasBoundary:8;\r
133 UINT64 TagLsBits:8;\r
134 UINT64 TagMsBits:8;\r
135} PAL_CACHE_INFO_RETURN2;\r
136\r
137/**\r
138 \r
139 PAL Procedure - PAL_CACHE_INFO.\r
140 \r
141 Return detailed instruction or data cache information. It is\r
142 required by IPF. The PAL procedure supports the Static\r
143 Registers calling convention. It could be called at virtual\r
144 mode and physical mode.\r
145 \r
146 @param Index Index of PAL_CACHE_INFO within the list of\r
147 PAL procedures.\r
148 \r
149 @param CacheLevel Unsigned 64-bit integer specifying the\r
150 level in the cache hierarchy for which\r
151 information is requested. This value must\r
152 be between 0 and one less than the value\r
153 returned in the cache_levels return value\r
154 from PAL_CACHE_SUMMARY.\r
155 \r
156 @param CacheType Unsigned 64-bit integer with a value of 1\r
157 for instruction cache and 2 for data or\r
158 unified cache. All other values are\r
159 reserved.\r
160 \r
161 @param Reserved Should be 0.\r
162 \r
163 \r
164 @return R9 Detail the characteristics of a given\r
165 processor controlled cache in the cache\r
166 hierarchy. See PAL_CACHE_INFO_RETURN1.\r
167 \r
168 @return R10 Detail the characteristics of a given\r
169 processor controlled cache in the cache\r
170 hierarchy. See PAL_CACHE_INFO_RETURN2.\r
171 \r
172 @return R11 Reserved with 0.\r
173 \r
174 \r
175 @return Status 0 - Call completed without error\r
176\r
177 @return Status -2 - Invalid argument\r
178\r
179 @return Status -3 - Call completed with error\r
180 \r
181**/\r
182#define PAL_CACHE_INFO 2\r
183\r
184\r
185\r
186//\r
187// Level of PAL_CACHE_INIT.\r
188// \r
189#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
190\r
2b5f1d9f 191//\r
192// CacheType \r
193//\r
194#define PAL_CACHE_INIT_TYPE_INSTRUCTION 0x1\r
195#define PAL_CACHE_INIT_TYPE_DATA 0x2\r
196#define PAL_CACHE_INIT_TYPE_INSTRUCTION_AND_DATA 0x3\r
197\r
de4eb1da 198//\r
199// Restrict of PAL_CACHE_INIT.\r
200// \r
201#define PAL_CACHE_INIT_NO_RESTRICT 0\r
202#define PAL_CACHE_INIT_RESTRICTED 1\r
203\r
204/**\r
205 \r
206 PAL Procedure - PAL_CACHE_INIT.\r
207 \r
208 Initialize the instruction or data caches. It is required by\r
209 IPF. The PAL procedure supports the Static Registers calling\r
210 convention. It could be called at physical mode.\r
211\r
212 @param Index Index of PAL_CACHE_INIT within the list of PAL\r
213 procedures.\r
214 \r
215 @param Level Unsigned 64-bit integer containing the level of\r
216 cache to initialize. If the cache level can be\r
217 initialized independently, only that level will\r
218 be initialized. Otherwise\r
219 implementation-dependent side-effects will\r
220 occur.\r
221 \r
222 @param CacheType Unsigned 64-bit integer with a value of 1 to\r
223 initialize the instruction cache, 2 to\r
224 initialize the data cache, or 3 to\r
225 initialize both. All other values are\r
226 reserved.\r
227\r
228 @param Restrict Unsigned 64-bit integer with a value of 0 or\r
229 1. All other values are reserved. If\r
230 restrict is 1 and initializing the specified\r
231 level and cache_type of the cache would\r
232 cause side-effects, PAL_CACHE_INIT will\r
233 return -4 instead of initializing the cache.\r
234 \r
235 \r
236 @return Status 0 - Call completed without error\r
237\r
238 @return Status -2 - Invalid argument\r
239\r
240 @return Status -3 - Call completed with error.\r
241 \r
242 @return Status -4 - Call could not initialize the specified\r
243 level and cache_type of the cache without\r
244 side-effects and restrict was 1. \r
245 \r
246**/\r
247#define PAL_CACHE_INIT 3 \r
248\r
249\r
250//\r
251// PAL_CACHE_PROTECTION.Method.\r
252// \r
253#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
254#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
255#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
256#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
257\r
258\r
259\r
260//\r
261// PAL_CACHE_PROTECTION.TagOrData.\r
262// \r
263#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
264#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
265#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
266#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
267\r
268//\r
269// 32-bit protection information structures.\r
270// \r
271typedef struct {\r
272 UINT32 DataBits:8;\r
273 UINT32 TagProtLsb:6;\r
274 UINT32 TagProtMsb:6;\r
275 UINT32 ProtBits:6;\r
276 UINT32 Method:4;\r
277 UINT32 TagOrData:2;\r
278} PAL_CACHE_PROTECTION;\r
279\r
280/**\r
281 \r
282 PAL Procedure - PAL_CACHE_PROT_INFO.\r
283 \r
284 Return instruction or data cache protection information. It is\r
285 required by IPF. The PAL procedure supports the Static\r
286 Registers calling convention. It could be called at physical\r
287 mode and Virtual mode.\r
288\r
289 @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
290 PAL procedures.\r
291\r
292 @param CacheLevel Unsigned 64-bit integer specifying the level\r
293 in the cache hierarchy for which information\r
294 is requested. This value must be between 0\r
295 and one less than the value returned in the\r
296 cache_levels return value from\r
297 PAL_CACHE_SUMMARY.\r
298\r
299 @param CacheType Unsigned 64-bit integer with a value of 1\r
300 for instruction cache and 2 for data or\r
301 unified cache. All other values are\r
302 reserved.\r
303 \r
304 @return R9 Detail the characteristics of a given\r
305 processor controlled cache in the cache\r
306 hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
307 \r
308 @return R10 Detail the characteristics of a given\r
309 processor controlled cache in the cache\r
310 hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
311 \r
312 @return R11 Detail the characteristics of a given\r
313 processor controlled cache in the cache\r
314 hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
315 \r
316 \r
317 @return Status 0 - Call completed without error\r
318\r
319 @return Status -2 - Invalid argument\r
320\r
321 @return Status -3 - Call completed with error.\r
322 \r
323**/\r
324#define PAL_CACHE_PROT_INFO 38\r
325\r
326/**\r
327 \r
328 @param ThreadId The thread identifier of the logical\r
329 processor for which information is being\r
330 returned. This value will be unique on a per\r
331 core basis.\r
332\r
333 @param CoreId The core identifier of the logical processor\r
334 for which information is being returned.\r
335 This value will be unique on a per physical\r
336 processor package basis.\r
337\r
338**/\r
339typedef struct {\r
340 UINT64 ThreadId : 16;\r
341 UINT64 Reserved1: 16;\r
342 UINT64 CoreId: 16;\r
343 UINT64 Reserved2: 16;\r
344} PAL_PCOC_N_CACHE_INFO1;\r
345\r
346/**\r
347 \r
348 @param LogicalAddress Logical address: geographical address\r
349 of the logical processor for which\r
350 information is being returned. This is\r
351 the same value that is returned by the\r
352 PAL_FIXED_ADDR procedure when it is\r
353 called on the logical processor.\r
354\r
355**/\r
356typedef struct {\r
357 UINT64 LogicalAddress : 16;\r
358 UINT64 Reserved1: 16;\r
359 UINT64 Reserved2: 32;\r
360} PAL_PCOC_N_CACHE_INFO2;\r
361\r
362/**\r
363 \r
364 PAL Procedure - PAL_CACHE_SHARED_INFO.\r
365 \r
366 Returns information on which logical processors share caches.\r
367 It is optional. The PAL procedure supports the Static\r
368 Registers calling convention. It could be called at physical\r
369 mode and Virtual mode.\r
370 \r
371 @param Index Index of PAL_CACHE_SHARED_INFO within the list\r
372 of PAL procedures.\r
373 \r
374 @param CacheLevel Unsigned 64-bit integer specifying the\r
375 level in the cache hierarchy for which\r
376 information is requested. This value must\r
377 be between 0 and one less than the value\r
378 returned in the cache_levels return value\r
379 from PAL_CACHE_SUMMARY.\r
380 \r
381 @param CacheType Unsigned 64-bit integer with a value of 1\r
382 for instruction cache and 2 for data or\r
383 unified cache. All other values are\r
384 reserved.\r
385 \r
386 @param ProcNumber Unsigned 64-bit integer that specifies for\r
387 which logical processor information is\r
388 being requested. This input argument must\r
389 be zero for the first call to this\r
390 procedure and can be a maximum value of\r
391 one less than the number of logical\r
392 processors sharing this cache, which is\r
393 returned by the num_shared return value.\r
394 \r
395 @return R9 Unsigned integer that returns the number of\r
396 logical processors that share the processor\r
397 cache level and type, for which information was\r
398 requested.\r
399\r
400 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r
401\r
402 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r
403\r
404 @return Status 0 - Call completed without error\r
405\r
406 @return Status -1 - Unimplemented procedure\r
407\r
408 @return Status -2 - Invalid argument\r
409\r
410 @return Status -3 - Call completed with error.\r
411 \r
412**/\r
413#define PAL_CACHE_SHARED_INFO 43\r
414\r
415\r
416/**\r
417 \r
418 PAL Procedure - PAL_CACHE_SUMMARY.\r
419 \r
420 Return a summary of the cache hierarchy. It is required by\r
421 IPF. The PAL procedure supports the Static Registers calling\r
422 convention. It could be called at physical mode and Virtual\r
423 mode.\r
424 \r
425 @param Index Index of PAL_CACHE_SUMMARY within the list of\r
426 PAL procedures.\r
427\r
428 \r
429 @return R9 CacheLevels Unsigned 64-bit integer denoting the\r
430 number of levels of cache\r
431 implemented by the processor.\r
432 Strictly, this is the number of\r
433 levels for which the cache\r
434 controller is integrated into the\r
435 processor (the cache SRAMs may be\r
436 external to the processor).\r
437\r
438 @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r
439 number of unique caches implemented\r
440 by the processor. This has a maximum\r
441 of 2*cache_levels, but may be less\r
442 if any of the levels in the cache\r
443 hierarchy are unified caches or do\r
444 not have both instruction and data\r
445 caches.\r
446\r
447 @return Status 0 - Call completed without error\r
448\r
449 @return Status -2 - Invalid argument\r
450\r
451 @return Status -3 - Call completed with error.\r
452 \r
453**/\r
454#define PAL_CACHE_SUMMARY 4\r
455\r
456\r
457//\r
458// Virtual Memory Attributes implemented by processor. \r
459// \r
460#define PAL_MEMORY_ATTR_WB 0\r
461#define PAL_MEMORY_ATTR_WC 6\r
462#define PAL_MEMORY_ATTR_UC 4\r
463#define PAL_MEMORY_ATTR_UCE 5\r
464#define PAL_MEMORY_ATTR_NATPAGE 7\r
465\r
466/**\r
467 \r
468 PAL Procedure - PAL_MEM_ATTRIB.\r
469 \r
470 Return a list of supported memory attributes.. It is required\r
471 by IPF. The PAL procedure supports the Static Registers calling\r
472 convention. It could be called at physical mode and Virtual\r
473 mode.\r
474 \r
475 @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
476 procedures.\r
477\r
478 \r
479 @return R9 Attributes 8-bit vector of memory attributes\r
480 implemented by processor. See Virtual\r
481 Memory Attributes above.\r
482\r
483 @return Status 0 - Call completed without error\r
484\r
485 @return Status -2 - Invalid argument\r
486\r
487 @return Status -3 - Call completed with error.\r
488 \r
489**/\r
490\r
491#define PAL_MEM_ATTRIB 5\r
492\r
493/**\r
494 \r
495 PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
496 \r
497 Used in architected sequence to transition pages from a\r
498 cacheable, speculative attribute to an uncacheable attribute.\r
499 It is required by IPF. The PAL procedure supports the Static\r
500 Registers calling convention. It could be called at physical\r
501 mode and Virtual mode.\r
502 \r
503 @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
504 of PAL procedures.\r
505\r
506 @param TransitionType Unsigned integer specifying the type\r
507 of memory attribute transition that is\r
508 being performed.\r
509 \r
510 @return Status 1 Call completed without error; this\r
511 call is not necessary on remote\r
512 processors.\r
513\r
514 @return Status 0 - Call completed without error\r
515\r
516 @return Status -2 - Invalid argument\r
517\r
518 @return Status -3 - Call completed with error.\r
519 \r
520**/\r
521#define PAL_PREFETCH_VISIBILITY 41\r
522\r
523/**\r
524 \r
525 PAL Procedure - PAL_PTCE_INFO.\r
526 \r
527 Return information needed for ptc.e instruction to purge\r
528 entire TC. It is required by IPF. The PAL procedure supports\r
529 the Static Registers calling convention. It could be called at\r
530 physical mode and Virtual mode.\r
531 \r
532 @param Index Index of PAL_PTCE_INFO within the list\r
533 of PAL procedures.\r
534\r
535 @return R9 Unsigned 64-bit integer denoting the beginning\r
536 address to be used by the first PTCE instruction\r
537 in the purge loop.\r
538 \r
539 @return R10 Two unsigned 32-bit integers denoting the loop\r
540 counts of the outer (loop 1) and inner (loop 2)\r
541 purge loops. count1 (loop 1) is contained in bits\r
542 63:32 of the parameter, and count2 (loop 2) is\r
543 contained in bits 31:0 of the parameter.\r
544 \r
545 @return R11 Two unsigned 32-bit integers denoting the loop\r
546 strides of the outer (loop 1) and inner (loop 2)\r
547 purge loops. stride1 (loop 1) is contained in bits\r
548 63:32 of the parameter, and stride2 (loop 2) is\r
549 contained in bits 31:0 of the parameter.\r
550\r
551 @return Status 0 - Call completed without error\r
552\r
553 @return Status -2 - Invalid argument\r
554\r
555 @return Status -3 - Call completed with error.\r
556 \r
557**/\r
558#define PAL_PTCE_INFO 6\r
559\r
560\r
561\r
562/**\r
563 \r
564 @param NumberSets Unsigned 8-bit integer denoting the number\r
565 of hash sets for the specified level\r
566 (1=fully associative)\r
567\r
568 @param NumberWays Unsigned 8-bit integer denoting the\r
569 associativity of the specified level\r
570 (1=direct).\r
571\r
572 @param NumberEntries Unsigned 16-bit integer denoting the\r
573 number of entries in the specified TC.\r
574\r
575\r
576 @param PageSizeIsOptimized Flag denoting whether the\r
577 specified level is optimized for\r
578 the region's preferred page size\r
579 (1=optimized) tc_pages indicates\r
580 which page sizes are usable by\r
581 this translation cache.\r
582\r
583 @param TcIsUnified Flag denoting whether the specified TC is\r
584 unified (1=unified).\r
585\r
586 @param EntriesReduction Flag denoting whether installed\r
587 translation registers will reduce\r
588 the number of entries within the\r
589 specified TC.\r
590\r
591**/\r
592typedef struct {\r
593 UINT64 NumberSets:8;\r
594 UINT64 NumberWays:8;\r
595 UINT64 NumberEntries:16;\r
596 UINT64 PageSizeIsOptimized:1;\r
597 UINT64 TcIsUnified:1;\r
598 UINT64 EntriesReduction:1;\r
599} PAL_TC_INFO;\r
600\r
601/**\r
602 \r
603 PAL Procedure - PAL_VM_INFO.\r
604 \r
605 Return detailed information about virtual memory features\r
606 supported in the processor. It is required by IPF. The PAL\r
607 procedure supports the Static Registers calling convention. It\r
608 could be called at physical mode and Virtual mode.\r
609 \r
610 @param Index Index of PAL_VM_INFO within the list\r
611 of PAL procedures.\r
612 \r
613 @param TcLevel Unsigned 64-bit integer specifying the level\r
614 in the TLB hierarchy for which information is\r
615 required. This value must be between 0 and one\r
616 less than the value returned in the\r
617 vm_info_1.num_tc_levels return value from\r
618 PAL_VM_SUMMARY.\r
619 \r
620 @param TcType Unsigned 64-bit integer with a value of 1 for\r
621 instruction translation cache and 2 for data\r
622 or unified translation cache. All other values\r
623 are reserved.\r
624\r
625 @return R9 8-byte formatted value returning information\r
626 about the specified TC. See PAL_TC_INFO above.\r
627\r
628 @return R10 64-bit vector containing a bit for each page\r
629 size supported in the specified TC, where bit\r
630 position n indicates a page size of 2**n.\r
631\r
632 @return Status 0 - Call completed without error\r
633\r
634 @return Status -2 - Invalid argument\r
635\r
636 @return Status -3 - Call completed with error.\r
637 \r
638**/\r
639#define PAL_VM_INFO 7\r
640\r
641\r
642/**\r
643 \r
644 PAL Procedure - PAL_VM_PAGE_SIZE.\r
645 \r
646 Return virtual memory TC and hardware walker page sizes\r
647 supported in the processor. It is required by IPF. The PAL\r
648 procedure supports the Static Registers calling convention. It\r
649 could be called at physical mode and Virtual mode.\r
650 \r
651 @param Index Index of PAL_VM_PAGE_SIZE within the list\r
652 of PAL procedures.\r
653 \r
654\r
655 @return R9 64-bit vector containing a bit for each\r
656 architected page size that is supported for\r
657 TLB insertions and region registers.\r
658\r
659 @return R10 64-bit vector containing a bit for each\r
660 architected page size supported for TLB purge\r
661 operations.\r
662\r
663 @return Status 0 - Call completed without error\r
664\r
665 @return Status -2 - Invalid argument\r
666\r
667 @return Status -3 - Call completed with error.\r
668 \r
669**/\r
670#define PAL_VM_PAGE_SIZE 34\r
671\r
672/**\r
673 \r
674 @param WalkerPresent 1-bit flag indicating whether a hardware\r
675 TLB walker is implemented (1 = walker\r
676 present).\r
677\r
678 @param WidthOfPhysicalAddress Unsigned 7-bit integer\r
679 denoting the number of bits of\r
680 physical address implemented.\r
681\r
682 @param WidthOfKey Unsigned 8-bit integer denoting the number\r
683 of bits mplemented in the PKR.key field.\r
684\r
685 @param MaxPkrIndex Unsigned 8-bit integer denoting the\r
686 maximum PKR index (number of PKRs-1).\r
687\r
688 @param HashTagId Unsigned 8-bit integer which uniquely\r
689 identifies the processor hash and tag\r
690 algorithm.\r
691\r
692 @param MaxDtrIndex Unsigned 8 bit integer denoting the\r
693 maximum data translation register index\r
694 (number of dtr entries - 1).\r
695\r
696 @param MaxItrIndex Unsigned 8 bit integer denoting the\r
697 maximum instruction translation register\r
698 index (number of itr entries - 1).\r
699\r
700 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r
701 number of unique TCs implemented.\r
702 This is a maximum of\r
703 2*num_tc_levels.\r
704\r
705 @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r
706 number of TC levels.\r
707\r
708**/\r
709typedef struct {\r
710 UINT64 WalkerPresent:1;\r
711 UINT64 WidthOfPhysicalAddress: 7;\r
712 UINT64 WidthOfKey:8;\r
713 UINT64 MaxPkrIndex:8;\r
714 UINT64 HashTagId:8;\r
715 UINT64 MaxDtrIndex:8;\r
716 UINT64 MaxItrIndex:8;\r
717 UINT64 NumberOfUniqueTc:8;\r
718 UINT64 NumberOfTcLevels:8;\r
719} PAL_VM_INFO1;\r
720\r
721/**\r
722 \r
723 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r
724 is the total number of virtual\r
725 address bits - 1.\r
726\r
727 @param WidthOfRid Unsigned 8-bit integer denoting the number\r
728 of bits implemented in the RR.rid field.\r
729\r
730 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r
731 maximum number of concurrent outstanding\r
732 TLB purges allowed by the processor. A\r
733 value of 0 indicates one outstanding\r
734 purge allowed. A value of 216-1\r
735 indicates no limit on outstanding\r
736 purges. All other values indicate the\r
737 actual number of concurrent outstanding\r
738 purges allowed.\r
739\r
740**/\r
741typedef struct {\r
742 UINT64 WidthOfVirtualAddress:8;\r
743 UINT64 WidthOfRid:8;\r
744 UINT64 MaxPurgedTlbs:16;\r
745 UINT64 Reserved:32;\r
746} PAL_VM_INFO2;\r
747\r
748/**\r
749 \r
750 PAL Procedure - PAL_VM_SUMMARY.\r
751 \r
752 Return summary information about virtual memory features\r
753 supported in the processor. It is required by IPF. The PAL\r
754 procedure supports the Static Registers calling convention. It\r
755 could be called at physical mode and Virtual mode.\r
756 \r
757 @param Index Index of PAL_VM_SUMMARY within the list\r
758 of PAL procedures.\r
759 \r
760\r
761 @return R9 8-byte formatted value returning global virtual\r
762 memory information. See PAL_VM_INFO1 above.\r
763\r
764 @return R10 8-byte formatted value returning global virtual\r
765 memory information. See PAL_VM_INFO2 above.\r
766\r
767 @return Status 0 - Call completed without error\r
768\r
769 @return Status -2 - Invalid argument\r
770\r
771 @return Status -3 - Call completed with error.\r
772 \r
773**/\r
774#define PAL_VM_SUMMARY 8\r
775\r
776\r
777//\r
778// Bit mask of TR_valid flag.\r
779// \r
780#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
781#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
782#define PAL_TR_DIRTY_IS_VALID BIT2\r
783#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r
784\r
785\r
786/**\r
787 \r
788 PAL Procedure - PAL_VM_TR_READ.\r
789 \r
790 Read contents of a translation register. It is required by\r
791 IPF. The PAL procedure supports the Stacked Register calling\r
792 convention. It could be called at physical mode.\r
793 \r
794 @param Index Index of PAL_VM_TR_READ within the list\r
795 of PAL procedures.\r
796\r
797 @param RegNumber Unsigned 64-bit number denoting which TR to\r
798 read.\r
799\r
800 @param TrType Unsigned 64-bit number denoting whether to\r
801 read an ITR (0) or DTR (1). All other values\r
802 are reserved.\r
803\r
804 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r
805 which translation data is returned.\r
806\r
807 @return R9 Formatted bit vector denoting which fields are\r
808 valid. See TR_valid above.\r
809\r
810 @return Status 0 - Call completed without error\r
811\r
812 @return Status -2 - Invalid argument\r
813\r
814 @return Status -3 - Call completed with error.\r
815 \r
816**/\r
817#define PAL_VM_TR_READ 261 \r
818\r
819\r
820\r
821\r
822//\r
823// Bit Mask of Processor Bus Fesatures .\r
824// \r
825\r
826/**\r
827 \r
828 When 0, bus data errors are detected and single bit errors are\r
829 corrected. When 1, no error detection or correction is done.\r
830\r
831**/\r
832#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r
833\r
834\r
835/**\r
836 \r
837 When 0, bus address errors are signalled on the bus. When 1,\r
838 no bus errors are signalled on the bus. If Disable Bus Address\r
839 Error Checking is 1, this bit is ignored.\r
840\r
841**/\r
842#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r
843\r
844\r
845\r
846\r
847/**\r
848 \r
849 When 0, bus errors are detected, single bit errors are\r
850 corrected., and a CMCI or MCA is generated internally to the\r
851 processor. When 1, no bus address errors are detected or\r
852 corrected.\r
853\r
854**/\r
855#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r
856\r
857\r
858/**\r
859 \r
860 When 0, bus protocol errors (BINIT#) are signaled by the\r
861 processor on the bus. When 1, bus protocol errors (BINIT#) are\r
862 not signaled on the bus. If Disable Bus Initialization Event\r
863 Checking is 1, this bit is ignored.\r
864\r
865**/\r
866#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r
867\r
868\r
869/**\r
870 \r
871 When 0, bus protocol errors (BINIT#) are detected and sampled\r
872 and an MCA is generated internally to the processor. When 1,\r
873 the processor will ignore bus protocol error conditions\r
874 (BINIT#).\r
875\r
876**/\r
877#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r
878\r
879\r
880\r
881/**\r
882 \r
883 When 0, BERR# is signalled if a bus error is detected. When 1,\r
884 bus errors are not signalled on the bus.\r
885\r
886**/\r
887#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r
888\r
889\r
890\r
891\r
892/**\r
893 \r
894 When 0, BERR# is signalled when internal processor requestor\r
895 initiated bus errors are detected. When 1, internal requester\r
896 bus errors are not signalled on the bus.\r
897 \r
898**/\r
899#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
900\r
901\r
902/**\r
903 \r
904 When 0, the processor takes an MCA if BERR# is asserted. When\r
905 1, the processor ignores the BERR# signal.\r
906\r
907**/\r
908#define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r
909\r
910\r
911/**\r
912 \r
913 When 0, the processor asserts BINIT# if it detects a parity\r
914 error on the signals which identify the transactions to which\r
915 this is a response. When 1, the processor ignores parity on\r
916 these signals.\r
917 \r
918**/\r
919#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
920\r
921\r
922/**\r
923 \r
924 When 0, the in-order transaction queue is limited only by the\r
925 number of hardware entries. When 1, the processor's in-order\r
926 transactions queue is limited to one entry.\r
927\r
928**/\r
929#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
930\r
931/**\r
932 \r
933 Enable a bus cache line replacement transaction when a cache\r
934 line in the exclusive state is replaced from the highest level\r
935 processor cache and is not present in the lower level processor\r
936 caches. When 0, no bus cache line replacement transaction will\r
937 be seen on the bus. When 1, bus cache line replacement\r
938 transactions will be seen on the bus when the above condition is\r
939 detected.\r
940\r
941**/\r
942#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r
943\r
944\r
945/**\r
946 \r
947 Enable a bus cache line replacement transaction when a cache\r
948 line in the shared or exclusive state is replaced from the\r
949 highest level processor cache and is not present in the lower\r
950 level processor caches.\r
951 When 0, no bus cache line replacement transaction will be seen\r
952 on the bus. When 1, bus cache line replacement transactions\r
953 will be seen on the bus when the above condition is detected.\r
954\r
955**/\r
956#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
957\r
958\r
959 \r
960/**\r
961 \r
962 When 0, the data bus is configured at the 2x data transfer\r
963 rate.When 1, the data bus is configured at the 1x data\r
964 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
965 processor executes locked transactions atomically. When 1, the\r
966 processor masks the bus lock signal and executes locked\r
967 transactions as a non-atomic series of transactions.\r
968\r
969**/\r
970#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
971\r
972/**\r
973 \r
974 When 0, the processor will deassert bus request when finished\r
975 with each transaction. When 1, the processor will continue to\r
976 assert bus request after it has finished, if it was the last\r
977 agent to own the bus and if there are no other pending\r
978 requests.\r
979\r
980**/\r
981#define PAL_BUS_REQUEST_BUS_PARKING BIT29\r
982\r
983\r
984/**\r
985 \r
986 PAL Procedure - PAL_BUS_GET_FEATURES.\r
987 \r
988 Return configurable processor bus interface features and their\r
989 current settings. It is required by IPF. The PAL procedure\r
990 supports the Stacked Register calling convention. It could be\r
991 called at physical mode.\r
992 \r
993 @param Index Index of PAL_BUS_GET_FEATURES within the list\r
994 of PAL procedures.\r
995\r
996 @return R9 64-bit vector of features implemented.\r
997 (1=implemented, 0=not implemented)\r
998\r
999 @return R10 64-bit vector of current feature settings.\r
1000\r
1001 @return R11 64-bit vector of features controllable by\r
1002 software. (1=controllable, 0= not controllable)\r
1003\r
1004 @return Status 0 - Call completed without error\r
1005\r
1006 @return Status -2 - Invalid argument\r
1007\r
1008 @return Status -3 - Call completed with error.\r
1009 \r
1010**/\r
1011#define PAL_BUS_GET_FEATURES 9\r
1012\r
1013/**\r
1014 \r
1015 PAL Procedure - PAL_BUS_SET_FEATURES.\r
1016 \r
1017 Enable or disable configurable features in processor bus\r
1018 interface. It is required by IPF. It is required by IPF. The PAL procedure\r
1019 supports the Static Registers calling convention. It could be\r
1020 called at physical mode.\r
1021 \r
1022 @param Index Index of PAL_BUS_SET_FEATURES within the list\r
1023 of PAL procedures.\r
1024 \r
1025 @param FeatureSelect 64-bit vector denoting desired state of\r
1026 each feature (1=select, 0=non-select).\r
1027\r
1028 @return Status 0 - Call completed without error\r
1029\r
1030 @return Status -2 - Invalid argument\r
1031\r
1032 @return Status -3 - Call completed with error.\r
1033 \r
1034**/\r
1035#define PAL_BUS_SET_FEATURES 10\r
1036\r
1037\r
1038/**\r
1039 \r
1040 PAL Procedure - PAL_DEBUG_INFO.\r
1041 \r
1042 Return the number of instruction and data breakpoint\r
1043 registers. It is required by IPF. It is required by IPF. The\r
1044 PAL procedure supports the Static Registers calling\r
1045 convention. It could be called at physical mode and virtual\r
1046 mode.\r
1047 \r
1048 @param Index Index of PAL_DEBUG_INFO within the list of PAL\r
1049 procedures.\r
1050 \r
1051 @return R9 Unsigned 64-bit integer denoting the number of\r
1052 pairs of instruction debug registers implemented\r
1053 by the processor. \r
1054 \r
1055 @return R10 Unsigned 64-bit integer denoting the number of\r
1056 pairs of data debug registers implemented by the\r
1057 processor.\r
1058 \r
1059 @return Status 0 - Call completed without error\r
1060\r
1061 @return Status -2 - Invalid argument\r
1062\r
1063 @return Status -3 - Call completed with error.\r
1064 \r
1065**/\r
1066#define PAL_DEBUG_INFO 11\r
1067\r
1068/**\r
1069 \r
1070 PAL Procedure - PAL_FIXED_ADDR.\r
1071 \r
1072