copied the PalCallLib.h from the new MdePkg
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63afc360 1/** @file\r
2 PAL Call Services\r
3\r
de4eb1da 4 Copyright (c) 2006 -2007, Intel Corporation All rights\r
5 reserved. This program and the accompanying materials are\r
6 licensed and made available under the terms and conditions of\r
7 the BSD License which accompanies this distribution. The full\r
8 text of the license may be found at\r
63afc360 9 http://opensource.org/licenses/bsd-license.php\r
10\r
11 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
12 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
13\r
14 Module Name: PalCallLib.h\r
15\r
16**/\r
17\r
18#ifndef __PAL_CALL_LIB_H__\r
19#define __PAL_CALL_LIB_H__\r
20\r
de4eb1da 21//\r
22// CacheType of PAL_CACHE_FLUSH.\r
23//\r
24#define PAL_CACHE_FLUSH_INSTRUCTION_ALL 1\r
25#define PAL_CACHE_FLUSH_DATA_ALL 2\r
26#define PAL_CACHE_FLUSH_ALL 3\r
27#define PAL_CACHE_FLUSH_SYNC_TO_DATA 4\r
28\r
29\r
30//\r
31// Bitmask of Opearation of PAL_CACHE_FLUSH.\r
32// \r
33#define PAL_CACHE_FLUSH_INVIDED_LINES BIT0\r
34#define PAL_CACHE_FLUSH_PROBE_INTERRUPT BIT1\r
35\r
36/**\r
37 \r
38 PAL Procedure - PAL_CACHE_FLUSH.\r
39 \r
40 Flush the instruction or data caches. It is required by IPF.\r
41 The PAL procedure supports the Static Registers calling\r
42 convention. It could be called at virtual mode and physical\r
43 mode.\r
44\r
45 @param Index Index of PAL_CACHE_FLUSH within the\r
46 list of PAL procedures.\r
47 \r
48 @param CacheType Unsigned 64-bit integer indicating\r
49 which cache to flush.\r
50\r
51 @param Operation Formatted bit vector indicating the\r
52 operation of this call.\r
53\r
54 @param ProgressIndicator Unsigned 64-bit integer specifying\r
55 the starting position of the flush\r
56 operation.\r
57 \r
58 @return R9 Unsigned 64-bit integer specifying the vector\r
59 number of the pending interrupt.\r
60 \r
61 @return R10 Unsigned 64-bit integer specifying the\r
62 starting position of the flush operation.\r
63 \r
64 @return R11 Unsigned 64-bit integer specifying the vector\r
65 number of the pending interrupt.\r
66 \r
67 @return Status 2 - Call completed without error, but a PMI\r
68 was taken during the execution of this\r
69 procedure.\r
70\r
71 @return Status 1 - Call has not completed flushing due to\r
72 a pending interrupt.\r
73\r
74 @return Status 0 - Call completed without error\r
75\r
76 @return Status -2 - Invalid argument\r
77\r
78 @return Status -3 - Call completed with error\r
79 \r
80**/\r
81#define PAL_CACHE_FLUSH 1\r
82\r
83\r
84//\r
85// Attributes of PAL_CACHE_CONFIG_INFO1\r
86// \r
87#define PAL_CACHE_ATTR_WT 0\r
88#define PAL_CACHE_ATTR_WB 1\r
89\r
90//\r
91// PAL_CACHE_CONFIG_INFO1.StoreHint\r
92// \r
93#define PAL_CACHE_STORE_TEMPORAL 0\r
94#define PAL_CACHE_STORE_NONE_TEMPORAL 3\r
95\r
96//\r
97// PAL_CACHE_CONFIG_INFO1.StoreHint\r
98// \r
99#define PAL_CACHE_STORE_TEMPORAL_LVL_1 0\r
100#define PAL_CACHE_STORE_NONE_TEMPORAL_LVL_ALL 3\r
101\r
102//\r
103// PAL_CACHE_CONFIG_INFO1.StoreHint\r
104// \r
105#define PAL_CACHE_LOAD_TEMPORAL_LVL_1 0\r
106#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_1 1\r
107#define PAL_CACHE_LOAD_NONE_TEMPORAL_LVL_ALL 3\r
108\r
109//\r
110// Detail the characteristics of a given processor controlled\r
111// cache in the cache hierarchy.\r
112// \r
113typedef struct {\r
114 UINT64 IsUnified : 1;\r
115 UINT64 Attributes : 2;\r
116 UINT64 Associativity:8;\r
117 UINT64 LineSize:8;\r
118 UINT64 Stride:8;\r
119 UINT64 StoreLatency:8;\r
120 UINT64 StoreHint:8;\r
121 UINT64 LoadHint:8;\r
122} PAL_CACHE_INFO_RETURN1;\r
123\r
124//\r
125// Detail the characteristics of a given processor controlled\r
126// cache in the cache hierarchy.\r
127// \r
128typedef struct {\r
129 UINT64 CacheSize:32;\r
130 UINT64 AliasBoundary:8;\r
131 UINT64 TagLsBits:8;\r
132 UINT64 TagMsBits:8;\r
133} PAL_CACHE_INFO_RETURN2;\r
134\r
135/**\r
136 \r
137 PAL Procedure - PAL_CACHE_INFO.\r
138 \r
139 Return detailed instruction or data cache information. It is\r
140 required by IPF. The PAL procedure supports the Static\r
141 Registers calling convention. It could be called at virtual\r
142 mode and physical mode.\r
143 \r
144 @param Index Index of PAL_CACHE_INFO within the list of\r
145 PAL procedures.\r
146 \r
147 @param CacheLevel Unsigned 64-bit integer specifying the\r
148 level in the cache hierarchy for which\r
149 information is requested. This value must\r
150 be between 0 and one less than the value\r
151 returned in the cache_levels return value\r
152 from PAL_CACHE_SUMMARY.\r
153 \r
154 @param CacheType Unsigned 64-bit integer with a value of 1\r
155 for instruction cache and 2 for data or\r
156 unified cache. All other values are\r
157 reserved.\r
158 \r
159 @param Reserved Should be 0.\r
160 \r
161 \r
162 @return R9 Detail the characteristics of a given\r
163 processor controlled cache in the cache\r
164 hierarchy. See PAL_CACHE_INFO_RETURN1.\r
165 \r
166 @return R10 Detail the characteristics of a given\r
167 processor controlled cache in the cache\r
168 hierarchy. See PAL_CACHE_INFO_RETURN2.\r
169 \r
170 @return R11 Reserved with 0.\r
171 \r
172 \r
173 @return Status 0 - Call completed without error\r
174\r
175 @return Status -2 - Invalid argument\r
176\r
177 @return Status -3 - Call completed with error\r
178 \r
179**/\r
180#define PAL_CACHE_INFO 2\r
181\r
182\r
183\r
184//\r
185// Level of PAL_CACHE_INIT.\r
186// \r
187#define PAL_CACHE_INIT_ALL 0xffffffffffffffffULL\r
188\r
189//\r
190// Restrict of PAL_CACHE_INIT.\r
191// \r
192#define PAL_CACHE_INIT_NO_RESTRICT 0\r
193#define PAL_CACHE_INIT_RESTRICTED 1\r
194\r
195/**\r
196 \r
197 PAL Procedure - PAL_CACHE_INIT.\r
198 \r
199 Initialize the instruction or data caches. It is required by\r
200 IPF. The PAL procedure supports the Static Registers calling\r
201 convention. It could be called at physical mode.\r
202\r
203 @param Index Index of PAL_CACHE_INIT within the list of PAL\r
204 procedures.\r
205 \r
206 @param Level Unsigned 64-bit integer containing the level of\r
207 cache to initialize. If the cache level can be\r
208 initialized independently, only that level will\r
209 be initialized. Otherwise\r
210 implementation-dependent side-effects will\r
211 occur.\r
212 \r
213 @param CacheType Unsigned 64-bit integer with a value of 1 to\r
214 initialize the instruction cache, 2 to\r
215 initialize the data cache, or 3 to\r
216 initialize both. All other values are\r
217 reserved.\r
218\r
219 @param Restrict Unsigned 64-bit integer with a value of 0 or\r
220 1. All other values are reserved. If\r
221 restrict is 1 and initializing the specified\r
222 level and cache_type of the cache would\r
223 cause side-effects, PAL_CACHE_INIT will\r
224 return -4 instead of initializing the cache.\r
225 \r
226 \r
227 @return Status 0 - Call completed without error\r
228\r
229 @return Status -2 - Invalid argument\r
230\r
231 @return Status -3 - Call completed with error.\r
232 \r
233 @return Status -4 - Call could not initialize the specified\r
234 level and cache_type of the cache without\r
235 side-effects and restrict was 1. \r
236 \r
237**/\r
238#define PAL_CACHE_INIT 3 \r
239\r
240\r
241//\r
242// PAL_CACHE_PROTECTION.Method.\r
243// \r
244#define PAL_CACHE_PROTECTION_NONE_PROTECT 0\r
245#define PAL_CACHE_PROTECTION_ODD_PROTECT 1\r
246#define PAL_CACHE_PROTECTION_EVEN_PROTECT 2\r
247#define PAL_CACHE_PROTECTION_ECC_PROTECT 3\r
248\r
249\r
250\r
251//\r
252// PAL_CACHE_PROTECTION.TagOrData.\r
253// \r
254#define PAL_CACHE_PROTECTION_PROTECT_DATA 0\r
255#define PAL_CACHE_PROTECTION_PROTECT_TAG 1\r
256#define PAL_CACHE_PROTECTION_PROTECT_TAG_ANDTHEN_DATA 2\r
257#define PAL_CACHE_PROTECTION_PROTECT_DATA_ANDTHEN_TAG 3\r
258\r
259//\r
260// 32-bit protection information structures.\r
261// \r
262typedef struct {\r
263 UINT32 DataBits:8;\r
264 UINT32 TagProtLsb:6;\r
265 UINT32 TagProtMsb:6;\r
266 UINT32 ProtBits:6;\r
267 UINT32 Method:4;\r
268 UINT32 TagOrData:2;\r
269} PAL_CACHE_PROTECTION;\r
270\r
271/**\r
272 \r
273 PAL Procedure - PAL_CACHE_PROT_INFO.\r
274 \r
275 Return instruction or data cache protection information. It is\r
276 required by IPF. The PAL procedure supports the Static\r
277 Registers calling convention. It could be called at physical\r
278 mode and Virtual mode.\r
279\r
280 @param Index Index of PAL_CACHE_PROT_INFO within the list of\r
281 PAL procedures.\r
282\r
283 @param CacheLevel Unsigned 64-bit integer specifying the level\r
284 in the cache hierarchy for which information\r
285 is requested. This value must be between 0\r
286 and one less than the value returned in the\r
287 cache_levels return value from\r
288 PAL_CACHE_SUMMARY.\r
289\r
290 @param CacheType Unsigned 64-bit integer with a value of 1\r
291 for instruction cache and 2 for data or\r
292 unified cache. All other values are\r
293 reserved.\r
294 \r
295 @return R9 Detail the characteristics of a given\r
296 processor controlled cache in the cache\r
297 hierarchy. See PAL_CACHE_PROTECTION[0..1].\r
298 \r
299 @return R10 Detail the characteristics of a given\r
300 processor controlled cache in the cache\r
301 hierarchy. See PAL_CACHE_PROTECTION[2..3].\r
302 \r
303 @return R11 Detail the characteristics of a given\r
304 processor controlled cache in the cache\r
305 hierarchy. See PAL_CACHE_PROTECTION[4..5].\r
306 \r
307 \r
308 @return Status 0 - Call completed without error\r
309\r
310 @return Status -2 - Invalid argument\r
311\r
312 @return Status -3 - Call completed with error.\r
313 \r
314**/\r
315#define PAL_CACHE_PROT_INFO 38\r
316\r
317/**\r
318 \r
319 @param ThreadId The thread identifier of the logical\r
320 processor for which information is being\r
321 returned. This value will be unique on a per\r
322 core basis.\r
323\r
324 @param CoreId The core identifier of the logical processor\r
325 for which information is being returned.\r
326 This value will be unique on a per physical\r
327 processor package basis.\r
328\r
329**/\r
330typedef struct {\r
331 UINT64 ThreadId : 16;\r
332 UINT64 Reserved1: 16;\r
333 UINT64 CoreId: 16;\r
334 UINT64 Reserved2: 16;\r
335} PAL_PCOC_N_CACHE_INFO1;\r
336\r
337/**\r
338 \r
339 @param LogicalAddress Logical address: geographical address\r
340 of the logical processor for which\r
341 information is being returned. This is\r
342 the same value that is returned by the\r
343 PAL_FIXED_ADDR procedure when it is\r
344 called on the logical processor.\r
345\r
346**/\r
347typedef struct {\r
348 UINT64 LogicalAddress : 16;\r
349 UINT64 Reserved1: 16;\r
350 UINT64 Reserved2: 32;\r
351} PAL_PCOC_N_CACHE_INFO2;\r
352\r
353/**\r
354 \r
355 PAL Procedure - PAL_CACHE_SHARED_INFO.\r
356 \r
357 Returns information on which logical processors share caches.\r
358 It is optional. The PAL procedure supports the Static\r
359 Registers calling convention. It could be called at physical\r
360 mode and Virtual mode.\r
361 \r
362 @param Index Index of PAL_CACHE_SHARED_INFO within the list\r
363 of PAL procedures.\r
364 \r
365 @param CacheLevel Unsigned 64-bit integer specifying the\r
366 level in the cache hierarchy for which\r
367 information is requested. This value must\r
368 be between 0 and one less than the value\r
369 returned in the cache_levels return value\r
370 from PAL_CACHE_SUMMARY.\r
371 \r
372 @param CacheType Unsigned 64-bit integer with a value of 1\r
373 for instruction cache and 2 for data or\r
374 unified cache. All other values are\r
375 reserved.\r
376 \r
377 @param ProcNumber Unsigned 64-bit integer that specifies for\r
378 which logical processor information is\r
379 being requested. This input argument must\r
380 be zero for the first call to this\r
381 procedure and can be a maximum value of\r
382 one less than the number of logical\r
383 processors sharing this cache, which is\r
384 returned by the num_shared return value.\r
385 \r
386 @return R9 Unsigned integer that returns the number of\r
387 logical processors that share the processor\r
388 cache level and type, for which information was\r
389 requested.\r
390\r
391 @return R10 The format of PAL_PCOC_N_CACHE_INFO1.\r
392\r
393 @return R11 The format of PAL_PCOC_N_CACHE_INFO2.\r
394\r
395 @return Status 0 - Call completed without error\r
396\r
397 @return Status -1 - Unimplemented procedure\r
398\r
399 @return Status -2 - Invalid argument\r
400\r
401 @return Status -3 - Call completed with error.\r
402 \r
403**/\r
404#define PAL_CACHE_SHARED_INFO 43\r
405\r
406\r
407/**\r
408 \r
409 PAL Procedure - PAL_CACHE_SUMMARY.\r
410 \r
411 Return a summary of the cache hierarchy. It is required by\r
412 IPF. The PAL procedure supports the Static Registers calling\r
413 convention. It could be called at physical mode and Virtual\r
414 mode.\r
415 \r
416 @param Index Index of PAL_CACHE_SUMMARY within the list of\r
417 PAL procedures.\r
418\r
419 \r
420 @return R9 CacheLevels Unsigned 64-bit integer denoting the\r
421 number of levels of cache\r
422 implemented by the processor.\r
423 Strictly, this is the number of\r
424 levels for which the cache\r
425 controller is integrated into the\r
426 processor (the cache SRAMs may be\r
427 external to the processor).\r
428\r
429 @return R10 UniqueCaches Unsigned 64-bit integer denoting the\r
430 number of unique caches implemented\r
431 by the processor. This has a maximum\r
432 of 2*cache_levels, but may be less\r
433 if any of the levels in the cache\r
434 hierarchy are unified caches or do\r
435 not have both instruction and data\r
436 caches.\r
437\r
438 @return Status 0 - Call completed without error\r
439\r
440 @return Status -2 - Invalid argument\r
441\r
442 @return Status -3 - Call completed with error.\r
443 \r
444**/\r
445#define PAL_CACHE_SUMMARY 4\r
446\r
447\r
448//\r
449// Virtual Memory Attributes implemented by processor. \r
450// \r
451#define PAL_MEMORY_ATTR_WB 0\r
452#define PAL_MEMORY_ATTR_WC 6\r
453#define PAL_MEMORY_ATTR_UC 4\r
454#define PAL_MEMORY_ATTR_UCE 5\r
455#define PAL_MEMORY_ATTR_NATPAGE 7\r
456\r
457/**\r
458 \r
459 PAL Procedure - PAL_MEM_ATTRIB.\r
460 \r
461 Return a list of supported memory attributes.. It is required\r
462 by IPF. The PAL procedure supports the Static Registers calling\r
463 convention. It could be called at physical mode and Virtual\r
464 mode.\r
465 \r
466 @param Index Index of PAL_MEM_ATTRIB within the list of PAL\r
467 procedures.\r
468\r
469 \r
470 @return R9 Attributes 8-bit vector of memory attributes\r
471 implemented by processor. See Virtual\r
472 Memory Attributes above.\r
473\r
474 @return Status 0 - Call completed without error\r
475\r
476 @return Status -2 - Invalid argument\r
477\r
478 @return Status -3 - Call completed with error.\r
479 \r
480**/\r
481\r
482#define PAL_MEM_ATTRIB 5\r
483\r
484/**\r
485 \r
486 PAL Procedure - PAL_PREFETCH_VISIBILITY.\r
487 \r
488 Used in architected sequence to transition pages from a\r
489 cacheable, speculative attribute to an uncacheable attribute.\r
490 It is required by IPF. The PAL procedure supports the Static\r
491 Registers calling convention. It could be called at physical\r
492 mode and Virtual mode.\r
493 \r
494 @param Index Index of PAL_PREFETCH_VISIBILITY within the list\r
495 of PAL procedures.\r
496\r
497 @param TransitionType Unsigned integer specifying the type\r
498 of memory attribute transition that is\r
499 being performed.\r
500 \r
501 @return Status 1 Call completed without error; this\r
502 call is not necessary on remote\r
503 processors.\r
504\r
505 @return Status 0 - Call completed without error\r
506\r
507 @return Status -2 - Invalid argument\r
508\r
509 @return Status -3 - Call completed with error.\r
510 \r
511**/\r
512#define PAL_PREFETCH_VISIBILITY 41\r
513\r
514/**\r
515 \r
516 PAL Procedure - PAL_PTCE_INFO.\r
517 \r
518 Return information needed for ptc.e instruction to purge\r
519 entire TC. It is required by IPF. The PAL procedure supports\r
520 the Static Registers calling convention. It could be called at\r
521 physical mode and Virtual mode.\r
522 \r
523 @param Index Index of PAL_PTCE_INFO within the list\r
524 of PAL procedures.\r
525\r
526 @return R9 Unsigned 64-bit integer denoting the beginning\r
527 address to be used by the first PTCE instruction\r
528 in the purge loop.\r
529 \r
530 @return R10 Two unsigned 32-bit integers denoting the loop\r
531 counts of the outer (loop 1) and inner (loop 2)\r
532 purge loops. count1 (loop 1) is contained in bits\r
533 63:32 of the parameter, and count2 (loop 2) is\r
534 contained in bits 31:0 of the parameter.\r
535 \r
536 @return R11 Two unsigned 32-bit integers denoting the loop\r
537 strides of the outer (loop 1) and inner (loop 2)\r
538 purge loops. stride1 (loop 1) is contained in bits\r
539 63:32 of the parameter, and stride2 (loop 2) is\r
540 contained in bits 31:0 of the parameter.\r
541\r
542 @return Status 0 - Call completed without error\r
543\r
544 @return Status -2 - Invalid argument\r
545\r
546 @return Status -3 - Call completed with error.\r
547 \r
548**/\r
549#define PAL_PTCE_INFO 6\r
550\r
551\r
552\r
553/**\r
554 \r
555 @param NumberSets Unsigned 8-bit integer denoting the number\r
556 of hash sets for the specified level\r
557 (1=fully associative)\r
558\r
559 @param NumberWays Unsigned 8-bit integer denoting the\r
560 associativity of the specified level\r
561 (1=direct).\r
562\r
563 @param NumberEntries Unsigned 16-bit integer denoting the\r
564 number of entries in the specified TC.\r
565\r
566\r
567 @param PageSizeIsOptimized Flag denoting whether the\r
568 specified level is optimized for\r
569 the region's preferred page size\r
570 (1=optimized) tc_pages indicates\r
571 which page sizes are usable by\r
572 this translation cache.\r
573\r
574 @param TcIsUnified Flag denoting whether the specified TC is\r
575 unified (1=unified).\r
576\r
577 @param EntriesReduction Flag denoting whether installed\r
578 translation registers will reduce\r
579 the number of entries within the\r
580 specified TC.\r
581\r
582**/\r
583typedef struct {\r
584 UINT64 NumberSets:8;\r
585 UINT64 NumberWays:8;\r
586 UINT64 NumberEntries:16;\r
587 UINT64 PageSizeIsOptimized:1;\r
588 UINT64 TcIsUnified:1;\r
589 UINT64 EntriesReduction:1;\r
590} PAL_TC_INFO;\r
591\r
592/**\r
593 \r
594 PAL Procedure - PAL_VM_INFO.\r
595 \r
596 Return detailed information about virtual memory features\r
597 supported in the processor. It is required by IPF. The PAL\r
598 procedure supports the Static Registers calling convention. It\r
599 could be called at physical mode and Virtual mode.\r
600 \r
601 @param Index Index of PAL_VM_INFO within the list\r
602 of PAL procedures.\r
603 \r
604 @param TcLevel Unsigned 64-bit integer specifying the level\r
605 in the TLB hierarchy for which information is\r
606 required. This value must be between 0 and one\r
607 less than the value returned in the\r
608 vm_info_1.num_tc_levels return value from\r
609 PAL_VM_SUMMARY.\r
610 \r
611 @param TcType Unsigned 64-bit integer with a value of 1 for\r
612 instruction translation cache and 2 for data\r
613 or unified translation cache. All other values\r
614 are reserved.\r
615\r
616 @return R9 8-byte formatted value returning information\r
617 about the specified TC. See PAL_TC_INFO above.\r
618\r
619 @return R10 64-bit vector containing a bit for each page\r
620 size supported in the specified TC, where bit\r
621 position n indicates a page size of 2**n.\r
622\r
623 @return Status 0 - Call completed without error\r
624\r
625 @return Status -2 - Invalid argument\r
626\r
627 @return Status -3 - Call completed with error.\r
628 \r
629**/\r
630#define PAL_VM_INFO 7\r
631\r
632\r
633/**\r
634 \r
635 PAL Procedure - PAL_VM_PAGE_SIZE.\r
636 \r
637 Return virtual memory TC and hardware walker page sizes\r
638 supported in the processor. It is required by IPF. The PAL\r
639 procedure supports the Static Registers calling convention. It\r
640 could be called at physical mode and Virtual mode.\r
641 \r
642 @param Index Index of PAL_VM_PAGE_SIZE within the list\r
643 of PAL procedures.\r
644 \r
645\r
646 @return R9 64-bit vector containing a bit for each\r
647 architected page size that is supported for\r
648 TLB insertions and region registers.\r
649\r
650 @return R10 64-bit vector containing a bit for each\r
651 architected page size supported for TLB purge\r
652 operations.\r
653\r
654 @return Status 0 - Call completed without error\r
655\r
656 @return Status -2 - Invalid argument\r
657\r
658 @return Status -3 - Call completed with error.\r
659 \r
660**/\r
661#define PAL_VM_PAGE_SIZE 34\r
662\r
663/**\r
664 \r
665 @param WalkerPresent 1-bit flag indicating whether a hardware\r
666 TLB walker is implemented (1 = walker\r
667 present).\r
668\r
669 @param WidthOfPhysicalAddress Unsigned 7-bit integer\r
670 denoting the number of bits of\r
671 physical address implemented.\r
672\r
673 @param WidthOfKey Unsigned 8-bit integer denoting the number\r
674 of bits mplemented in the PKR.key field.\r
675\r
676 @param MaxPkrIndex Unsigned 8-bit integer denoting the\r
677 maximum PKR index (number of PKRs-1).\r
678\r
679 @param HashTagId Unsigned 8-bit integer which uniquely\r
680 identifies the processor hash and tag\r
681 algorithm.\r
682\r
683 @param MaxDtrIndex Unsigned 8 bit integer denoting the\r
684 maximum data translation register index\r
685 (number of dtr entries - 1).\r
686\r
687 @param MaxItrIndex Unsigned 8 bit integer denoting the\r
688 maximum instruction translation register\r
689 index (number of itr entries - 1).\r
690\r
691 @param NumberOfUniqueTc Unsigned 8-bit integer denoting the\r
692 number of unique TCs implemented.\r
693 This is a maximum of\r
694 2*num_tc_levels.\r
695\r
696 @param NumberOfTcLevels Unsigned 8-bit integer denoting the\r
697 number of TC levels.\r
698\r
699**/\r
700typedef struct {\r
701 UINT64 WalkerPresent:1;\r
702 UINT64 WidthOfPhysicalAddress: 7;\r
703 UINT64 WidthOfKey:8;\r
704 UINT64 MaxPkrIndex:8;\r
705 UINT64 HashTagId:8;\r
706 UINT64 MaxDtrIndex:8;\r
707 UINT64 MaxItrIndex:8;\r
708 UINT64 NumberOfUniqueTc:8;\r
709 UINT64 NumberOfTcLevels:8;\r
710} PAL_VM_INFO1;\r
711\r
712/**\r
713 \r
714 @param WidthOfVirtualAddress Unsigned 8-bit integer denoting\r
715 is the total number of virtual\r
716 address bits - 1.\r
717\r
718 @param WidthOfRid Unsigned 8-bit integer denoting the number\r
719 of bits implemented in the RR.rid field.\r
720\r
721 @param MaxPurgedTlbs Unsigned 16 bit integer denoting the\r
722 maximum number of concurrent outstanding\r
723 TLB purges allowed by the processor. A\r
724 value of 0 indicates one outstanding\r
725 purge allowed. A value of 216-1\r
726 indicates no limit on outstanding\r
727 purges. All other values indicate the\r
728 actual number of concurrent outstanding\r
729 purges allowed.\r
730\r
731**/\r
732typedef struct {\r
733 UINT64 WidthOfVirtualAddress:8;\r
734 UINT64 WidthOfRid:8;\r
735 UINT64 MaxPurgedTlbs:16;\r
736 UINT64 Reserved:32;\r
737} PAL_VM_INFO2;\r
738\r
739/**\r
740 \r
741 PAL Procedure - PAL_VM_SUMMARY.\r
742 \r
743 Return summary information about virtual memory features\r
744 supported in the processor. It is required by IPF. The PAL\r
745 procedure supports the Static Registers calling convention. It\r
746 could be called at physical mode and Virtual mode.\r
747 \r
748 @param Index Index of PAL_VM_SUMMARY within the list\r
749 of PAL procedures.\r
750 \r
751\r
752 @return R9 8-byte formatted value returning global virtual\r
753 memory information. See PAL_VM_INFO1 above.\r
754\r
755 @return R10 8-byte formatted value returning global virtual\r
756 memory information. See PAL_VM_INFO2 above.\r
757\r
758 @return Status 0 - Call completed without error\r
759\r
760 @return Status -2 - Invalid argument\r
761\r
762 @return Status -3 - Call completed with error.\r
763 \r
764**/\r
765#define PAL_VM_SUMMARY 8\r
766\r
767\r
768//\r
769// Bit mask of TR_valid flag.\r
770// \r
771#define PAL_TR_ACCESS_RIGHT_IS_VALID BIT0\r
772#define PAL_TR_PRIVILEGE_LEVEL_IS_VALID BIT1\r
773#define PAL_TR_DIRTY_IS_VALID BIT2\r
774#define PAL_TR_MEMORY_ATTR_IS_VALID BIT3\r
775\r
776\r
777/**\r
778 \r
779 PAL Procedure - PAL_VM_TR_READ.\r
780 \r
781 Read contents of a translation register. It is required by\r
782 IPF. The PAL procedure supports the Stacked Register calling\r
783 convention. It could be called at physical mode.\r
784 \r
785 @param Index Index of PAL_VM_TR_READ within the list\r
786 of PAL procedures.\r
787\r
788 @param RegNumber Unsigned 64-bit number denoting which TR to\r
789 read.\r
790\r
791 @param TrType Unsigned 64-bit number denoting whether to\r
792 read an ITR (0) or DTR (1). All other values\r
793 are reserved.\r
794\r
795 @param TrBuffer 64-bit pointer to the 32-byte memory buffer in\r
796 which translation data is returned.\r
797\r
798 @return R9 Formatted bit vector denoting which fields are\r
799 valid. See TR_valid above.\r
800\r
801 @return Status 0 - Call completed without error\r
802\r
803 @return Status -2 - Invalid argument\r
804\r
805 @return Status -3 - Call completed with error.\r
806 \r
807**/\r
808#define PAL_VM_TR_READ 261 \r
809\r
810\r
811\r
812\r
813//\r
814// Bit Mask of Processor Bus Fesatures .\r
815// \r
816\r
817/**\r
818 \r
819 When 0, bus data errors are detected and single bit errors are\r
820 corrected. When 1, no error detection or correction is done.\r
821\r
822**/\r
823#define PAL_BUS_DISABLE_DATA_ERROR_SIGNALLING BIT63\r
824\r
825\r
826/**\r
827 \r
828 When 0, bus address errors are signalled on the bus. When 1,\r
829 no bus errors are signalled on the bus. If Disable Bus Address\r
830 Error Checking is 1, this bit is ignored.\r
831\r
832**/\r
833#define PAL_BUS_DISABLE_ADDRESS_ERROR_SIGNALLING BIT62\r
834\r
835\r
836\r
837\r
838/**\r
839 \r
840 When 0, bus errors are detected, single bit errors are\r
841 corrected., and a CMCI or MCA is generated internally to the\r
842 processor. When 1, no bus address errors are detected or\r
843 corrected.\r
844\r
845**/\r
846#define PAL_BUS_DISABLE_ADDRESS_ERROR_CHECK BIT61\r
847\r
848\r
849/**\r
850 \r
851 When 0, bus protocol errors (BINIT#) are signaled by the\r
852 processor on the bus. When 1, bus protocol errors (BINIT#) are\r
853 not signaled on the bus. If Disable Bus Initialization Event\r
854 Checking is 1, this bit is ignored.\r
855\r
856**/\r
857#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_SIGNALLING BIT60\r
858\r
859\r
860/**\r
861 \r
862 When 0, bus protocol errors (BINIT#) are detected and sampled\r
863 and an MCA is generated internally to the processor. When 1,\r
864 the processor will ignore bus protocol error conditions\r
865 (BINIT#).\r
866\r
867**/\r
868#define PAL_BUS_DISABLE_INITIALIZATION_EVENT_CHECK BIT59\r
869\r
870\r
871\r
872/**\r
873 \r
874 When 0, BERR# is signalled if a bus error is detected. When 1,\r
875 bus errors are not signalled on the bus.\r
876\r
877**/\r
878#define PAL_BUS_DISABLE_ERROR_SIGNALLING BIT58\r
879\r
880\r
881\r
882\r
883/**\r
884 \r
885 When 0, BERR# is signalled when internal processor requestor\r
886 initiated bus errors are detected. When 1, internal requester\r
887 bus errors are not signalled on the bus.\r
888 \r
889**/\r
890#define PAL_BUS_DISABLE__INTERNAL_ERROR_SIGNALLING BIT57\r
891\r
892\r
893/**\r
894 \r
895 When 0, the processor takes an MCA if BERR# is asserted. When\r
896 1, the processor ignores the BERR# signal.\r
897\r
898**/\r
899#define PAL_BUS_DISABLE_ERROR_CHECK BIT56\r
900\r
901\r
902/**\r
903 \r
904 When 0, the processor asserts BINIT# if it detects a parity\r
905 error on the signals which identify the transactions to which\r
906 this is a response. When 1, the processor ignores parity on\r
907 these signals.\r
908 \r
909**/\r
910#define PAL_BUS_DISABLE_RSP_ERROR_CHECK BIT55\r
911\r
912\r
913/**\r
914 \r
915 When 0, the in-order transaction queue is limited only by the\r
916 number of hardware entries. When 1, the processor's in-order\r
917 transactions queue is limited to one entry.\r
918\r
919**/\r
920#define PAL_BUS_DISABLE_TRANSACTION_QUEUE BIT54\r
921\r
922/**\r
923 \r
924 Enable a bus cache line replacement transaction when a cache\r
925 line in the exclusive state is replaced from the highest level\r
926 processor cache and is not present in the lower level processor\r
927 caches. When 0, no bus cache line replacement transaction will\r
928 be seen on the bus. When 1, bus cache line replacement\r
929 transactions will be seen on the bus when the above condition is\r
930 detected.\r
931\r
932**/\r
933#define PAL_BUS_ENABLE_EXCLUSIVE_CACHE_LINE_REPLACEMENT BIT53\r
934\r
935\r
936/**\r
937 \r
938 Enable a bus cache line replacement transaction when a cache\r
939 line in the shared or exclusive state is replaced from the\r
940 highest level processor cache and is not present in the lower\r
941 level processor caches.\r
942 When 0, no bus cache line replacement transaction will be seen\r
943 on the bus. When 1, bus cache line replacement transactions\r
944 will be seen on the bus when the above condition is detected.\r
945\r
946**/\r
947#define PAL_BUS_ENABLE_SHARED_CACHE_LINE_REPLACEMENT BIT52\r
948\r
949\r
950 \r
951/**\r
952 \r
953 When 0, the data bus is configured at the 2x data transfer\r
954 rate.When 1, the data bus is configured at the 1x data\r
955 transfer rate, 30 Opt. Req. Disable Bus Lock Mask. When 0, the\r
956 processor executes locked transactions atomically. When 1, the\r
957 processor masks the bus lock signal and executes locked\r
958 transactions as a non-atomic series of transactions.\r
959\r
960**/\r
961#define PAL_BUS_ENABLE_HALF_TRANSFER BIT30\r
962\r
963/**\r
964 \r
965 When 0, the processor will deassert bus request when finished\r
966 with each transaction. When 1, the processor will continue to\r
967 assert bus request after it has finished, if it was the last\r
968 agent to own the bus and if there are no other pending\r
969 requests.\r
970\r
971**/\r
972#define PAL_BUS_REQUEST_BUS_PARKING BIT29\r
973\r
974\r
975/**\r
976 \r
977 PAL Procedure - PAL_BUS_GET_FEATURES.\r
978 \r
979 Return configurable processor bus interface features and their\r
980 current settings. It is required by IPF. The PAL procedure\r
981 supports the Stacked Register calling convention. It could be\r
982 called at physical mode.\r
983 \r
984 @param Index Index of PAL_BUS_GET_FEATURES within the list\r
985 of PAL procedures.\r
986\r
987 @return R9 64-bit vector of features implemented.\r
988 (1=implemented, 0=not implemented)\r
989\r
990 @return R10 64-bit vector of current feature settings.\r
991\r
992 @return R11 64-bit vector of features controllable by\r
993 software. (1=controllable, 0= not controllable)\r
994\r
995 @return Status 0 - Call completed without error\r
996\r
997 @return Status -2 - Invalid argument\r
998\r
999 @return Status -3 - Call completed with error.\r
1000 \r
1001**/\r
1002#define PAL_BUS_GET_FEATURES 9\r
1003\r
1004/**\r
1005 \r
1006 PAL Procedure - PAL_BUS_SET_FEATURES.\r
1007 \r
1008 Enable or disable configurable features in processor bus\r
1009 interface. It is required by IPF. It is required by IPF. The PAL procedure\r
1010 supports the Static Registers calling convention. It could be\r
1011 called at physical mode.\r
1012 \r
1013 @param Index Index of PAL_BUS_SET_FEATURES within the list\r
1014 of PAL procedures.\r
1015 \r
1016 @param FeatureSelect 64-bit vector denoting desired state of\r
1017 each feature (1=select, 0=non-select).\r
1018\r
1019 @return Status 0 - Call completed without error\r
1020\r
1021 @return Status -2 - Invalid argument\r
1022\r
1023 @return Status -3 - Call completed with error.\r
1024 \r
1025**/\r
1026#define PAL_BUS_SET_FEATURES 10\r
1027\r
1028\r
1029/**\r
1030 \r
1031 PAL Procedure - PAL_DEBUG_INFO.\r
1032 \r
1033 Return the number of instruction and data breakpoint\r
1034 registers. It is required by IPF. It is required by IPF. The\r
1035 PAL procedure supports the Static Registers calling\r
1036 convention. It could be called at physical mode and virtual\r
1037 mode.\r
1038 \r
1039 @param Index Index of PAL_DEBUG_INFO within the list of PAL\r
1040 procedures.\r
1041 \r
1042 @return R9 Unsigned 64-bit integer denoting the number of\r
1043 pairs of instruction debug registers implemented\r
1044 by the processor. \r
1045 \r
1046 @return R10 Unsigned 64-bit integer denoting the number of\r
1047 pairs of data debug registers implemented by the\r
1048 processor.\r
1049 \r
1050 @return Status 0 - Call completed without error\r
1051\r
1052 @return Status -2 - Invalid argument\r
1053\r
1054 @return Status -3 - Call completed with error.\r
1055 \r
1056**/\r
1057#define PAL_DEBUG_INFO 11\r
1058\r
1059/**\r
1060 \r
1061 PAL Procedure - PAL_FIXED_ADDR.\r
1062 \r
1063