Program SD Cards into 4-bit mode (support for this is required in the spec). This...
[mirror_edk2.git] / Omap35xxPkg / Include / Omap3530 / Omap3530Dma.h
CommitLineData
ef0f565c 1/** @file
2
3 Copyright (c) 2008 - 2010, Apple Inc. All rights reserved.<BR>
4
5 This program and the accompanying materials
6 are licensed and made available under the terms and conditions of the BSD License
7 which accompanies this distribution. The full text of the license may be found at
8 http://opensource.org/licenses/bsd-license.php
9
10 THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
11 WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
12
13**/
14
15#ifndef __OMAP3530DMA_H__
16#define __OMAP3530DMA_H__
17
18#define DMA4_IRQENABLE_L(_i) (0x48056018 + (0x4*(i)))
19
20#define DMA4_CCR(_i) (0x48056080 + (0x60*(i)))
21#define DMA4_CICR(_i) (0x48056088 + (0x60*(i)))
22#define DMA4_CSDP(_i) (0x48056090 + (0x60*(i)))
23#define DMA4_CEN(_i) (0x48056094 + (0x60*(i)))
24#define DMA4_CFN(_i) (0x48056098 + (0x60*(i)))
25#define DMA4_CSSA(_i) (0x4805609c + (0x60*(i)))
26#define DMA4_CDSA(_i) (0x480560a0 + (0x60*(i)))
27#define DMA4_CSE(_i) (0x480560a4 + (0x60*(i)))
28#define DMA4_CSF(_i) (0x480560a8 + (0x60*(i)))
29#define DMA4_CDE(_i) (0x480560ac + (0x60*(i)))
30
20f461ce 31// Channel Source Destination parameters
32#define DMA4_CSDP_DATA_TYPE8 0
33#define DMA4_CSDP_DATA_TYPE16 1
34#define DMA4_CSDP_DATA_TYPE32 2
35
36#define DMA4_CSDP_SRC_PACKED BIT6
37#define DMA4_CSDP_SRC_NONPACKED 0
38
39#define DMA4_CSDP_SRC_BURST_EN (0x0 << 7)
40#define DMA4_CSDP_SRC_BURST_EN16 (0x1 << 7)
41#define DMA4_CSDP_SRC_BURST_EN32 (0x2 << 7)
42#define DMA4_CSDP_SRC_BURST_EN64 (0x3 << 7)
43
44#define DMA4_CSDP_DST_PACKED BIT13
45#define DMA4_CSDP_DST_NONPACKED 0
46
47#define DMA4_CSDP_BURST_EN (0x0 << 14)
48#define DMA4_CSDP_BURST_EN16 (0x1 << 14)
49#define DMA4_CSDP_BURST_EN32 (0x2 << 14)
50#define DMA4_CSDP_BURST_EN64 (0x3 << 14)
51
52#define DMA4_CSDP_WRITE_MODE_NONE_POSTED (0x0 << 16)
53#define DMA4_CSDP_WRITE_MODE_POSTED (0x1 << 16)
54#define DMA4_CSDP_WRITE_MODE_LAST_NON_POSTED (0x2 << 16)
55
56#define DMA4_CSDP_DST_ENDIAN_LOCK_LOCK BIT18
57#define DMA4_CSDP_DST_ENDIAN_LOCK_ADAPT 0
58
59#define DMA4_CSDP_DST_ENDIAN_BIG BIT19
60#define DMA4_CSDP_DST_ENDIAN_LITTLE 0
61
62#define DMA4_CSDP_SRC_ENDIAN_LOCK_LOCK BIT20
63#define DMA4_CSDP_SRC_ENDIAN_LOCK_ADAPT 0
64
65#define DMA4_CSDP_SRC_ENDIAN_BIG BIT21
66#define DMA4_CSDP_SRC_ENDIAN_LITTLE 0
67
68// Channel Control
69#define DMA4_CCR_SYNCHRO_CONTROL_MASK 0x1f
70
71#define DMA4_CCR_FS_ELEMENT (0 | 0)
72#define DMA4_CCR_FS_BLOCK (0 | BIT18)
73#define DMA4_CCR_FS_FRAME (BIT5 | 0)
74#define DMA4_CCR_FS_PACKET (BIT5 | BIT18)
75
76#define DMA4_CCR_READ_PRIORITY_HIGH BIT6
77#define DMA4_CCR_READ_PRIORITY_LOW 0
78
79#define DMA4_CCR_ENABLE BIT7
80#define DMA4_CCR_DISABLE 0
81
82#define DMA4_CCR_SUSPEND_SENSITIVE_IGNORE BIT8
83#define DMA4_CCR_SUSPEND_SENSITIVE 0
84
85#define DMA4_CCR_RD_ACTIVE BIT9
86#define DMA4_CCR_WR_ACTIVE BIT10
87
88#define DMA4_CCR_SRC_AMODE (0 | 0)
89#define DMA4_CCR_SRC_AMODE_POST_INC (0 | BIT12)
90#define DMA4_CCR_SRC_AMODE_SINGLE_INDEX (BIT13 | 0)
91#define DMA4_CCR_SRC_AMODE_DOUBLE_INDEX (BIT13 | BIT12)
92
93#define DMA4_CCR_DST_AMODE (0 | 0)
94#define DMA4_CCR_DST_AMODE_POST_INC (0 | BIT14)
95#define DMA4_CCR_DST_AMODE_SINGLE_INDEX (BIT15 | 0)
96#define DMA4_CCR_DST_AMODE_DOUBLE_INDEX (BIT15 | BIT14)
97
98#define DMA4_CCR_CONST_FILL_ENABLE BIT16
99#define DMA4_CCR_TRANSPARENT_COPY_ENABLE BIT17
2b649f74 100
ef0f565c 101#endif
102