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1 | /** @file\r |
| 2 | \r |
| 3 | Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r |
| 4 | \r |
| 5 | This program and the accompanying materials\r |
| 6 | are licensed and made available under the terms and conditions of the BSD License\r |
| 7 | which accompanies this distribution. The full text of the license may be found at\r |
| 8 | http://opensource.org/licenses/bsd-license.php\r |
| 9 | \r |
| 10 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r |
| 11 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r |
| 12 | \r |
| 13 | **/\r |
| 14 | \r |
| 15 | #ifndef __OMAP3530INTERRUPT_H__\r |
| 16 | #define __OMAP3530INTERRUPT_H__\r |
| 17 | \r |
| 18 | #define INTERRUPT_BASE (0x48200000)\r |
| 19 | \r |
| 20 | #define INT_NROF_VECTORS (96)\r |
| 21 | #define MAX_VECTOR (INT_NROF_VECTORS - 1)\r |
| 22 | #define INTCPS_SYSCONFIG (INTERRUPT_BASE + 0x0010)\r |
| 23 | #define INTCPS_SYSSTATUS (INTERRUPT_BASE + 0x0014)\r |
| 24 | #define INTCPS_SIR_IRQ (INTERRUPT_BASE + 0x0040)\r |
| 25 | #define INTCPS_SIR_IFQ (INTERRUPT_BASE + 0x0044)\r |
| 26 | #define INTCPS_CONTROL (INTERRUPT_BASE + 0x0048)\r |
| 27 | #define INTCPS_PROTECTION (INTERRUPT_BASE + 0x004C)\r |
| 28 | #define INTCPS_IDLE (INTERRUPT_BASE + 0x0050)\r |
| 29 | #define INTCPS_IRQ_PRIORITY (INTERRUPT_BASE + 0x0060)\r |
| 30 | #define INTCPS_FIQ_PRIORITY (INTERRUPT_BASE + 0x0064)\r |
| 31 | #define INTCPS_THRESHOLD (INTERRUPT_BASE + 0x0068)\r |
| 32 | #define INTCPS_ITR(n) (INTERRUPT_BASE + 0x0080 + (0x20 * (n)))\r |
| 33 | #define INTCPS_MIR(n) (INTERRUPT_BASE + 0x0084 + (0x20 * (n)))\r |
| 34 | #define INTCPS_MIR_CLEAR(n) (INTERRUPT_BASE + 0x0088 + (0x20 * (n)))\r |
| 35 | #define INTCPS_MIR_SET(n) (INTERRUPT_BASE + 0x008C + (0x20 * (n)))\r |
| 36 | #define INTCPS_ISR_SET(n) (INTERRUPT_BASE + 0x0090 + (0x20 * (n)))\r |
| 37 | #define INTCPS_ISR_CLEAR(n) (INTERRUPT_BASE + 0x0094 + (0x20 * (n)))\r |
| 38 | #define INTCPS_PENDING_IRQ(n) (INTERRUPT_BASE + 0x0098 + (0x20 * (n)))\r |
| 39 | #define INTCPS_PENDING_FIQ(n) (INTERRUPT_BASE + 0x009C + (0x20 * (n)))\r |
| 40 | #define INTCPS_ILR(m) (INTERRUPT_BASE + 0x0100 + (0x04 * (m)))\r |
| 41 | \r |
| 42 | #define INTCPS_ILR_FIQ BIT0\r |
| 43 | #define INTCPS_SIR_IRQ_MASK (0x7F)\r |
| 44 | #define INTCPS_CONTROL_NEWIRQAGR BIT0\r |
| 45 | #define INTCPS_CONTROL_NEWFIQAGR BIT1\r |
| 46 | \r |
| 47 | #endif // __OMAP3530INTERRUPT_H__\r |
| 48 | \r |
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