[mirror_edk2.git] / Omap35xxPkg / PciEmulation / PciEmulation.c

/** @file\r
\r
  Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
\r
  This program and the accompanying materials\r
  are licensed and made available under the terms and conditions of the BSD License\r
  which accompanies this distribution.  The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
  WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
\r
**/\r
\r
#include "PciEmulation.h"\r
\r
EMBEDDED_EXTERNAL_DEVICE   *gTPS65950;\r
\r
#define HOST_CONTROLLER_OPERATION_REG_SIZE  0x44\r
\r
typedef struct {\r
  ACPI_HID_DEVICE_PATH      AcpiDevicePath;\r
  PCI_DEVICE_PATH           PciDevicePath;\r
  EFI_DEVICE_PATH_PROTOCOL  EndDevicePath;\r
} EFI_PCI_IO_DEVICE_PATH;\r
\r
typedef struct {\r
  UINT32                  Signature;\r
  EFI_PCI_IO_DEVICE_PATH  DevicePath;\r
  EFI_PCI_IO_PROTOCOL     PciIoProtocol;\r
  PCI_TYPE00              *ConfigSpace;\r
  PCI_ROOT_BRIDGE         RootBridge;\r
  UINTN                   Segment;\r
} EFI_PCI_IO_PRIVATE_DATA;\r
\r
#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE     SIGNATURE_32('p', 'c', 'i', 'o')\r
#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a)  CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)\r
\r
EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =\r
{\r
  {\r
    { ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },\r
    EISA_PNP_ID(0x0A03),  // HID\r
    0                     // UID\r
  },\r
  {\r
    { HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },\r
    0,\r
    0\r
  },\r
  { END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }\r
};\r
\r
STATIC\r
VOID\r
ConfigureUSBHost (\r
  VOID\r
  )\r
{\r
  EFI_STATUS Status;\r
  UINT8      Data = 0;\r
\r
  // Take USB host out of force-standby mode\r
  MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY\r
                            | UHH_SYSCONFIG_CLOCKACTIVITY_ON\r
                            | UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY\r
                            | UHH_SYSCONFIG_ENAWAKEUP_ENABLE\r
                            | UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);\r
  MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT\r
                             | UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT\r
                             | UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT\r
                             | UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE\r
                             | UHH_HOSTCONFIG_ENA_INCR16_ENABLE\r
                             | UHH_HOSTCONFIG_ENA_INCR8_ENABLE\r
                             | UHH_HOSTCONFIG_ENA_INCR4_ENABLE\r
                             | UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON\r
                             | UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);\r
\r
  // USB reset (GPIO 147 - Port 5 pin 19) output high\r
  MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);\r
  MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);\r
\r
  // Get the Power IC protocol\r
  Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Power the USB PHY\r
  Data = VAUX_DEV_GRP_P1;\r
  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEV_GRP), 1, &Data);\r
  ASSERT_EFI_ERROR(Status);\r
\r
  Data = VAUX_DEDICATED_18V;\r
  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // Enable power to the USB hub\r
  Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  // LEDAON controls the power to the USB host, PWM is disabled\r
  Data &= ~LEDAPWM;\r
  Data |= LEDAON;\r
\r
  Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
EFI_STATUS\r
PciIoPollMem (\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT8                        BarIndex,\r
  IN  UINT64                       Offset,\r
  IN  UINT64                       Mask,\r
  IN  UINT64                       Value,\r
  IN  UINT64                       Delay,\r
  OUT UINT64                       *Result\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
PciIoPollIo (\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN  UINT8                        BarIndex,\r
  IN  UINT64                       Offset,\r
  IN  UINT64                       Mask,\r
  IN  UINT64                       Value,\r
  IN  UINT64                       Delay,\r
  OUT UINT64                       *Result\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
PciIoMemRead (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  )\r
{\r
  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
\r
  return PciRootBridgeIoMemRead (&Private->RootBridge.Io,\r
                                (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
                                Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
                                Count,\r
                                Buffer\r
                                );\r
}\r
\r
EFI_STATUS\r
PciIoMemWrite (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  )\r
{\r
  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
\r
  return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,\r
                                 (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
                                 Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
                                 Count,\r
                                 Buffer\r
                                 );\r
}\r
\r
EFI_STATUS\r
PciIoIoRead (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
PciIoIoWrite (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        BarIndex,\r
  IN     UINT64                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
/**\r
  Enable a PCI driver to read PCI controller registers in PCI configuration space.\r
\r
  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param[in]      Width   Signifies the width of the memory operations.\r
  @param[in]      Offset  The offset within the PCI configuration space for\r
                          the PCI controller.\r
  @param[in]      Count   The number of PCI configuration operations to\r
                          perform. Bytes moved is Width size * Count,\r
                          starting at Offset.\r
\r
  @param[in out]  Buffer  The destination buffer to store the results.\r
\r
  @retval  EFI_SUCCESS            The data was read from the PCI controller.\r
  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.\r
  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.\r
\r
**/\r
EFI_STATUS\r
PciIoPciRead (\r
  IN     EFI_PCI_IO_PROTOCOL       *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH  Width,\r
  IN     UINT32                     Offset,\r
  IN     UINTN                      Count,\r
  IN OUT VOID                      *Buffer\r
  )\r
{\r
  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
  EFI_STATUS Status;\r
\r
  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Status = PciRootBridgeIoMemRW (\r
             (EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
             Count,\r
             TRUE,\r
             (PTR)(UINTN)Buffer,\r
             TRUE,\r
             (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset)  //Fix me ConfigSpace\r
             );\r
\r
  return Status;\r
}\r
\r
/**\r
  Enable a PCI driver to write PCI controller registers in PCI configuration space.\r
\r
  @param[in]      This    A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param[in]      Width   Signifies the width of the memory operations.\r
  @param[in]      Offset  The offset within the PCI configuration space for\r
                          the PCI controller.\r
  @param[in]      Count   The number of PCI configuration operations to\r
                          perform. Bytes moved is Width size * Count,\r
                          starting at Offset.\r
\r
  @param[in out]  Buffer  The source buffer to write data from.\r
\r
  @retval  EFI_SUCCESS            The data was read from the PCI controller.\r
  @retval  EFI_INVALID_PARAMETER  "Width" is invalid.\r
  @retval  EFI_INVALID_PARAMETER  "Buffer" is NULL.\r
\r
**/\r
EFI_STATUS\r
PciIoPciWrite (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT32                       Offset,\r
  IN     UINTN                        Count,\r
  IN OUT VOID                         *Buffer\r
  )\r
{\r
  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
\r
  if ((Width < 0) || (Width >= EfiPciIoWidthMaximum) || (Buffer == NULL)) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
                               Count,\r
                               TRUE,\r
                               (PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),\r
                               TRUE,\r
                               (PTR)(UINTN)Buffer\r
                               );\r
}\r
\r
EFI_STATUS\r
PciIoCopyMem (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     EFI_PCI_IO_PROTOCOL_WIDTH    Width,\r
  IN     UINT8                        DestBarIndex,\r
  IN     UINT64                       DestOffset,\r
  IN     UINT8                        SrcBarIndex,\r
  IN     UINT64                       SrcOffset,\r
  IN     UINTN                        Count\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
PciIoMap (\r
  IN EFI_PCI_IO_PROTOCOL                *This,\r
  IN     EFI_PCI_IO_PROTOCOL_OPERATION  Operation,\r
  IN     VOID                           *HostAddress,\r
  IN OUT UINTN                          *NumberOfBytes,\r
  OUT    EFI_PHYSICAL_ADDRESS           *DeviceAddress,\r
  OUT    VOID                           **Mapping\r
  )\r
{\r
  DMA_MAP_OPERATION   DmaOperation;\r
\r
  if (Operation == EfiPciIoOperationBusMasterRead) {\r
    DmaOperation = MapOperationBusMasterRead;\r
  } else if (Operation == EfiPciIoOperationBusMasterWrite) {\r
    DmaOperation = MapOperationBusMasterWrite;\r
  } else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {\r
    DmaOperation = MapOperationBusMasterCommonBuffer;\r
  } else {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
  return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);\r
}\r
\r
EFI_STATUS\r
PciIoUnmap (\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  VOID                         *Mapping\r
  )\r
{\r
  return DmaUnmap (Mapping);\r
}\r
\r
/**\r
  Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
  mapping.\r
\r
  @param[in]   This         A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param[in]   Type         This parameter is not used and must be ignored.\r
  @param[in]   MemoryType   The type of memory to allocate, EfiBootServicesData or\r
                            EfiRuntimeServicesData.\r
  @param[in]   Pages        The number of pages to allocate.\r
  @param[out]  HostAddress  A pointer to store the base system memory address of\r
                            the allocated range.\r
  @param[in]   Attributes   The requested bit mask of attributes for the allocated\r
                            range. Only the attributes,\r
                            EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and\r
                            EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this\r
                            function. If any other bits are set, then EFI_UNSUPPORTED\r
                            is returned. This function ignores this bit mask.\r
\r
  @retval  EFI_SUCCESS            The requested memory pages were allocated.\r
  @retval  EFI_INVALID_PARAMETER  HostAddress is NULL.\r
  @retval  EFI_INVALID_PARAMETER  MemoryType is invalid.\r
  @retval  EFI_UNSUPPORTED        Attributes is unsupported.\r
  @retval  EFI_OUT_OF_RESOURCES   The memory pages could not be allocated.\r
\r
**/\r
EFI_STATUS\r
PciIoAllocateBuffer (\r
  IN EFI_PCI_IO_PROTOCOL  *This,\r
  IN  EFI_ALLOCATE_TYPE   Type,\r
  IN  EFI_MEMORY_TYPE     MemoryType,\r
  IN  UINTN               Pages,\r
  OUT VOID                **HostAddress,\r
  IN  UINT64              Attributes\r
  )\r
{\r
  if (Attributes &\r
      (~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE |\r
         EFI_PCI_ATTRIBUTE_MEMORY_CACHED         ))) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  return DmaAllocateBuffer (MemoryType, Pages, HostAddress);\r
}\r
\r
\r
EFI_STATUS\r
PciIoFreeBuffer (\r
  IN EFI_PCI_IO_PROTOCOL           *This,\r
  IN  UINTN                        Pages,\r
  IN  VOID                         *HostAddress\r
  )\r
{\r
  return DmaFreeBuffer (Pages, HostAddress);\r
}\r
\r
\r
EFI_STATUS\r
PciIoFlush (\r
  IN EFI_PCI_IO_PROTOCOL  *This\r
  )\r
{\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
\r
  @param[in]   This            A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param[out]  SegmentNumber   The PCI controller's current PCI segment number.\r
  @param[out]  BusNumber       The PCI controller's current PCI bus number.\r
  @param[out]  DeviceNumber    The PCI controller's current PCI device number.\r
  @param[out]  FunctionNumber  The PCI controller’s current PCI function number.\r
\r
  @retval  EFI_SUCCESS            The PCI controller location was returned.\r
  @retval  EFI_INVALID_PARAMETER  At least one out of the four output parameters is\r
                                  a NULL pointer.\r
**/\r
EFI_STATUS\r
PciIoGetLocation (\r
  IN   EFI_PCI_IO_PROTOCOL  *This,\r
  OUT  UINTN                *SegmentNumber,\r
  OUT  UINTN                *BusNumber,\r
  OUT  UINTN                *DeviceNumber,\r
  OUT  UINTN                *FunctionNumber\r
  )\r
{\r
  EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
\r
  if ((SegmentNumber == NULL) || (BusNumber      == NULL) ||\r
      (DeviceNumber  == NULL) || (FunctionNumber == NULL)    ) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *SegmentNumber  = Private->Segment;\r
  *BusNumber      = 0xff;\r
  *DeviceNumber   = 0;\r
  *FunctionNumber = 0;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Performs an operation on the attributes that this PCI controller supports.\r
\r
  The operations include getting the set of supported attributes, retrieving\r
  the current attributes, setting the current attributes, enabling attributes,\r
  and disabling attributes.\r
\r
  @param[in]   This        A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
  @param[in]   Operation   The operation to perform on the attributes for this\r
                           PCI controller.\r
  @param[in]   Attributes  The mask of attributes that are used for Set,\r
                           Enable and Disable operations.\r
  @param[out]  Result      A pointer to the result mask of attributes that are\r
                           returned for the Get and Supported operations. This\r
                           is an optional parameter that may be NULL for the\r
                           Set, Enable, and Disable operations.\r
\r
  @retval  EFI_SUCCESS            The operation on the PCI controller's\r
                                  attributes was completed. If the operation\r
                                  was Get or Supported, then the attribute mask\r
                                  is returned in Result.\r
  @retval  EFI_INVALID_PARAMETER  Operation is greater than or equal to\r
                                  EfiPciIoAttributeOperationMaximum.\r
  @retval  EFI_INVALID_PARAMETER  Operation is Get and Result is NULL.\r
  @retval  EFI_INVALID_PARAMETER  Operation is Supported and Result is NULL.\r
\r
**/\r
EFI_STATUS\r
PciIoAttributes (\r
  IN EFI_PCI_IO_PROTOCOL                       *This,\r
  IN  EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION  Operation,\r
  IN  UINT64                                   Attributes,\r
  OUT UINT64                                   *Result OPTIONAL\r
  )\r
{\r
  switch (Operation) {\r
  case EfiPciIoAttributeOperationGet:\r
  case EfiPciIoAttributeOperationSupported:\r
    if (Result == NULL) {\r
      return EFI_INVALID_PARAMETER;\r
    }\r
    //\r
    // We are not a real PCI device so just say things we kind of do\r
    //\r
    *Result = EFI_PCI_DEVICE_ENABLE;\r
    break;\r
\r
  case EfiPciIoAttributeOperationSet:\r
  case EfiPciIoAttributeOperationEnable:\r
  case EfiPciIoAttributeOperationDisable:\r
    if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) {\r
      return EFI_UNSUPPORTED;\r
    }\r
    // Since we are not a real PCI device no enable/set or disable operations exist.\r
    return EFI_SUCCESS;\r
\r
  default:\r
    return EFI_INVALID_PARAMETER;\r
  };\r
  return EFI_SUCCESS;\r
}\r
\r
EFI_STATUS\r
PciIoGetBarAttributes (\r
  IN EFI_PCI_IO_PROTOCOL             *This,\r
  IN  UINT8                          BarIndex,\r
  OUT UINT64                         *Supports, OPTIONAL\r
  OUT VOID                           **Resources OPTIONAL\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_STATUS\r
PciIoSetBarAttributes (\r
  IN EFI_PCI_IO_PROTOCOL              *This,\r
  IN     UINT64                       Attributes,\r
  IN     UINT8                        BarIndex,\r
  IN OUT UINT64                       *Offset,\r
  IN OUT UINT64                       *Length\r
  )\r
{\r
  ASSERT (FALSE);\r
  return EFI_UNSUPPORTED;\r
}\r
\r
EFI_PCI_IO_PROTOCOL PciIoTemplate =\r
{\r
  PciIoPollMem,\r
  PciIoPollIo,\r
  { PciIoMemRead, PciIoMemWrite },\r
  { PciIoIoRead,  PciIoIoWrite },\r
  { PciIoPciRead, PciIoPciWrite },\r
  PciIoCopyMem,\r
  PciIoMap,\r
  PciIoUnmap,\r
  PciIoAllocateBuffer,\r
  PciIoFreeBuffer,\r
  PciIoFlush,\r
  PciIoGetLocation,\r
  PciIoAttributes,\r
  PciIoGetBarAttributes,\r
  PciIoSetBarAttributes,\r
  0,\r
  0\r
};\r
\r
EFI_STATUS\r
EFIAPI\r
PciEmulationEntryPoint (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  EFI_STATUS              Status;\r
  EFI_HANDLE              Handle;\r
  EFI_PCI_IO_PRIVATE_DATA *Private;\r
  UINT8                   CapabilityLength;\r
  UINT8                   PhysicalPorts;\r
  UINTN                   Count;\r
\r
\r
  //Configure USB host for OMAP3530.\r
  ConfigureUSBHost();\r
\r
  // Create a private structure\r
  Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));\r
  if (Private == NULL) {\r
    Status = EFI_OUT_OF_RESOURCES;\r
    return Status;\r
  }\r
\r
  Private->Signature              = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE;  // Fill in signature\r
  Private->RootBridge.Signature   = PCI_ROOT_BRIDGE_SIGNATURE;          // Fake Root Bridge structure needs a signature too\r
  Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE;                 // Get the USB capability register base\r
  Private->Segment                = 0;                                  // Default to segment zero\r
\r
  // Find out the capability register length and number of physical ports.\r
  CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);\r
  PhysicalPorts    = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;\r
\r
  // Calculate the total size of the USB registers.\r
  Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));\r
\r
  // Enable Port Power bit in Port status and control registers in EHCI register space.\r
  // Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates\r
  // host controller implementation includes port power control.\r
  for (Count = 0; Count < PhysicalPorts; Count++) {\r
    MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);\r
  }\r
\r
  // Create fake PCI config space.\r
  Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));\r
  if (Private->ConfigSpace == NULL) {\r
    Status = EFI_OUT_OF_RESOURCES;\r
    FreePool(Private);\r
    return Status;\r
  }\r
\r
  // Configure PCI config space\r
  Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device.\r
  Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid.\r
  Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;\r
  Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;\r
  Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;\r
  Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;\r
\r
  Handle = NULL;\r
\r
  // Unique device path.\r
  CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));\r
  Private->DevicePath.AcpiDevicePath.UID = 0;\r
\r
  // Copy protocol structure\r
  CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));\r
\r
  Status = gBS->InstallMultipleProtocolInterfaces(&Handle,\r
                                                  &gEfiPciIoProtocolGuid,       &Private->PciIoProtocol,\r
                                                  &gEfiDevicePathProtocolGuid,  &Private->DevicePath,\r
                                                  NULL);\r
  if (EFI_ERROR(Status)) {\r
    DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));\r
  }\r
\r
  return Status;\r
}\r
\r
Commit	Line	Data
1e57a462	1	/** @file\r
	2	\r
	3	Copyright (c) 2008 - 2009, Apple Inc. All rights reserved.<BR>\r
3402aac7	4	\r
1e57a462	5	This program and the accompanying materials\r
	6	are licensed and made available under the terms and conditions of the BSD License\r
	7	which accompanies this distribution. The full text of the license may be found at\r
	8	http://opensource.org/licenses/bsd-license.php\r
	9	\r
	10	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r
	11	WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	12	\r
	13	**/\r
	14	\r
	15	#include "PciEmulation.h"\r
	16	\r
	17	EMBEDDED_EXTERNAL_DEVICE *gTPS65950;\r
	18	\r
	19	#define HOST_CONTROLLER_OPERATION_REG_SIZE 0x44\r
	20	\r
	21	typedef struct {\r
	22	ACPI_HID_DEVICE_PATH AcpiDevicePath;\r
	23	PCI_DEVICE_PATH PciDevicePath;\r
	24	EFI_DEVICE_PATH_PROTOCOL EndDevicePath;\r
	25	} EFI_PCI_IO_DEVICE_PATH;\r
	26	\r
	27	typedef struct {\r
	28	UINT32 Signature;\r
	29	EFI_PCI_IO_DEVICE_PATH DevicePath;\r
	30	EFI_PCI_IO_PROTOCOL PciIoProtocol;\r
	31	PCI_TYPE00 *ConfigSpace;\r
	32	PCI_ROOT_BRIDGE RootBridge;\r
	33	UINTN Segment;\r
	34	} EFI_PCI_IO_PRIVATE_DATA;\r
	35	\r
	36	#define EFI_PCI_IO_PRIVATE_DATA_SIGNATURE SIGNATURE_32('p', 'c', 'i', 'o')\r
	37	#define EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(a) CR(a, EFI_PCI_IO_PRIVATE_DATA, PciIoProtocol, EFI_PCI_IO_PRIVATE_DATA_SIGNATURE)\r
	38	\r
3402aac7	39	EFI_PCI_IO_DEVICE_PATH PciIoDevicePathTemplate =\r
1e57a462	40	{\r
1e57a462	41	{\r
b0fdce95	42	{ ACPI_DEVICE_PATH, ACPI_DP, { sizeof (ACPI_HID_DEVICE_PATH), 0 } },\r
1e57a462	43	EISA_PNP_ID(0x0A03), // HID\r
	44	0 // UID\r
	45	},\r
	46	{\r
b0fdce95	47	{ HARDWARE_DEVICE_PATH, HW_PCI_DP, { sizeof (PCI_DEVICE_PATH), 0 } },\r
1e57a462	48	0,\r
	49	0\r
	50	},\r
b0fdce95	51	{ END_DEVICE_PATH_TYPE, END_ENTIRE_DEVICE_PATH_SUBTYPE, { sizeof (EFI_DEVICE_PATH_PROTOCOL), 0} }\r
1e57a462	52	};\r
	53	\r
	54	STATIC\r
	55	VOID\r
	56	ConfigureUSBHost (\r
	57	VOID\r
	58	)\r
	59	{\r
	60	EFI_STATUS Status;\r
	61	UINT8 Data = 0;\r
	62	\r
	63	// Take USB host out of force-standby mode\r
	64	MmioWrite32 (UHH_SYSCONFIG, UHH_SYSCONFIG_MIDLEMODE_NO_STANDBY\r
	65	\| UHH_SYSCONFIG_CLOCKACTIVITY_ON\r
	66	\| UHH_SYSCONFIG_SIDLEMODE_NO_STANDBY\r
	67	\| UHH_SYSCONFIG_ENAWAKEUP_ENABLE\r
	68	\| UHH_SYSCONFIG_AUTOIDLE_ALWAYS_RUN);\r
	69	MmioWrite32 (UHH_HOSTCONFIG, UHH_HOSTCONFIG_P3_CONNECT_STATUS_DISCONNECT\r
	70	\| UHH_HOSTCONFIG_P2_CONNECT_STATUS_DISCONNECT\r
	71	\| UHH_HOSTCONFIG_P1_CONNECT_STATUS_DISCONNECT\r
	72	\| UHH_HOSTCONFIG_ENA_INCR_ALIGN_DISABLE\r
	73	\| UHH_HOSTCONFIG_ENA_INCR16_ENABLE\r
	74	\| UHH_HOSTCONFIG_ENA_INCR8_ENABLE\r
	75	\| UHH_HOSTCONFIG_ENA_INCR4_ENABLE\r
	76	\| UHH_HOSTCONFIG_AUTOPPD_ON_OVERCUR_EN_ON\r
	77	\| UHH_HOSTCONFIG_P1_ULPI_BYPASS_ULPI_MODE);\r
	78	\r
	79	// USB reset (GPIO 147 - Port 5 pin 19) output high\r
	80	MmioAnd32 (GPIO5_BASE + GPIO_OE, ~BIT19);\r
	81	MmioWrite32 (GPIO5_BASE + GPIO_SETDATAOUT, BIT19);\r
	82	\r
	83	// Get the Power IC protocol\r
	84	Status = gBS->LocateProtocol (&gEmbeddedExternalDeviceProtocolGuid, NULL, (VOID **)&gTPS65950);\r
3402aac7	85	ASSERT_EFI_ERROR (Status);\r
1e57a462	86	\r
	87	// Power the USB PHY\r
	88	Data = VAUX_DEV_GRP_P1;\r
	89	Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEV_GRP), 1, &Data);\r
	90	ASSERT_EFI_ERROR(Status);\r
	91	\r
	92	Data = VAUX_DEDICATED_18V;\r
	93	Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID4, VAUX2_DEDICATED), 1, &Data);\r
3402aac7	94	ASSERT_EFI_ERROR (Status);\r
1e57a462	95	\r
	96	// Enable power to the USB hub\r
	97	Status = gTPS65950->Read (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
	98	ASSERT_EFI_ERROR (Status);\r
	99	\r
	100	// LEDAON controls the power to the USB host, PWM is disabled\r
	101	Data &= ~LEDAPWM;\r
	102	Data \|= LEDAON;\r
	103	\r
	104	Status = gTPS65950->Write (gTPS65950, EXTERNAL_DEVICE_REGISTER(I2C_ADDR_GRP_ID3, LEDEN), 1, &Data);\r
	105	ASSERT_EFI_ERROR (Status);\r
	106	}\r
	107	\r
	108	\r
	109	EFI_STATUS\r
	110	PciIoPollMem (\r
	111	IN EFI_PCI_IO_PROTOCOL *This,\r
	112	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	113	IN UINT8 BarIndex,\r
	114	IN UINT64 Offset,\r
	115	IN UINT64 Mask,\r
	116	IN UINT64 Value,\r
	117	IN UINT64 Delay,\r
	118	OUT UINT64 *Result\r
	119	)\r
	120	{\r
	121	ASSERT (FALSE);\r
	122	return EFI_UNSUPPORTED;\r
	123	}\r
	124	\r
	125	EFI_STATUS\r
	126	PciIoPollIo (\r
	127	IN EFI_PCI_IO_PROTOCOL *This,\r
	128	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	129	IN UINT8 BarIndex,\r
	130	IN UINT64 Offset,\r
	131	IN UINT64 Mask,\r
	132	IN UINT64 Value,\r
	133	IN UINT64 Delay,\r
	134	OUT UINT64 *Result\r
	135	)\r
	136	{\r
	137	ASSERT (FALSE);\r
	138	return EFI_UNSUPPORTED;\r
	139	}\r
	140	\r
	141	EFI_STATUS\r
	142	PciIoMemRead (\r
	143	IN EFI_PCI_IO_PROTOCOL *This,\r
	144	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	145	IN UINT8 BarIndex,\r
	146	IN UINT64 Offset,\r
	147	IN UINTN Count,\r
	148	IN OUT VOID *Buffer\r
	149	)\r
	150	{\r
	151	EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
	152	\r
3402aac7	153	return PciRootBridgeIoMemRead (&Private->RootBridge.Io,\r
1e57a462	154	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
	155	Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
	156	Count,\r
	157	Buffer\r
	158	);\r
	159	}\r
	160	\r
	161	EFI_STATUS\r
	162	PciIoMemWrite (\r
	163	IN EFI_PCI_IO_PROTOCOL *This,\r
	164	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	165	IN UINT8 BarIndex,\r
	166	IN UINT64 Offset,\r
	167	IN UINTN Count,\r
	168	IN OUT VOID *Buffer\r
	169	)\r
	170	{\r
	171	EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS(This);\r
	172	\r
3402aac7	173	return PciRootBridgeIoMemWrite (&Private->RootBridge.Io,\r
1e57a462	174	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
	175	Private->ConfigSpace->Device.Bar[BarIndex] + Offset,\r
	176	Count,\r
	177	Buffer\r
	178	);\r
	179	}\r
	180	\r
	181	EFI_STATUS\r
	182	PciIoIoRead (\r
	183	IN EFI_PCI_IO_PROTOCOL *This,\r
	184	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	185	IN UINT8 BarIndex,\r
	186	IN UINT64 Offset,\r
	187	IN UINTN Count,\r
	188	IN OUT VOID *Buffer\r
	189	)\r
	190	{\r
	191	ASSERT (FALSE);\r
	192	return EFI_UNSUPPORTED;\r
	193	}\r
	194	\r
	195	EFI_STATUS\r
	196	PciIoIoWrite (\r
	197	IN EFI_PCI_IO_PROTOCOL *This,\r
	198	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	199	IN UINT8 BarIndex,\r
	200	IN UINT64 Offset,\r
	201	IN UINTN Count,\r
	202	IN OUT VOID *Buffer\r
	203	)\r
	204	{\r
	205	ASSERT (FALSE);\r
	206	return EFI_UNSUPPORTED;\r
	207	}\r
	208	\r
8a8641b5 RC	209	/**\r
	210	Enable a PCI driver to read PCI controller registers in PCI configuration space.\r
	211	\r
	212	@param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
	213	@param[in] Width Signifies the width of the memory operations.\r
	214	@param[in] Offset The offset within the PCI configuration space for\r
	215	the PCI controller.\r
	216	@param[in] Count The number of PCI configuration operations to\r
	217	perform. Bytes moved is Width size * Count,\r
	218	starting at Offset.\r
	219	\r
	220	@param[in out] Buffer The destination buffer to store the results.\r
	221	\r
	222	@retval EFI_SUCCESS The data was read from the PCI controller.\r
	223	@retval EFI_INVALID_PARAMETER "Width" is invalid.\r
	224	@retval EFI_INVALID_PARAMETER "Buffer" is NULL.\r
	225	\r
	226	**/\r
1e57a462	227	EFI_STATUS\r
1e57a462	228	PciIoPciRead (\r
8a8641b5 RC	229	IN EFI_PCI_IO_PROTOCOL *This,\r
	230	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	231	IN UINT32 Offset,\r
	232	IN UINTN Count,\r
	233	IN OUT VOID *Buffer\r
1e57a462	234	)\r
1e57a462	235	{\r
8a8641b5 RC	236	EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
8a8641b5 RC	237	EFI_STATUS Status;\r
1e57a462	238	\r
8a8641b5 RC	239	if ((Width < 0) \|\| (Width >= EfiPciIoWidthMaximum) \|\| (Buffer == NULL)) {\r
	240	return EFI_INVALID_PARAMETER;\r
	241	}\r
	242	\r
	243	Status = PciRootBridgeIoMemRW (\r
	244	(EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH)Width,\r
	245	Count,\r
	246	TRUE,\r
	247	(PTR)(UINTN)Buffer,\r
	248	TRUE,\r
	249	(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset) //Fix me ConfigSpace\r
	250	);\r
	251	\r
	252	return Status;\r
1e57a462	253	}\r
1e57a462	254	\r
8a8641b5 RC	255	/**\r
	256	Enable a PCI driver to write PCI controller registers in PCI configuration space.\r
	257	\r
	258	@param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
	259	@param[in] Width Signifies the width of the memory operations.\r
	260	@param[in] Offset The offset within the PCI configuration space for\r
	261	the PCI controller.\r
	262	@param[in] Count The number of PCI configuration operations to\r
	263	perform. Bytes moved is Width size * Count,\r
	264	starting at Offset.\r
	265	\r
	266	@param[in out] Buffer The source buffer to write data from.\r
	267	\r
	268	@retval EFI_SUCCESS The data was read from the PCI controller.\r
	269	@retval EFI_INVALID_PARAMETER "Width" is invalid.\r
	270	@retval EFI_INVALID_PARAMETER "Buffer" is NULL.\r
	271	\r
	272	**/\r
1e57a462	273	EFI_STATUS\r
	274	PciIoPciWrite (\r
	275	IN EFI_PCI_IO_PROTOCOL *This,\r
	276	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	277	IN UINT32 Offset,\r
	278	IN UINTN Count,\r
	279	IN OUT VOID *Buffer\r
	280	)\r
	281	{\r
8a8641b5 RC	282	EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
	283	\r
	284	if ((Width < 0) \|\| (Width >= EfiPciIoWidthMaximum) \|\| (Buffer == NULL)) {\r
	285	return EFI_INVALID_PARAMETER;\r
	286	}\r
1e57a462	287	\r
3402aac7 RC	288	return PciRootBridgeIoMemRW ((EFI_PCI_ROOT_BRIDGE_IO_PROTOCOL_WIDTH) Width,\r
	289	Count,\r
	290	TRUE,\r
	291	(PTR)(UINTN)(((UINT8 *)Private->ConfigSpace) + Offset),\r
	292	TRUE,\r
1e57a462	293	(PTR)(UINTN)Buffer\r
	294	);\r
	295	}\r
	296	\r
	297	EFI_STATUS\r
	298	PciIoCopyMem (\r
	299	IN EFI_PCI_IO_PROTOCOL *This,\r
	300	IN EFI_PCI_IO_PROTOCOL_WIDTH Width,\r
	301	IN UINT8 DestBarIndex,\r
	302	IN UINT64 DestOffset,\r
	303	IN UINT8 SrcBarIndex,\r
	304	IN UINT64 SrcOffset,\r
	305	IN UINTN Count\r
	306	)\r
	307	{\r
	308	ASSERT (FALSE);\r
	309	return EFI_UNSUPPORTED;\r
	310	}\r
	311	\r
	312	EFI_STATUS\r
	313	PciIoMap (\r
	314	IN EFI_PCI_IO_PROTOCOL *This,\r
	315	IN EFI_PCI_IO_PROTOCOL_OPERATION Operation,\r
	316	IN VOID *HostAddress,\r
	317	IN OUT UINTN *NumberOfBytes,\r
	318	OUT EFI_PHYSICAL_ADDRESS *DeviceAddress,\r
	319	OUT VOID **Mapping\r
	320	)\r
	321	{\r
	322	DMA_MAP_OPERATION DmaOperation;\r
	323	\r
	324	if (Operation == EfiPciIoOperationBusMasterRead) {\r
	325	DmaOperation = MapOperationBusMasterRead;\r
	326	} else if (Operation == EfiPciIoOperationBusMasterWrite) {\r
	327	DmaOperation = MapOperationBusMasterWrite;\r
	328	} else if (Operation == EfiPciIoOperationBusMasterCommonBuffer) {\r
	329	DmaOperation = MapOperationBusMasterCommonBuffer;\r
	330	} else {\r
	331	return EFI_INVALID_PARAMETER;\r
	332	}\r
	333	return DmaMap (DmaOperation, HostAddress, NumberOfBytes, DeviceAddress, Mapping);\r
	334	}\r
	335	\r
	336	EFI_STATUS\r
	337	PciIoUnmap (\r
	338	IN EFI_PCI_IO_PROTOCOL *This,\r
	339	IN VOID *Mapping\r
	340	)\r
	341	{\r
	342	return DmaUnmap (Mapping);\r
	343	}\r
	344	\r
8a8641b5 RC	345	/**\r
	346	Allocate pages that are suitable for an EfiPciIoOperationBusMasterCommonBuffer\r
	347	mapping.\r
	348	\r
	349	@param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
	350	@param[in] Type This parameter is not used and must be ignored.\r
	351	@param[in] MemoryType The type of memory to allocate, EfiBootServicesData or\r
	352	EfiRuntimeServicesData.\r
	353	@param[in] Pages The number of pages to allocate.\r
	354	@param[out] HostAddress A pointer to store the base system memory address of\r
	355	the allocated range.\r
	356	@param[in] Attributes The requested bit mask of attributes for the allocated\r
	357	range. Only the attributes,\r
	358	EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE and\r
	359	EFI_PCI_ATTRIBUTE_MEMORY_CACHED may be used with this\r
	360	function. If any other bits are set, then EFI_UNSUPPORTED\r
	361	is returned. This function ignores this bit mask.\r
	362	\r
	363	@retval EFI_SUCCESS The requested memory pages were allocated.\r
	364	@retval EFI_INVALID_PARAMETER HostAddress is NULL.\r
	365	@retval EFI_INVALID_PARAMETER MemoryType is invalid.\r
	366	@retval EFI_UNSUPPORTED Attributes is unsupported.\r
	367	@retval EFI_OUT_OF_RESOURCES The memory pages could not be allocated.\r
	368	\r
	369	**/\r
1e57a462	370	EFI_STATUS\r
1e57a462	371	PciIoAllocateBuffer (\r
8a8641b5 RC	372	IN EFI_PCI_IO_PROTOCOL *This,\r
	373	IN EFI_ALLOCATE_TYPE Type,\r
	374	IN EFI_MEMORY_TYPE MemoryType,\r
	375	IN UINTN Pages,\r
	376	OUT VOID **HostAddress,\r
	377	IN UINT64 Attributes\r
1e57a462	378	)\r
1e57a462	379	{\r
8a8641b5 RC	380	if (Attributes &\r
	381	(~(EFI_PCI_ATTRIBUTE_MEMORY_WRITE_COMBINE \|\r
	382	EFI_PCI_ATTRIBUTE_MEMORY_CACHED ))) {\r
1e57a462	383	return EFI_UNSUPPORTED;\r
	384	}\r
	385	\r
	386	return DmaAllocateBuffer (MemoryType, Pages, HostAddress);\r
	387	}\r
	388	\r
	389	\r
	390	EFI_STATUS\r
	391	PciIoFreeBuffer (\r
	392	IN EFI_PCI_IO_PROTOCOL *This,\r
	393	IN UINTN Pages,\r
	394	IN VOID *HostAddress\r
	395	)\r
	396	{\r
	397	return DmaFreeBuffer (Pages, HostAddress);\r
	398	}\r
	399	\r
	400	\r
	401	EFI_STATUS\r
	402	PciIoFlush (\r
	403	IN EFI_PCI_IO_PROTOCOL *This\r
	404	)\r
	405	{\r
	406	return EFI_SUCCESS;\r
	407	}\r
	408	\r
8a8641b5 RC	409	/**\r
	410	Retrieves this PCI controller's current PCI bus number, device number, and function number.\r
	411	\r
	412	@param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
	413	@param[out] SegmentNumber The PCI controller's current PCI segment number.\r
	414	@param[out] BusNumber The PCI controller's current PCI bus number.\r
	415	@param[out] DeviceNumber The PCI controller's current PCI device number.\r
	416	@param[out] FunctionNumber The PCI controller’s current PCI function number.\r
	417	\r
	418	@retval EFI_SUCCESS The PCI controller location was returned.\r
	419	@retval EFI_INVALID_PARAMETER At least one out of the four output parameters is\r
	420	a NULL pointer.\r
	421	**/\r
1e57a462	422	EFI_STATUS\r
1e57a462	423	PciIoGetLocation (\r
8a8641b5 RC	424	IN EFI_PCI_IO_PROTOCOL *This,\r
	425	OUT UINTN *SegmentNumber,\r
	426	OUT UINTN *BusNumber,\r
	427	OUT UINTN *DeviceNumber,\r
	428	OUT UINTN *FunctionNumber\r
1e57a462	429	)\r
1e57a462	430	{\r
8a8641b5	431	EFI_PCI_IO_PRIVATE_DATA *Private = EFI_PCI_IO_PRIVATE_DATA_FROM_THIS (This);\r
1e57a462	432	\r
8a8641b5 RC	433	if ((SegmentNumber == NULL) \|\| (BusNumber == NULL) \|\|\r
	434	(DeviceNumber == NULL) \|\| (FunctionNumber == NULL) ) {\r
	435	return EFI_INVALID_PARAMETER;\r
1e57a462	436	}\r
1e57a462	437	\r
8a8641b5 RC	438	*SegmentNumber = Private->Segment;\r
	439	*BusNumber = 0xff;\r
	440	*DeviceNumber = 0;\r
	441	*FunctionNumber = 0;\r
1e57a462	442	\r
	443	return EFI_SUCCESS;\r
	444	}\r
	445	\r
8a8641b5 RC	446	/**\r
	447	Performs an operation on the attributes that this PCI controller supports.\r
	448	\r
	449	The operations include getting the set of supported attributes, retrieving\r
	450	the current attributes, setting the current attributes, enabling attributes,\r
	451	and disabling attributes.\r
	452	\r
	453	@param[in] This A pointer to the EFI_PCI_IO_PROTOCOL instance.\r
	454	@param[in] Operation The operation to perform on the attributes for this\r
	455	PCI controller.\r
	456	@param[in] Attributes The mask of attributes that are used for Set,\r
	457	Enable and Disable operations.\r
	458	@param[out] Result A pointer to the result mask of attributes that are\r
	459	returned for the Get and Supported operations. This\r
	460	is an optional parameter that may be NULL for the\r
	461	Set, Enable, and Disable operations.\r
	462	\r
	463	@retval EFI_SUCCESS The operation on the PCI controller's\r
	464	attributes was completed. If the operation\r
	465	was Get or Supported, then the attribute mask\r
	466	is returned in Result.\r
	467	@retval EFI_INVALID_PARAMETER Operation is greater than or equal to\r
	468	EfiPciIoAttributeOperationMaximum.\r
	469	@retval EFI_INVALID_PARAMETER Operation is Get and Result is NULL.\r
	470	@retval EFI_INVALID_PARAMETER Operation is Supported and Result is NULL.\r
	471	\r
	472	**/\r
1e57a462	473	EFI_STATUS\r
	474	PciIoAttributes (\r
	475	IN EFI_PCI_IO_PROTOCOL *This,\r
	476	IN EFI_PCI_IO_PROTOCOL_ATTRIBUTE_OPERATION Operation,\r
	477	IN UINT64 Attributes,\r
	478	OUT UINT64 *Result OPTIONAL\r
	479	)\r
	480	{\r
	481	switch (Operation) {\r
	482	case EfiPciIoAttributeOperationGet:\r
	483	case EfiPciIoAttributeOperationSupported:\r
	484	if (Result == NULL) {\r
	485	return EFI_INVALID_PARAMETER;\r
	486	}\r
8a8641b5	487	//\r
1e57a462	488	// We are not a real PCI device so just say things we kind of do\r
8a8641b5 RC	489	//\r
8a8641b5 RC	490	*Result = EFI_PCI_DEVICE_ENABLE;\r
1e57a462	491	break;\r
	492	\r
	493	case EfiPciIoAttributeOperationSet:\r
	494	case EfiPciIoAttributeOperationEnable:\r
	495	case EfiPciIoAttributeOperationDisable:\r
8a8641b5 RC	496	if (Attributes & (~EFI_PCI_DEVICE_ENABLE)) {\r
	497	return EFI_UNSUPPORTED;\r
	498	}\r
1e57a462	499	// Since we are not a real PCI device no enable/set or disable operations exist.\r
1e57a462	500	return EFI_SUCCESS;\r
3402aac7	501	\r
1e57a462	502	default:\r
1e57a462	503	return EFI_INVALID_PARAMETER;\r
	504	};\r
	505	return EFI_SUCCESS;\r
	506	}\r
	507	\r
	508	EFI_STATUS\r
	509	PciIoGetBarAttributes (\r
	510	IN EFI_PCI_IO_PROTOCOL *This,\r
	511	IN UINT8 BarIndex,\r
	512	OUT UINT64 *Supports, OPTIONAL\r
	513	OUT VOID **Resources OPTIONAL\r
	514	)\r
	515	{\r
	516	ASSERT (FALSE);\r
	517	return EFI_UNSUPPORTED;\r
	518	}\r
	519	\r
	520	EFI_STATUS\r
	521	PciIoSetBarAttributes (\r
	522	IN EFI_PCI_IO_PROTOCOL *This,\r
	523	IN UINT64 Attributes,\r
	524	IN UINT8 BarIndex,\r
	525	IN OUT UINT64 *Offset,\r
	526	IN OUT UINT64 *Length\r
	527	)\r
	528	{\r
	529	ASSERT (FALSE);\r
	530	return EFI_UNSUPPORTED;\r
	531	}\r
	532	\r
3402aac7	533	EFI_PCI_IO_PROTOCOL PciIoTemplate =\r
1e57a462	534	{\r
	535	PciIoPollMem,\r
	536	PciIoPollIo,\r
b0fdce95 OM	537	{ PciIoMemRead, PciIoMemWrite },\r
	538	{ PciIoIoRead, PciIoIoWrite },\r
	539	{ PciIoPciRead, PciIoPciWrite },\r
1e57a462	540	PciIoCopyMem,\r
	541	PciIoMap,\r
	542	PciIoUnmap,\r
	543	PciIoAllocateBuffer,\r
	544	PciIoFreeBuffer,\r
	545	PciIoFlush,\r
	546	PciIoGetLocation,\r
	547	PciIoAttributes,\r
	548	PciIoGetBarAttributes,\r
	549	PciIoSetBarAttributes,\r
	550	0,\r
	551	0\r
	552	};\r
	553	\r
	554	EFI_STATUS\r
	555	EFIAPI\r
	556	PciEmulationEntryPoint (\r
	557	IN EFI_HANDLE ImageHandle,\r
	558	IN EFI_SYSTEM_TABLE *SystemTable\r
	559	)\r
	560	{\r
	561	EFI_STATUS Status;\r
	562	EFI_HANDLE Handle;\r
	563	EFI_PCI_IO_PRIVATE_DATA *Private;\r
	564	UINT8 CapabilityLength;\r
	565	UINT8 PhysicalPorts;\r
	566	UINTN Count;\r
	567	\r
	568	\r
	569	//Configure USB host for OMAP3530.\r
	570	ConfigureUSBHost();\r
	571	\r
	572	// Create a private structure\r
	573	Private = AllocatePool(sizeof(EFI_PCI_IO_PRIVATE_DATA));\r
	574	if (Private == NULL) {\r
	575	Status = EFI_OUT_OF_RESOURCES;\r
	576	return Status;\r
	577	}\r
3402aac7	578	\r
1e57a462	579	Private->Signature = EFI_PCI_IO_PRIVATE_DATA_SIGNATURE; // Fill in signature\r
	580	Private->RootBridge.Signature = PCI_ROOT_BRIDGE_SIGNATURE; // Fake Root Bridge structure needs a signature too\r
	581	Private->RootBridge.MemoryStart = USB_EHCI_HCCAPBASE; // Get the USB capability register base\r
	582	Private->Segment = 0; // Default to segment zero\r
	583	\r
	584	// Find out the capability register length and number of physical ports.\r
	585	CapabilityLength = MmioRead8(Private->RootBridge.MemoryStart);\r
	586	PhysicalPorts = (MmioRead32 (Private->RootBridge.MemoryStart + 0x4)) & 0x0000000F;\r
	587	\r
	588	// Calculate the total size of the USB registers.\r
	589	Private->RootBridge.MemorySize = CapabilityLength + (HOST_CONTROLLER_OPERATION_REG_SIZE + ((4 * PhysicalPorts) - 1));\r
	590	\r
	591	// Enable Port Power bit in Port status and control registers in EHCI register space.\r
	592	// Port Power Control (PPC) bit in the HCSPARAMS register is already set which indicates\r
	593	// host controller implementation includes port power control.\r
	594	for (Count = 0; Count < PhysicalPorts; Count++) {\r
	595	MmioOr32 ((Private->RootBridge.MemoryStart + CapabilityLength + HOST_CONTROLLER_OPERATION_REG_SIZE + 4*Count), 0x00001000);\r
	596	}\r
	597	\r
	598	// Create fake PCI config space.\r
	599	Private->ConfigSpace = AllocateZeroPool(sizeof(PCI_TYPE00));\r
	600	if (Private->ConfigSpace == NULL) {\r
	601	Status = EFI_OUT_OF_RESOURCES;\r
	602	FreePool(Private);\r
	603	return Status;\r
	604	}\r
	605	\r
	606	// Configure PCI config space\r
6e8b37f1 RC	607	Private->ConfigSpace->Hdr.VendorId = 0xFFFF; // Invalid vendor Id as it is not an actual device.\r
6e8b37f1 RC	608	Private->ConfigSpace->Hdr.DeviceId = 0x0000; // Not relevant as the vendor id is not valid.\r
1e57a462	609	Private->ConfigSpace->Hdr.ClassCode[0] = 0x20;\r
	610	Private->ConfigSpace->Hdr.ClassCode[1] = 0x03;\r
	611	Private->ConfigSpace->Hdr.ClassCode[2] = 0x0C;\r
	612	Private->ConfigSpace->Device.Bar[0] = Private->RootBridge.MemoryStart;\r
	613	\r
	614	Handle = NULL;\r
	615	\r
	616	// Unique device path.\r
	617	CopyMem(&Private->DevicePath, &PciIoDevicePathTemplate, sizeof(PciIoDevicePathTemplate));\r
	618	Private->DevicePath.AcpiDevicePath.UID = 0;\r
3402aac7	619	\r
1e57a462	620	// Copy protocol structure\r
	621	CopyMem(&Private->PciIoProtocol, &PciIoTemplate, sizeof(PciIoTemplate));\r
	622	\r
	623	Status = gBS->InstallMultipleProtocolInterfaces(&Handle,\r
	624	&gEfiPciIoProtocolGuid, &Private->PciIoProtocol,\r
	625	&gEfiDevicePathProtocolGuid, &Private->DevicePath,\r
	626	NULL);\r
	627	if (EFI_ERROR(Status)) {\r
	628	DEBUG((EFI_D_ERROR, "PciEmulationEntryPoint InstallMultipleProtocolInterfaces() failed.\n"));\r
	629	}\r
	630	\r
	631	return Status;\r
	632	}\r
	633	\r