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1/** @file\r
2\r
3 AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being list\r
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4 in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when SEV\r
5 is enabled.\r
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6\r
7 Copyright (c) 2017, AMD Inc. All rights reserved.<BR>\r
8\r
b26f0cf9 9 SPDX-License-Identifier: BSD-2-Clause-Patent\r
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10\r
11**/\r
12\r
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13#include <Library/BaseLib.h>\r
14#include <Library/BaseMemoryLib.h>\r
c6073a0e 15#include <Library/DebugLib.h>\r
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16#include <Library/DxeServicesTableLib.h>\r
17#include <Library/MemEncryptSevLib.h>\r
c6073a0e 18#include <Library/MemoryAllocationLib.h>\r
5e2e5647 19#include <Library/PcdLib.h>\r
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20\r
21EFI_STATUS\r
22EFIAPI\r
23AmdSevDxeEntryPoint (\r
24 IN EFI_HANDLE ImageHandle,\r
25 IN EFI_SYSTEM_TABLE *SystemTable\r
26 )\r
27{\r
28 EFI_STATUS Status;\r
29 EFI_GCD_MEMORY_SPACE_DESCRIPTOR *AllDescMap;\r
30 UINTN NumEntries;\r
31 UINTN Index;\r
32\r
33 //\r
34 // Do nothing when SEV is not enabled\r
35 //\r
36 if (!MemEncryptSevIsEnabled ()) {\r
37 return EFI_UNSUPPORTED;\r
38 }\r
39\r
40 //\r
41 // Iterate through the GCD map and clear the C-bit from MMIO and NonExistent\r
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42 // memory space. The NonExistent memory space will be used for mapping the\r
43 // MMIO space added later (eg PciRootBridge). By clearing both known MMIO and\r
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44 // NonExistent memory space can gurantee that current and furture MMIO adds\r
45 // will have C-bit cleared.\r
46 //\r
47 Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);\r
48 if (!EFI_ERROR (Status)) {\r
49 for (Index = 0; Index < NumEntries; Index++) {\r
50 CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR *Desc;\r
51\r
52 Desc = &AllDescMap[Index];\r
53 if (Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo ||\r
54 Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent) {\r
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55 Status = MemEncryptSevClearPageEncMask (\r
56 0,\r
57 Desc->BaseAddress,\r
58 EFI_SIZE_TO_PAGES (Desc->Length),\r
59 FALSE\r
60 );\r
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61 ASSERT_EFI_ERROR (Status);\r
62 }\r
63 }\r
64\r
65 FreePool (AllDescMap);\r
66 }\r
67\r
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68 //\r
69 // When SMM is enabled, clear the C-bit from SMM Saved State Area\r
70 //\r
71 // NOTES: The SavedStateArea address cleared here is before SMBASE\r
72 // relocation. Currently, we do not clear the SavedStateArea address after\r
73 // SMBASE is relocated due to the following reasons:\r
74 //\r
75 // 1) Guest BIOS never access the relocated SavedStateArea.\r
76 //\r
77 // 2) The C-bit works on page-aligned address, but the SavedStateArea\r
78 // address is not a page-aligned. Theoretically, we could roundup the address\r
79 // and clear the C-bit of aligned address but looking carefully we found\r
80 // that some portion of the page contains code -- which will causes a bigger\r
81 // issues for SEV guest. When SEV is enabled, all the code must be encrypted\r
82 // otherwise hardware will cause trap.\r
83 //\r
84 // We restore the C-bit for this SMM Saved State Area after SMBASE relocation\r
85 // is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c).\r
86 //\r
87 if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
88 UINTN MapPagesBase;\r
89 UINTN MapPagesCount;\r
90\r
91 Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r
92 &MapPagesBase,\r
93 &MapPagesCount\r
94 );\r
95 ASSERT_EFI_ERROR (Status);\r
96\r
97 //\r
98 // Although these pages were set aside (i.e., allocated) by PlatformPei, we\r
99 // could be after a warm reboot from the OS. Don't leak any stale OS data\r
100 // to the hypervisor.\r
101 //\r
102 ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r
103\r
104 Status = MemEncryptSevClearPageEncMask (\r
105 0, // Cr3BaseAddress -- use current CR3\r
106 MapPagesBase, // BaseAddress\r
107 MapPagesCount, // NumPages\r
108 TRUE // Flush\r
109 );\r
110 if (EFI_ERROR (Status)) {\r
111 DEBUG ((DEBUG_ERROR, "%a: MemEncryptSevClearPageEncMask(): %r\n",\r
112 __FUNCTION__, Status));\r
113 ASSERT (FALSE);\r
114 CpuDeadLoop ();\r
115 }\r
116 }\r
117\r
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118 return EFI_SUCCESS;\r
119}\r