OvmfPkg/VirtNorFlashDxe: map flash memory as uncacheable

[mirror_edk2.git] / OvmfPkg / AmdSevDxe / AmdSevDxe.c

/** @file\r
\r
  AMD Sev Dxe driver. This driver is dispatched early in DXE, due to being list\r
  in APRIORI. It clears C-bit from MMIO and NonExistent Memory space when SEV\r
  is enabled.\r
\r
  Copyright (c) 2017 - 2020, AMD Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/DxeServicesTableLib.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
#include <Guid/ConfidentialComputingSevSnpBlob.h>\r
#include <Library/PcdLib.h>\r
\r
STATIC CONFIDENTIAL_COMPUTING_SNP_BLOB_LOCATION  mSnpBootDxeTable = {\r
  SIGNATURE_32 ('A',                                    'M', 'D', 'E'),\r
  1,\r
  0,\r
  (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfSnpSecretsBase),\r
  FixedPcdGet32 (PcdOvmfSnpSecretsSize),\r
  (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfCpuidBase),\r
  FixedPcdGet32 (PcdOvmfCpuidSize),\r
};\r
\r
EFI_STATUS\r
EFIAPI\r
AmdSevDxeEntryPoint (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS                       Status;\r
  EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *AllDescMap;\r
  UINTN                            NumEntries;\r
  UINTN                            Index;\r
\r
  //\r
  // Do nothing when SEV is not enabled\r
  //\r
  if (!MemEncryptSevIsEnabled ()) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Iterate through the GCD map and clear the C-bit from MMIO and NonExistent\r
  // memory space. The NonExistent memory space will be used for mapping the\r
  // MMIO space added later (eg PciRootBridge). By clearing both known MMIO and\r
  // NonExistent memory space can gurantee that current and furture MMIO adds\r
  // will have C-bit cleared.\r
  //\r
  Status = gDS->GetMemorySpaceMap (&NumEntries, &AllDescMap);\r
  if (!EFI_ERROR (Status)) {\r
    for (Index = 0; Index < NumEntries; Index++) {\r
      CONST EFI_GCD_MEMORY_SPACE_DESCRIPTOR  *Desc;\r
\r
      Desc = &AllDescMap[Index];\r
      if ((Desc->GcdMemoryType == EfiGcdMemoryTypeMemoryMappedIo) ||\r
          (Desc->GcdMemoryType == EfiGcdMemoryTypeNonExistent))\r
      {\r
        Status = MemEncryptSevClearMmioPageEncMask (\r
                   0,\r
                   Desc->BaseAddress,\r
                   EFI_SIZE_TO_PAGES (Desc->Length)\r
                   );\r
        ASSERT_EFI_ERROR (Status);\r
      }\r
    }\r
\r
    FreePool (AllDescMap);\r
  }\r
\r
  //\r
  // If PCI Express is enabled, the MMCONFIG area has been reserved, rather\r
  // than marked as MMIO, and so the C-bit won't be cleared by the above walk\r
  // through the GCD map. Check for the MMCONFIG area and clear the C-bit for\r
  // the range.\r
  //\r
  if (PcdGet16 (PcdOvmfHostBridgePciDevId) == INTEL_Q35_MCH_DEVICE_ID) {\r
    Status = MemEncryptSevClearMmioPageEncMask (\r
               0,\r
               FixedPcdGet64 (PcdPciExpressBaseAddress),\r
               EFI_SIZE_TO_PAGES (SIZE_256MB)\r
               );\r
\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
\r
  //\r
  // When SMM is enabled, clear the C-bit from SMM Saved State Area\r
  //\r
  // NOTES: The SavedStateArea address cleared here is before SMBASE\r
  // relocation. Currently, we do not clear the SavedStateArea address after\r
  // SMBASE is relocated due to the following reasons:\r
  //\r
  // 1) Guest BIOS never access the relocated SavedStateArea.\r
  //\r
  // 2) The C-bit works on page-aligned address, but the SavedStateArea\r
  // address is not a page-aligned. Theoretically, we could roundup the address\r
  // and clear the C-bit of aligned address but looking carefully we found\r
  // that some portion of the page contains code -- which will causes a bigger\r
  // issues for SEV guest. When SEV is enabled, all the code must be encrypted\r
  // otherwise hardware will cause trap.\r
  //\r
  // We restore the C-bit for this SMM Saved State Area after SMBASE relocation\r
  // is completed (See OvmfPkg/Library/SmmCpuFeaturesLib/SmmCpuFeaturesLib.c).\r
  //\r
  if (FeaturePcdGet (PcdSmmSmramRequire)) {\r
    UINTN  MapPagesBase;\r
    UINTN  MapPagesCount;\r
\r
    Status = MemEncryptSevLocateInitialSmramSaveStateMapPages (\r
               &MapPagesBase,\r
               &MapPagesCount\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Although these pages were set aside (i.e., allocated) by PlatformPei, we\r
    // could be after a warm reboot from the OS. Don't leak any stale OS data\r
    // to the hypervisor.\r
    //\r
    ZeroMem ((VOID *)MapPagesBase, EFI_PAGES_TO_SIZE (MapPagesCount));\r
\r
    Status = MemEncryptSevClearPageEncMask (\r
               0,             // Cr3BaseAddress -- use current CR3\r
               MapPagesBase,  // BaseAddress\r
               MapPagesCount  // NumPages\r
               );\r
    if (EFI_ERROR (Status)) {\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: MemEncryptSevClearPageEncMask(): %r\n",\r
        __FUNCTION__,\r
        Status\r
        ));\r
      ASSERT (FALSE);\r
      CpuDeadLoop ();\r
    }\r
  }\r
\r
  //\r
  // If its SEV-SNP active guest then install the CONFIDENTIAL_COMPUTING_SEV_SNP_BLOB.\r
  // It contains the location for both the Secrets and CPUID page.\r
  //\r
  if (MemEncryptSevSnpIsEnabled ()) {\r
    return gBS->InstallConfigurationTable (\r
                  &gConfidentialComputingSevSnpBlobGuid,\r
                  &mSnpBootDxeTable\r
                  );\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r