projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 656419f9 RC |
1 | /*\r |
| 2 | * Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r | |
| 3 | * Copyright (c) 2014, Pluribus Networks, Inc.\r | |
| 4 | *\r | |
| 5 | * SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 6 | */\r | |
| 7 | \r | |
| 8 | #include "Platform.h"\r | |
| 9 | \r | |
| 10 | #define EFI_ACPI_OEM_TABLE_ID SIGNATURE_64('B','V','F','A','C','P',' ',' ')\r | |
| 11 | \r | |
| 12 | EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE FACP = {\r | |
| 13 | {\r | |
| 14 | EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_SIGNATURE,\r | |
| 15 | sizeof (EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE),\r | |
| 16 | EFI_ACPI_3_0_FIXED_ACPI_DESCRIPTION_TABLE_REVISION,\r | |
| 17 | 0, // to make sum of entire table == 0\r | |
| 18 | {EFI_ACPI_OEM_ID}, // OEMID is a 6 bytes long field\r | |
| 19 | EFI_ACPI_OEM_TABLE_ID, // OEM table identification(8 bytes long)\r | |
| 20 | EFI_ACPI_OEM_REVISION, // OEM revision number\r | |
| 21 | EFI_ACPI_CREATOR_ID, // ASL compiler vendor ID\r | |
| 22 | EFI_ACPI_CREATOR_REVISION // ASL compiler revision number\r | |
| 23 | },\r | |
| 24 | 0, // Physical addesss of FACS\r | |
| 25 | 0, // Physical address of DSDT\r | |
| 26 | INT_MODEL, // System Interrupt Model\r | |
| 27 | RESERVED, // reserved\r | |
| 28 | SCI_INT_VECTOR, // System vector of SCI interrupt\r | |
| 29 | SMI_CMD_IO_PORT, // Port address of SMI command port\r | |
| 30 | ACPI_ENABLE, // value to write to port smi_cmd to enable ACPI\r | |
| 31 | ACPI_DISABLE, // value to write to port smi_cmd to disable ACPI\r | |
| 32 | S4BIOS_REQ, // Value to write to SMI CMD port to enter the S4BIOS state\r | |
| 33 | 0, // PState control\r | |
| 34 | PM1a_EVT_BLK, // Port address of Power Mgt 1a Event Reg Blk\r | |
| 35 | PM1b_EVT_BLK, // Port address of Power Mgt 1b Event Reg Blk\r | |
| 36 | PM1a_CNT_BLK, // Port address of Power Mgt 1a Ctrl Reg Blk\r | |
| 37 | PM1b_CNT_BLK, // Port address of Power Mgt 1b Ctrl Reg Blk\r | |
| 38 | PM2_CNT_BLK, // Port address of Power Mgt 2 Ctrl Reg Blk\r | |
| 39 | PM_TMR_BLK, // Port address of Power Mgt Timer Ctrl Reg Blk\r | |
| 40 | GPE0_BLK, // Port addr of General Purpose Event 0 Reg Blk\r | |
| 41 | GPE1_BLK, // Port addr of General Purpose Event 1 Reg Blk\r | |
| 42 | PM1_EVT_LEN, // Byte Length of ports at pm1X_evt_blk\r | |
| 43 | PM1_CNT_LEN, // Byte Length of ports at pm1X_cnt_blk\r | |
| 44 | PM2_CNT_LEN, // Byte Length of ports at pm2_cnt_blk\r | |
| 45 | PM_TM_LEN, // Byte Length of ports at pm_tm_blk\r | |
| 46 | GPE0_BLK_LEN, // Byte Length of ports at gpe0_blk\r | |
| 47 | GPE1_BLK_LEN, // Byte Length of ports at gpe1_blk\r | |
| 48 | GPE1_BASE, // offset in gpe model where gpe1 events start\r | |
| 49 | 0, // _CST support\r | |
| 50 | P_LVL2_LAT, // worst case HW latency to enter/exit C2 state\r | |
| 51 | P_LVL3_LAT, // worst case HW latency to enter/exit C3 state\r | |
| 52 | FLUSH_SIZE, // Size of area read to flush caches\r | |
| 53 | FLUSH_STRIDE, // Stride used in flushing caches\r | |
| 54 | DUTY_OFFSET, // bit location of duty cycle field in p_cnt reg\r | |
| 55 | DUTY_WIDTH, // bit width of duty cycle field in p_cnt reg\r | |
| 56 | DAY_ALRM, // index to day-of-month alarm in RTC CMOS RAM\r | |
| 57 | MON_ALRM, // index to month-of-year alarm in RTC CMOS RAM\r | |
| 58 | CENTURY, // index to century in RTC CMOS RAM\r | |
| 59 | IAPC_BOOT_ARCH, // Boot architecture flag\r | |
| 60 | RESERVED, // reserved\r | |
| 61 | FACP_FLAGS,\r | |
| 62 | FACP_RESET_REG,\r | |
| 63 | FACP_RESET_VAL,\r | |
| 64 | };\r | |
| 65 | \r | |
| 66 | VOID*\r | |
| 67 | ReferenceAcpiTable (\r | |
| 68 | VOID\r | |
| 69 | )\r | |
| 70 | {\r | |
| 71 | //\r | |
| 72 | // Reference the table being generated to prevent the optimizer from removing the\r | |
| 73 | // data structure from the exeutable\r | |
| 74 | //\r | |
| 75 | return (VOID*)&FACP;\r | |
| 76 | }\r |