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1 | /** @file\r |
2 | Platform specific defines for constructing ACPI tables\r | |
3 | \r | |
4 | Copyright (c) 2020, Rebecca Cran <rebecca@bsdio.com>\r | |
5 | Copyright (c) 2014, Pluribus Networks, Inc.\r | |
6 | Copyright (c) 2012, 2013, Red Hat, Inc.\r | |
7 | Copyright (c) 2008, Intel Corporation. All rights reserved.<BR>\r | |
8 | \r | |
9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
10 | \r | |
11 | **/\r | |
12 | \r | |
13 | #ifndef _Platform_h_INCLUDED_\r | |
14 | #define _Platform_h_INCLUDED_\r | |
15 | \r | |
16 | #include <IndustryStandard/Acpi.h>\r | |
656419f9 | 17 | #include <IndustryStandard/MemoryMappedConfigurationSpaceAccessTable.h>\r |
9fb629ed | 18 | #include <IndustryStandard/SerialPortConsoleRedirectionTable.h>\r |
656419f9 RC |
19 | \r |
20 | //\r | |
21 | // ACPI table information used to initialize tables.\r | |
22 | //\r | |
ac0a286f MK |
23 | #define EFI_ACPI_OEM_ID 'B','H','Y','V','E',' ' // OEMID 6 bytes long\r |
24 | #define EFI_ACPI_OEM_REVISION 0x1\r | |
25 | #define EFI_ACPI_CREATOR_ID SIGNATURE_32('B','H','Y','V')\r | |
26 | #define EFI_ACPI_CREATOR_REVISION 0x00000001\r | |
656419f9 | 27 | \r |
ac0a286f MK |
28 | #define INT_MODEL 0x01\r |
29 | #define SCI_INT_VECTOR 0x0009\r | |
30 | #define SMI_CMD_IO_PORT 0xB2\r | |
31 | #define ACPI_ENABLE 0xA0\r | |
32 | #define ACPI_DISABLE 0xA1\r | |
33 | #define S4BIOS_REQ 0x00\r | |
34 | #define PM1a_EVT_BLK 0x00000400 /* TNXXX */\r | |
35 | #define PM1b_EVT_BLK 0x00000000\r | |
36 | #define PM1a_CNT_BLK 0x00000404 /* TNXXX */\r | |
37 | #define PM1b_CNT_BLK 0x00000000\r | |
38 | #define PM2_CNT_BLK 0x00000000\r | |
39 | #define PM_TMR_BLK 0x00000408\r | |
40 | #define GPE0_BLK 0x00000000\r | |
41 | #define GPE1_BLK 0x00000000\r | |
42 | #define PM1_EVT_LEN 0x04\r | |
43 | #define PM1_CNT_LEN 0x02\r | |
44 | #define PM2_CNT_LEN 0x00\r | |
45 | #define PM_TM_LEN 0x04\r | |
46 | #define GPE0_BLK_LEN 0x00\r | |
47 | #define GPE1_BLK_LEN 0x00\r | |
48 | #define GPE1_BASE 0x00\r | |
49 | #define RESERVED 0x00\r | |
50 | #define P_LVL2_LAT 0x0000\r | |
51 | #define P_LVL3_LAT 0x0000\r | |
52 | #define FLUSH_SIZE 0x0000\r | |
53 | #define FLUSH_STRIDE 0x0000\r | |
54 | #define DUTY_OFFSET 0x00\r | |
55 | #define DUTY_WIDTH 0x00\r | |
56 | #define DAY_ALRM 0x00\r | |
57 | #define MON_ALRM 0x00\r | |
58 | #define CENTURY 0x32\r | |
59 | #define IAPC_BOOT_ARCH 0x12 /* 8042 present, disable PCIe ASPM */\r | |
60 | #define FACP_FLAGS (EFI_ACPI_1_0_WBINVD | EFI_ACPI_1_0_PROC_C1 | \\r | |
656419f9 RC |
61 | EFI_ACPI_1_0_SLP_BUTTON | EFI_ACPI_1_0_TMR_VAL_EXT | \\r |
62 | EFI_ACPI_2_0_RESET_REG_SUP | \\r | |
63 | EFI_ACPI_3_0_FORCE_APIC_PHYSICAL_DESTINATION_MODE)\r | |
ac0a286f | 64 | #define FACP_RESET_REG { \\r |
656419f9 RC |
65 | EFI_ACPI_3_0_SYSTEM_IO, /* Address Space ID */ \\r |
66 | 8, /* Bit Width */ \\r | |
67 | 0, /* Bit Offset */ \\r | |
68 | EFI_ACPI_3_0_BYTE, /* Byte Access */ \\r | |
69 | 0xCF9 /* I/O Port */ \\r | |
70 | }\r | |
ac0a286f | 71 | #define FACP_RESET_VAL 0x6\r |
656419f9 | 72 | #endif\r |