projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 79f802a5 GL |
1 | /** @file\r |
| 2 | \r | |
| 3 | Macros and type definitions for LSI 53C895A SCSI devices.\r | |
| 4 | \r | |
| 5 | Copyright (C) 2020, SUSE LLC.\r | |
| 6 | \r | |
| 7 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
| 8 | \r | |
| 9 | **/\r | |
| 10 | \r | |
| 11 | #ifndef _LSI_SCSI_H_\r | |
| 12 | #define _LSI_SCSI_H_\r | |
| 13 | \r | |
| 14 | //\r | |
| 15 | // Device ID\r | |
| 16 | //\r | |
| ac0a286f MK |
17 | #define LSI_LOGIC_PCI_VENDOR_ID 0x1000\r |
| 18 | #define LSI_53C895A_PCI_DEVICE_ID 0x0012\r | |
| 79f802a5 | 19 | \r |
| 8d619390 GL |
20 | //\r |
| 21 | // LSI 53C895A Registers\r | |
| 22 | //\r | |
| ac0a286f MK |
23 | #define LSI_REG_DSTAT 0x0C\r |
| 24 | #define LSI_REG_ISTAT0 0x14\r | |
| 25 | #define LSI_REG_DSP 0x2C\r | |
| 26 | #define LSI_REG_SIST0 0x42\r | |
| 27 | #define LSI_REG_SIST1 0x43\r | |
| 28 | #define LSI_REG_CSBC 0xDC\r | |
| 31830b07 GL |
29 | \r |
| 30 | //\r | |
| 31 | // The status bits for DMA Status (DSTAT)\r | |
| 32 | //\r | |
| ac0a286f MK |
33 | #define LSI_DSTAT_IID BIT0\r |
| 34 | #define LSI_DSTAT_R BIT1\r | |
| 35 | #define LSI_DSTAT_SIR BIT2\r | |
| 36 | #define LSI_DSTAT_SSI BIT3\r | |
| 37 | #define LSI_DSTAT_ABRT BIT4\r | |
| 38 | #define LSI_DSTAT_BF BIT5\r | |
| 39 | #define LSI_DSTAT_MDPE BIT6\r | |
| 40 | #define LSI_DSTAT_DFE BIT7\r | |
| 8d619390 GL |
41 | \r |
| 42 | //\r | |
| 43 | // The status bits for Interrupt Status Zero (ISTAT0)\r | |
| 44 | //\r | |
| ac0a286f MK |
45 | #define LSI_ISTAT0_DIP BIT0\r |
| 46 | #define LSI_ISTAT0_SIP BIT1\r | |
| 47 | #define LSI_ISTAT0_INTF BIT2\r | |
| 48 | #define LSI_ISTAT0_CON BIT3\r | |
| 49 | #define LSI_ISTAT0_SEM BIT4\r | |
| 50 | #define LSI_ISTAT0_SIGP BIT5\r | |
| 51 | #define LSI_ISTAT0_SRST BIT6\r | |
| 52 | #define LSI_ISTAT0_ABRT BIT7\r | |
| 8d619390 | 53 | \r |
| 31830b07 GL |
54 | //\r |
| 55 | // The status bits for SCSI Interrupt Status Zero (SIST0)\r | |
| 56 | //\r | |
| ac0a286f MK |
57 | #define LSI_SIST0_PAR BIT0\r |
| 58 | #define LSI_SIST0_RST BIT1\r | |
| 59 | #define LSI_SIST0_UDC BIT2\r | |
| 60 | #define LSI_SIST0_SGE BIT3\r | |
| 61 | #define LSI_SIST0_RSL BIT4\r | |
| 62 | #define LSI_SIST0_SEL BIT5\r | |
| 63 | #define LSI_SIST0_CMP BIT6\r | |
| 64 | #define LSI_SIST0_MA BIT7\r | |
| 31830b07 GL |
65 | \r |
| 66 | //\r | |
| 67 | // The status bits for SCSI Interrupt Status One (SIST1)\r | |
| 68 | //\r | |
| ac0a286f MK |
69 | #define LSI_SIST1_HTH BIT0\r |
| 70 | #define LSI_SIST1_GEN BIT1\r | |
| 71 | #define LSI_SIST1_STO BIT2\r | |
| 72 | #define LSI_SIST1_R3 BIT3\r | |
| 73 | #define LSI_SIST1_SBMC BIT4\r | |
| 74 | #define LSI_SIST1_R5 BIT5\r | |
| 75 | #define LSI_SIST1_R6 BIT6\r | |
| 76 | #define LSI_SIST1_R7 BIT7\r | |
| 31830b07 GL |
77 | \r |
| 78 | //\r | |
| 79 | // LSI 53C895A Script Instructions\r | |
| 80 | //\r | |
| ac0a286f MK |
81 | #define LSI_INS_TYPE_BLK 0x00000000\r |
| 82 | #define LSI_INS_TYPE_IO BIT30\r | |
| 83 | #define LSI_INS_TYPE_TC BIT31\r | |
| 84 | \r | |
| 85 | #define LSI_INS_BLK_SCSIP_DAT_OUT 0x00000000\r | |
| 86 | #define LSI_INS_BLK_SCSIP_DAT_IN BIT24\r | |
| 87 | #define LSI_INS_BLK_SCSIP_CMD BIT25\r | |
| 88 | #define LSI_INS_BLK_SCSIP_STAT (BIT24 | BIT25)\r | |
| 89 | #define LSI_INS_BLK_SCSIP_MSG_OUT (BIT25 | BIT26)\r | |
| 90 | #define LSI_INS_BLK_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)\r | |
| 91 | \r | |
| 92 | #define LSI_INS_IO_OPC_SEL 0x00000000\r | |
| 93 | #define LSI_INS_IO_OPC_WAIT_RESEL BIT28\r | |
| 94 | \r | |
| 95 | #define LSI_INS_TC_CP BIT17\r | |
| 96 | #define LSI_INS_TC_JMP BIT19\r | |
| 97 | #define LSI_INS_TC_RA BIT23\r | |
| 98 | \r | |
| 99 | #define LSI_INS_TC_OPC_JMP 0x00000000\r | |
| 100 | #define LSI_INS_TC_OPC_INT (BIT27 | BIT28)\r | |
| 31830b07 GL |
101 | \r |
| 102 | #define LSI_INS_TC_SCSIP_DAT_OUT 0x00000000\r | |
| 103 | #define LSI_INS_TC_SCSIP_MSG_IN (BIT24 | BIT25 | BIT26)\r | |
| 104 | \r | |
| 79f802a5 | 105 | #endif // _LSI_SCSI_H_\r |