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1 | /** @file\r |
2 | Macro and type definitions corresponding to the QEMU fw_cfg interface.\r | |
3 | \r | |
4 | Refer to "docs/specs/fw_cfg.txt" in the QEMU source directory.\r | |
5 | \r | |
6 | Copyright (c) 2011 - 2013, Intel Corporation. All rights reserved.<BR>\r | |
7 | Copyright (C) 2013 - 2017, Red Hat, Inc.\r | |
8 | \r | |
b26f0cf9 | 9 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
5583a8a4 LE |
10 | **/\r |
11 | \r | |
12 | #ifndef __FW_CFG_H__\r | |
13 | #define __FW_CFG_H__\r | |
14 | \r | |
15 | #include <Base.h>\r | |
16 | \r | |
17 | //\r | |
18 | // The size, in bytes, of names of firmware configuration files, including at\r | |
19 | // least one terminating NUL byte.\r | |
20 | //\r | |
21 | #define QEMU_FW_CFG_FNAME_SIZE 56\r | |
22 | \r | |
23 | //\r | |
24 | // If the following bit is set in the UINT32 fw_cfg revision / feature bitmap\r | |
25 | // -- read from key 0x0001 with the basic IO Port or MMIO method --, then the\r | |
26 | // DMA interface is available.\r | |
27 | //\r | |
28 | #define FW_CFG_F_DMA BIT1\r | |
29 | \r | |
30 | //\r | |
31 | // Macros for the FW_CFG_DMA_ACCESS.Control bitmap (in native encoding).\r | |
32 | //\r | |
33 | #define FW_CFG_DMA_CTL_ERROR BIT0\r | |
34 | #define FW_CFG_DMA_CTL_READ BIT1\r | |
35 | #define FW_CFG_DMA_CTL_SKIP BIT2\r | |
36 | #define FW_CFG_DMA_CTL_SELECT BIT3\r | |
37 | #define FW_CFG_DMA_CTL_WRITE BIT4\r | |
38 | \r | |
21ca2f28 LE |
39 | //\r |
40 | // The fw_cfg registers can be found at these IO Ports, on the IO-mapped\r | |
41 | // platforms (Ia32 and X64).\r | |
42 | //\r | |
43 | #define FW_CFG_IO_SELECTOR 0x510\r | |
509e6b5a | 44 | #define FW_CFG_IO_DATA 0x511\r |
ed1a2d42 | 45 | #define FW_CFG_IO_DMA_ADDRESS 0x514\r |
21ca2f28 | 46 | \r |
5583a8a4 LE |
47 | //\r |
48 | // Numerically defined keys.\r | |
49 | //\r | |
50 | typedef enum {\r | |
51 | QemuFwCfgItemSignature = 0x0000,\r | |
52 | QemuFwCfgItemInterfaceVersion = 0x0001,\r | |
53 | QemuFwCfgItemSystemUuid = 0x0002,\r | |
54 | QemuFwCfgItemRamSize = 0x0003,\r | |
55 | QemuFwCfgItemGraphicsEnabled = 0x0004,\r | |
56 | QemuFwCfgItemSmpCpuCount = 0x0005,\r | |
57 | QemuFwCfgItemMachineId = 0x0006,\r | |
58 | QemuFwCfgItemKernelAddress = 0x0007,\r | |
59 | QemuFwCfgItemKernelSize = 0x0008,\r | |
60 | QemuFwCfgItemKernelCommandLine = 0x0009,\r | |
61 | QemuFwCfgItemInitrdAddress = 0x000a,\r | |
62 | QemuFwCfgItemInitrdSize = 0x000b,\r | |
63 | QemuFwCfgItemBootDevice = 0x000c,\r | |
64 | QemuFwCfgItemNumaData = 0x000d,\r | |
65 | QemuFwCfgItemBootMenu = 0x000e,\r | |
66 | QemuFwCfgItemMaximumCpuCount = 0x000f,\r | |
67 | QemuFwCfgItemKernelEntry = 0x0010,\r | |
68 | QemuFwCfgItemKernelData = 0x0011,\r | |
69 | QemuFwCfgItemInitrdData = 0x0012,\r | |
70 | QemuFwCfgItemCommandLineAddress = 0x0013,\r | |
71 | QemuFwCfgItemCommandLineSize = 0x0014,\r | |
72 | QemuFwCfgItemCommandLineData = 0x0015,\r | |
73 | QemuFwCfgItemKernelSetupAddress = 0x0016,\r | |
74 | QemuFwCfgItemKernelSetupSize = 0x0017,\r | |
75 | QemuFwCfgItemKernelSetupData = 0x0018,\r | |
76 | QemuFwCfgItemFileDir = 0x0019,\r | |
77 | \r | |
78 | QemuFwCfgItemX86AcpiTables = 0x8000,\r | |
79 | QemuFwCfgItemX86SmbiosTables = 0x8001,\r | |
80 | QemuFwCfgItemX86Irq0Override = 0x8002,\r | |
81 | QemuFwCfgItemX86E820Table = 0x8003,\r | |
82 | QemuFwCfgItemX86HpetData = 0x8004,\r | |
83 | \r | |
84 | } FIRMWARE_CONFIG_ITEM;\r | |
85 | \r | |
86 | //\r | |
87 | // Communication structure for the DMA access method. All fields are encoded in\r | |
88 | // big endian.\r | |
89 | //\r | |
90 | #pragma pack (1)\r | |
91 | typedef struct {\r | |
92 | UINT32 Control;\r | |
93 | UINT32 Length;\r | |
94 | UINT64 Address;\r | |
95 | } FW_CFG_DMA_ACCESS;\r | |
96 | #pragma pack ()\r | |
97 | \r | |
98 | #endif\r |