OvmfPkg/IndustryStandard/Xen: replace MIT license text with SPDX ID

[mirror_edk2.git] / OvmfPkg / Include / IndustryStandard / Xen / arch-arm / xen.h

/******************************************************************************\r
 * arch-arm.h\r
 *\r
 * Guest OS interface to ARM Xen.\r
 *\r
 * SPDX-License-Identifier: MIT\r
 *\r
 * Copyright 2011 (C) Citrix Systems\r
 */\r
\r
#ifndef __XEN_PUBLIC_ARCH_ARM_H__\r
#define __XEN_PUBLIC_ARCH_ARM_H__\r
\r
/*\r
 * `incontents 50 arm_abi Hypercall Calling Convention\r
 *\r
 * A hypercall is issued using the ARM HVC instruction.\r
 *\r
 * A hypercall can take up to 5 arguments. These are passed in\r
 * registers, the first argument in x0/r0 (for arm64/arm32 guests\r
 * respectively irrespective of whether the underlying hypervisor is\r
 * 32- or 64-bit), the second argument in x1/r1, the third in x2/r2,\r
 * the forth in x3/r3 and the fifth in x4/r4.\r
 *\r
 * The hypercall number is passed in r12 (arm) or x16 (arm64). In both\r
 * cases the relevant ARM procedure calling convention specifies this\r
 * is an inter-procedure-call scratch register (e.g. for use in linker\r
 * stubs). This use does not conflict with use during a hypercall.\r
 *\r
 * The HVC ISS must contain a Xen specific TAG: XEN_HYPERCALL_TAG.\r
 *\r
 * The return value is in x0/r0.\r
 *\r
 * The hypercall will clobber x16/r12 and the argument registers used\r
 * by that hypercall (except r0 which is the return value) i.e. in\r
 * addition to x16/r12 a 2 argument hypercall will clobber x1/r1 and a\r
 * 4 argument hypercall will clobber x1/r1, x2/r2 and x3/r3.\r
 *\r
 * Parameter structs passed to hypercalls are laid out according to\r
 * the Procedure Call Standard for the ARM Architecture (AAPCS, AKA\r
 * EABI) and Procedure Call Standard for the ARM 64-bit Architecture\r
 * (AAPCS64). Where there is a conflict the 64-bit standard should be\r
 * used regardless of guest type. Structures which are passed as\r
 * hypercall arguments are always little endian.\r
 *\r
 * All memory which is shared with other entities in the system\r
 * (including the hypervisor and other guests) must reside in memory\r
 * which is mapped as Normal Inner-cacheable. This applies to:\r
 *  - hypercall arguments passed via a pointer to guest memory.\r
 *  - memory shared via the grant table mechanism (including PV I/O\r
 *    rings etc).\r
 *  - memory shared with the hypervisor (struct shared_info, struct\r
 *    vcpu_info, the grant table, etc).\r
 *\r
 * Any Inner cache allocation strategy (Write-Back, Write-Through etc)\r
 * is acceptable. There is no restriction on the Outer-cacheability.\r
 */\r
\r
/*\r
 * `incontents 55 arm_hcall Supported Hypercalls\r
 *\r
 * Xen on ARM makes extensive use of hardware facilities and therefore\r
 * only a subset of the potential hypercalls are required.\r
 *\r
 * Since ARM uses second stage paging any machine/physical addresses\r
 * passed to hypercalls are Guest Physical Addresses (Intermediate\r
 * Physical Addresses) unless otherwise noted.\r
 *\r
 * The following hypercalls (and sub operations) are supported on the\r
 * ARM platform. Other hypercalls should be considered\r
 * unavailable/unsupported.\r
 *\r
 *  HYPERVISOR_memory_op\r
 *   All generic sub-operations.\r
 *\r
 *   In addition the following arch specific sub-ops:\r
 *    * XENMEM_add_to_physmap\r
 *    * XENMEM_add_to_physmap_batch\r
 *\r
 *  HYPERVISOR_domctl\r
 *   All generic sub-operations, with the exception of:\r
 *    * XEN_DOMCTL_iomem_permission (not yet implemented)\r
 *    * XEN_DOMCTL_irq_permission (not yet implemented)\r
 *\r
 *  HYPERVISOR_sched_op\r
 *   All generic sub-operations, with the exception of:\r
 *    * SCHEDOP_block -- prefer wfi hardware instruction\r
 *\r
 *  HYPERVISOR_console_io\r
 *   All generic sub-operations\r
 *\r
 *  HYPERVISOR_xen_version\r
 *   All generic sub-operations\r
 *\r
 *  HYPERVISOR_event_channel_op\r
 *   All generic sub-operations\r
 *\r
 *  HYPERVISOR_physdev_op\r
 *   No sub-operations are currenty supported\r
 *\r
 *  HYPERVISOR_sysctl\r
 *   All generic sub-operations, with the exception of:\r
 *    * XEN_SYSCTL_page_offline_op\r
 *    * XEN_SYSCTL_get_pmstat\r
 *    * XEN_SYSCTL_pm_op\r
 *\r
 *  HYPERVISOR_hvm_op\r
 *   Exactly these sub-operations are supported:\r
 *    * HVMOP_set_param\r
 *    * HVMOP_get_param\r
 *\r
 *  HYPERVISOR_grant_table_op\r
 *   All generic sub-operations\r
 *\r
 *  HYPERVISOR_vcpu_op\r
 *   Exactly these sub-operations are supported:\r
 *    * VCPUOP_register_vcpu_info\r
 *    * VCPUOP_register_runstate_memory_area\r
 *\r
 *\r
 * Other notes on the ARM ABI:\r
 *\r
 * - struct start_info is not exported to ARM guests.\r
 *\r
 * - struct shared_info is mapped by ARM guests using the\r
 *   HYPERVISOR_memory_op sub-op XENMEM_add_to_physmap, passing\r
 *   XENMAPSPACE_shared_info as space parameter.\r
 *\r
 * - All the per-cpu struct vcpu_info are mapped by ARM guests using the\r
 *   HYPERVISOR_vcpu_op sub-op VCPUOP_register_vcpu_info, including cpu0\r
 *   struct vcpu_info.\r
 *\r
 * - The grant table is mapped using the HYPERVISOR_memory_op sub-op\r
 *   XENMEM_add_to_physmap, passing XENMAPSPACE_grant_table as space\r
 *   parameter. The memory range specified under the Xen compatible\r
 *   hypervisor node on device tree can be used as target gpfn for the\r
 *   mapping.\r
 *\r
 * - Xenstore is initialized by using the two hvm_params\r
 *   HVM_PARAM_STORE_PFN and HVM_PARAM_STORE_EVTCHN. They can be read\r
 *   with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.\r
 *\r
 * - The paravirtualized console is initialized by using the two\r
 *   hvm_params HVM_PARAM_CONSOLE_PFN and HVM_PARAM_CONSOLE_EVTCHN. They\r
 *   can be read with the HYPERVISOR_hvm_op sub-op HVMOP_get_param.\r
 *\r
 * - Event channel notifications are delivered using the percpu GIC\r
 *   interrupt specified under the Xen compatible hypervisor node on\r
 *   device tree.\r
 *\r
 * - The device tree Xen compatible node is fully described under Linux\r
 *   at Documentation/devicetree/bindings/arm/xen.txt.\r
 */\r
\r
#define XEN_HYPERCALL_TAG   0xEA1\r
\r
#define uint64_aligned_t UINT64 __attribute__((aligned(8)))\r
\r
#ifndef __ASSEMBLY__\r
#define ___DEFINE_XEN_GUEST_HANDLE(name, type)                  \\r
    typedef union { type *p; unsigned long q; }                 \\r
        __guest_handle_ ## name;                                \\r
    typedef union { type *p; uint64_aligned_t q; }              \\r
        __guest_handle_64_ ## name;\r
\r
/*\r
 * XEN_GUEST_HANDLE represents a guest pointer, when passed as a field\r
 * in a struct in memory. On ARM is always 8 bytes sizes and 8 bytes\r
 * aligned.\r
 * XEN_GUEST_HANDLE_PARAM represent a guest pointer, when passed as an\r
 * hypercall argument. It is 4 bytes on aarch and 8 bytes on aarch64.\r
 */\r
#define __DEFINE_XEN_GUEST_HANDLE(name, type) \\r
    ___DEFINE_XEN_GUEST_HANDLE(name, type);   \\r
    ___DEFINE_XEN_GUEST_HANDLE(const_##name, const type)\r
#define DEFINE_XEN_GUEST_HANDLE(name)   __DEFINE_XEN_GUEST_HANDLE(name, name)\r
#define __XEN_GUEST_HANDLE(name)        __guest_handle_64_ ## name\r
#define XEN_GUEST_HANDLE(name)          __XEN_GUEST_HANDLE(name)\r
/* this is going to be changed on 64 bit */\r
#define XEN_GUEST_HANDLE_PARAM(name)    __guest_handle_ ## name\r
#define set_xen_guest_handle_raw(hnd, val)                  \\r
    do {                                                    \\r
        typeof(&(hnd)) _sxghr_tmp = &(hnd);                 \\r
        _sxghr_tmp->q = 0;                                  \\r
        _sxghr_tmp->p = val;                                \\r
    } while ( 0 )\r
#ifdef __XEN_TOOLS__\r
#define get_xen_guest_handle(val, hnd)  do { val = (hnd).p; } while (0)\r
#endif\r
#define set_xen_guest_handle(hnd, val) set_xen_guest_handle_raw(hnd, val)\r
\r
#if defined(__GNUC__) && !defined(__STRICT_ANSI__)\r
/* Anonymous union includes both 32- and 64-bit names (e.g., r0/x0). */\r
# define __DECL_REG(n64, n32) union {          \\r
        UINT64 n64;                          \\r
        UINT32 n32;                          \\r
    }\r
#else\r
/* Non-gcc sources must always use the proper 64-bit name (e.g., x0). */\r
#define __DECL_REG(n64, n32) UINT64 n64\r
#endif\r
\r
struct vcpu_guest_core_regs\r
{\r
    /*         Aarch64       Aarch32 */\r
    __DECL_REG(x0,           r0_usr);\r
    __DECL_REG(x1,           r1_usr);\r
    __DECL_REG(x2,           r2_usr);\r
    __DECL_REG(x3,           r3_usr);\r
    __DECL_REG(x4,           r4_usr);\r
    __DECL_REG(x5,           r5_usr);\r
    __DECL_REG(x6,           r6_usr);\r
    __DECL_REG(x7,           r7_usr);\r
    __DECL_REG(x8,           r8_usr);\r
    __DECL_REG(x9,           r9_usr);\r
    __DECL_REG(x10,          r10_usr);\r
    __DECL_REG(x11,          r11_usr);\r
    __DECL_REG(x12,          r12_usr);\r
\r
    __DECL_REG(x13,          sp_usr);\r
    __DECL_REG(x14,          lr_usr);\r
\r
    __DECL_REG(x15,          __unused_sp_hyp);\r
\r
    __DECL_REG(x16,          lr_irq);\r
    __DECL_REG(x17,          sp_irq);\r
\r
    __DECL_REG(x18,          lr_svc);\r
    __DECL_REG(x19,          sp_svc);\r
\r
    __DECL_REG(x20,          lr_abt);\r
    __DECL_REG(x21,          sp_abt);\r
\r
    __DECL_REG(x22,          lr_und);\r
    __DECL_REG(x23,          sp_und);\r
\r
    __DECL_REG(x24,          r8_fiq);\r
    __DECL_REG(x25,          r9_fiq);\r
    __DECL_REG(x26,          r10_fiq);\r
    __DECL_REG(x27,          r11_fiq);\r
    __DECL_REG(x28,          r12_fiq);\r
\r
    __DECL_REG(x29,          sp_fiq);\r
    __DECL_REG(x30,          lr_fiq);\r
\r
    /* Return address and mode */\r
    __DECL_REG(pc64,         pc32);             /* ELR_EL2 */\r
    UINT32 cpsr;                              /* SPSR_EL2 */\r
\r
    union {\r
        UINT32 spsr_el1;       /* AArch64 */\r
        UINT32 spsr_svc;       /* AArch32 */\r
    };\r
\r
    /* AArch32 guests only */\r
    UINT32 spsr_fiq, spsr_irq, spsr_und, spsr_abt;\r
\r
    /* AArch64 guests only */\r
    UINT64 sp_el0;\r
    UINT64 sp_el1, elr_el1;\r
};\r
typedef struct vcpu_guest_core_regs vcpu_guest_core_regs_t;\r
DEFINE_XEN_GUEST_HANDLE(vcpu_guest_core_regs_t);\r
\r
#undef __DECL_REG\r
\r
typedef UINT64 xen_pfn_t;\r
#define PRI_xen_pfn PRIx64\r
\r
/* Maximum number of virtual CPUs in legacy multi-processor guests. */\r
/* Only one. All other VCPUS must use VCPUOP_register_vcpu_info */\r
#define XEN_LEGACY_MAX_VCPUS 1\r
\r
typedef UINT64 xen_ulong_t;\r
#define PRI_xen_ulong PRIx64\r
\r
#if defined(__XEN__) || defined(__XEN_TOOLS__)\r
struct vcpu_guest_context {\r
#define _VGCF_online                   0\r
#define VGCF_online                    (1<<_VGCF_online)\r
    UINT32 flags;                         /* VGCF_* */\r
\r
    struct vcpu_guest_core_regs user_regs;  /* Core CPU registers */\r
\r
    UINT32 sctlr;\r
    UINT64 ttbcr, ttbr0, ttbr1;\r
};\r
typedef struct vcpu_guest_context vcpu_guest_context_t;\r
DEFINE_XEN_GUEST_HANDLE(vcpu_guest_context_t);\r
#endif\r
\r
struct arch_vcpu_info {\r
};\r
typedef struct arch_vcpu_info arch_vcpu_info_t;\r
\r
struct arch_shared_info {\r
};\r
typedef struct arch_shared_info arch_shared_info_t;\r
typedef UINT64 xen_callback_t;\r
\r
#endif\r
\r
#if defined(__XEN__) || defined(__XEN_TOOLS__)\r
\r
/* PSR bits (CPSR, SPSR)*/\r
\r
#define PSR_THUMB       (1<<5)        /* Thumb Mode enable */\r
#define PSR_FIQ_MASK    (1<<6)        /* Fast Interrupt mask */\r
#define PSR_IRQ_MASK    (1<<7)        /* Interrupt mask */\r
#define PSR_ABT_MASK    (1<<8)        /* Asynchronous Abort mask */\r
#define PSR_BIG_ENDIAN  (1<<9)        /* arm32: Big Endian Mode */\r
#define PSR_DBG_MASK    (1<<9)        /* arm64: Debug Exception mask */\r
#define PSR_IT_MASK     (0x0600fc00)  /* Thumb If-Then Mask */\r
#define PSR_JAZELLE     (1<<24)       /* Jazelle Mode */\r
\r
/* 32 bit modes */\r
#define PSR_MODE_USR 0x10\r
#define PSR_MODE_FIQ 0x11\r
#define PSR_MODE_IRQ 0x12\r
#define PSR_MODE_SVC 0x13\r
#define PSR_MODE_MON 0x16\r
#define PSR_MODE_ABT 0x17\r
#define PSR_MODE_HYP 0x1a\r
#define PSR_MODE_UND 0x1b\r
#define PSR_MODE_SYS 0x1f\r
\r
/* 64 bit modes */\r
#define PSR_MODE_BIT  0x10 /* Set iff AArch32 */\r
#define PSR_MODE_EL3h 0x0d\r
#define PSR_MODE_EL3t 0x0c\r
#define PSR_MODE_EL2h 0x09\r
#define PSR_MODE_EL2t 0x08\r
#define PSR_MODE_EL1h 0x05\r
#define PSR_MODE_EL1t 0x04\r
#define PSR_MODE_EL0t 0x00\r
\r
#define PSR_GUEST32_INIT  (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_SVC)\r
#define PSR_GUEST64_INIT (PSR_ABT_MASK|PSR_FIQ_MASK|PSR_IRQ_MASK|PSR_MODE_EL1h)\r
\r
#define SCTLR_GUEST_INIT    0x00c50078\r
\r
/*\r
 * Virtual machine platform (memory layout, interrupts)\r
 *\r
 * These are defined for consistency between the tools and the\r
 * hypervisor. Guests must not rely on these hardcoded values but\r
 * should instead use the FDT.\r
 */\r
\r
/* Physical Address Space */\r
\r
/* vGIC mappings: Only one set of mapping is used by the guest.\r
 * Therefore they can overlap.\r
 */\r
\r
/* vGIC v2 mappings */\r
#define GUEST_GICD_BASE   0x03001000ULL\r
#define GUEST_GICD_SIZE   0x00001000ULL\r
#define GUEST_GICC_BASE   0x03002000ULL\r
#define GUEST_GICC_SIZE   0x00000100ULL\r
\r
/* vGIC v3 mappings */\r
#define GUEST_GICV3_GICD_BASE      0x03001000ULL\r
#define GUEST_GICV3_GICD_SIZE      0x00010000ULL\r
\r
#define GUEST_GICV3_RDIST_STRIDE   0x20000ULL\r
#define GUEST_GICV3_RDIST_REGIONS  1\r
\r
#define GUEST_GICV3_GICR0_BASE     0x03020000ULL    /* vCPU0 - vCPU7 */\r
#define GUEST_GICV3_GICR0_SIZE     0x00100000ULL\r
\r
/* 16MB == 4096 pages reserved for guest to use as a region to map its\r
 * grant table in.\r
 */\r
#define GUEST_GNTTAB_BASE 0x38000000ULL\r
#define GUEST_GNTTAB_SIZE 0x01000000ULL\r
\r
#define GUEST_MAGIC_BASE  0x39000000ULL\r
#define GUEST_MAGIC_SIZE  0x01000000ULL\r
\r
#define GUEST_RAM_BANKS   2\r
\r
#define GUEST_RAM0_BASE   0x40000000ULL /* 3GB of low RAM @ 1GB */\r
#define GUEST_RAM0_SIZE   0xc0000000ULL\r
\r
#define GUEST_RAM1_BASE   0x0200000000ULL /* 1016GB of RAM @ 8GB */\r
#define GUEST_RAM1_SIZE   0xfe00000000ULL\r
\r
#define GUEST_RAM_BASE    GUEST_RAM0_BASE /* Lowest RAM address */\r
/* Largest amount of actual RAM, not including holes */\r
#define GUEST_RAM_MAX     (GUEST_RAM0_SIZE + GUEST_RAM1_SIZE)\r
/* Suitable for e.g. const uint64_t ramfoo[] = GUEST_RAM_BANK_FOOS; */\r
#define GUEST_RAM_BANK_BASES   { GUEST_RAM0_BASE, GUEST_RAM1_BASE }\r
#define GUEST_RAM_BANK_SIZES   { GUEST_RAM0_SIZE, GUEST_RAM1_SIZE }\r
\r
/* Interrupts */\r
#define GUEST_TIMER_VIRT_PPI    27\r
#define GUEST_TIMER_PHYS_S_PPI  29\r
#define GUEST_TIMER_PHYS_NS_PPI 30\r
#define GUEST_EVTCHN_PPI        31\r
\r
/* PSCI functions */\r
#define PSCI_cpu_suspend 0\r
#define PSCI_cpu_off     1\r
#define PSCI_cpu_on      2\r
#define PSCI_migrate     3\r
\r
#endif\r
\r
#endif /*  __XEN_PUBLIC_ARCH_ARM_H__ */\r
\r
/*\r
 * Local variables:\r
 * mode: C\r
 * c-file-style: "BSD"\r
 * c-basic-offset: 4\r
 * tab-width: 4\r
 * indent-tabs-mode: nil\r
 * End:\r
 */\r