[mirror_edk2.git] / OvmfPkg / Include / Library / PciCapLib.h

/** @file\r
  Library class to work with PCI capabilities in PCI config space.\r
\r
  Provides functions to parse capabilities lists, and to locate, describe, read\r
  and write capabilities. PCI config space access is abstracted away.\r
\r
  Copyright (C) 2018, Red Hat, Inc.\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#ifndef __PCI_CAP_LIB_H__\r
#define __PCI_CAP_LIB_H__\r
\r
#include <Uefi/UefiBaseType.h>\r
\r
//\r
// Base structure for representing a PCI device -- down to the PCI function\r
// level -- for the purposes of this library class. This is a forward\r
// declaration that is completed below. Concrete implementations are supposed\r
// to inherit and extend this type.\r
//\r
typedef struct PCI_CAP_DEV PCI_CAP_DEV;\r
\r
/**\r
  Read the config space of a given PCI device (both normal and extended).\r
\r
  PCI_CAP_DEV_READ_CONFIG performs as few config space accesses as possible\r
  (without attempting 64-bit wide accesses).\r
\r
  PCI_CAP_DEV_READ_CONFIG returns an unspecified error if accessing Size bytes\r
  from SourceOffset exceeds the config space limit of the PCI device. Fewer\r
  than Size bytes may have been read in this case.\r
\r
  @param[in] PciDevice           Implementation-specific unique representation\r
                                 of the PCI device in the PCI hierarchy.\r
\r
  @param[in] SourceOffset        Source offset in the config space of the PCI\r
                                 device to start reading from.\r
\r
  @param[out] DestinationBuffer  Buffer to store the read data to.\r
\r
  @param[in] Size                The number of bytes to transfer.\r
\r
  @retval RETURN_SUCCESS  Size bytes have been transferred from config space to\r
                          DestinationBuffer.\r
\r
  @return                 Unspecified error codes. Fewer than Size bytes may\r
                          have been read.\r
**/\r
typedef\r
RETURN_STATUS\r
(EFIAPI *PCI_CAP_DEV_READ_CONFIG) (\r
  IN  PCI_CAP_DEV *PciDevice,\r
  IN  UINT16      SourceOffset,\r
  OUT VOID        *DestinationBuffer,\r
  IN  UINT16      Size\r
  );\r
\r
/**\r
  Write the config space of a given PCI device (both normal and extended).\r
\r
  PCI_CAP_DEV_WRITE_CONFIG performs as few config space accesses as possible\r
  (without attempting 64-bit wide accesses).\r
\r
  PCI_CAP_DEV_WRITE_CONFIG returns an unspecified error if accessing Size bytes\r
  at DestinationOffset exceeds the config space limit of the PCI device. Fewer\r
  than Size bytes may have been written in this case.\r
\r
  @param[in] PciDevice          Implementation-specific unique representation\r
                                of the PCI device in the PCI hierarchy.\r
\r
  @param[in] DestinationOffset  Destination offset in the config space of the\r
                                PCI device to start writing at.\r
\r
  @param[in] SourceBuffer       Buffer to read the data to be stored from.\r
\r
  @param[in] Size               The number of bytes to transfer.\r
\r
  @retval RETURN_SUCCESS  Size bytes have been transferred from SourceBuffer to\r
                          config space.\r
\r
  @return                 Unspecified error codes. Fewer than Size bytes may\r
                          have been written.\r
**/\r
typedef\r
RETURN_STATUS\r
(EFIAPI *PCI_CAP_DEV_WRITE_CONFIG) (\r
  IN PCI_CAP_DEV *PciDevice,\r
  IN UINT16      DestinationOffset,\r
  IN VOID        *SourceBuffer,\r
  IN UINT16      Size\r
  );\r
\r
//\r
// Complete the PCI_CAP_DEV type here. The base abstraction only requires\r
// config space accessors.\r
//\r
struct PCI_CAP_DEV {\r
  PCI_CAP_DEV_READ_CONFIG  ReadConfig;\r
  PCI_CAP_DEV_WRITE_CONFIG WriteConfig;\r
};\r
\r
//\r
// Opaque data structure representing parsed PCI Capabilities Lists.\r
//\r
typedef struct PCI_CAP_LIST PCI_CAP_LIST;\r
\r
//\r
// Opaque data structure representing a PCI Capability in a parsed Capability\r
// List.\r
//\r
typedef struct PCI_CAP PCI_CAP;\r
\r
//\r
// Distinguishes whether a Capability ID is 8-bit wide and interpreted in\r
// normal config space, or 16-bit wide and interpreted in extended config\r
// space. Capability ID definitions are relative to domain.\r
//\r
typedef enum {\r
  PciCapNormal,\r
  PciCapExtended\r
} PCI_CAP_DOMAIN;\r
\r
//\r
// Public data structure that PciCapGetInfo() fills in about a PCI_CAP object.\r
//\r
typedef struct {\r
  PCI_CAP_DOMAIN Domain;\r
  UINT16         CapId;\r
  //\r
  // The capability identified by Domain and CapId may have multiple instances\r
  // in config space. NumInstances provides the total count of occurrences of\r
  // the capability. It is always positive.\r
  //\r
  UINT16 NumInstances;\r
  //\r
  // Instance is the serial number, in capabilities list traversal order (not\r
  // necessarily config space offset order), of the one capability instance\r
  // that PciCapGetInfo() is reporting about. Instance is always smaller than\r
  // NumInstances.\r
  //\r
  UINT16 Instance;\r
  //\r
  // The offset in config space at which the capability header of the\r
  // capability instance starts.\r
  //\r
  UINT16 Offset;\r
  //\r
  // The deduced maximum size of the capability instance, including the\r
  // capability header. This hint is an upper bound, calculated -- without\r
  // regard to the internal structure of the capability -- from (a) the next\r
  // lowest offset in configuration space that is known to be used by another\r
  // capability, and (b) from the end of the config space identified by Domain,\r
  // whichever is lower.\r
  //\r
  UINT16 MaxSizeHint;\r
  //\r
  // The version number of the capability instance. Always zero when Domain is\r
  // PciCapNormal.\r
  //\r
  UINT8 Version;\r
} PCI_CAP_INFO;\r
\r
\r
/**\r
  Parse the capabilities lists (both normal and extended, as applicable) of a\r
  PCI device.\r
\r
  If the PCI device has no capabilities, that per se will not fail\r
  PciCapListInit(); an empty capabilities list will be represented.\r
\r
  If the PCI device is found to be PCI Express, then an attempt will be made to\r
  parse the extended capabilities list as well. If the first extended config\r
  space access -- via PciDevice->ReadConfig() with SourceOffset=0x100 and\r
  Size=4 -- fails, that per se will not fail PciCapListInit(); the device will\r
  be assumed to have no extended capabilities.\r
\r
  @param[in] PciDevice  Implementation-specific unique representation of the\r
                        PCI device in the PCI hierarchy.\r
\r
  @param[out] CapList   Opaque data structure that holds an in-memory\r
                        representation of the parsed capabilities lists of\r
                        PciDevice.\r
\r
  @retval RETURN_SUCCESS           The capabilities lists have been parsed from\r
                                   config space.\r
\r
  @retval RETURN_OUT_OF_RESOURCES  Memory allocation failed.\r
\r
  @retval RETURN_DEVICE_ERROR      A loop or some other kind of invalid pointer\r
                                   was detected in the capabilities lists of\r
                                   PciDevice.\r
\r
  @return                          Error codes propagated from\r
                                   PciDevice->ReadConfig().\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapListInit (\r
  IN  PCI_CAP_DEV  *PciDevice,\r
  OUT PCI_CAP_LIST **CapList\r
  );\r
\r
\r
/**\r
  Free the resources used by CapList.\r
\r
  @param[in] CapList  The PCI_CAP_LIST object to free, originally produced by\r
                      PciCapListInit().\r
**/\r
VOID\r
EFIAPI\r
PciCapListUninit (\r
  IN PCI_CAP_LIST *CapList\r
  );\r
\r
\r
/**\r
  Locate a capability instance in the parsed capabilities lists.\r
\r
  @param[in] CapList   The PCI_CAP_LIST object produced by PciCapListInit().\r
\r
  @param[in] Domain    Distinguishes whether CapId is 8-bit wide and\r
                       interpreted in normal config space, or 16-bit wide and\r
                       interpreted in extended config space. Capability ID\r
                       definitions are relative to domain.\r
\r
  @param[in] CapId     Capability identifier to look up.\r
\r
  @param[in] Instance  Domain and CapId may identify a multi-instance\r
                       capability. When Instance is zero, the first instance of\r
                       the capability is located (in list traversal order --\r
                       which may not mean increasing config space offset\r
                       order). Higher Instance values locate subsequent\r
                       instances of the same capability (in list traversal\r
                       order).\r
\r
  @param[out] Cap      The capability instance that matches the search\r
                       criteria. Cap is owned by CapList and becomes invalid\r
                       when CapList is freed with PciCapListUninit().\r
                       PciCapListFindCap() may be called with Cap set to NULL,\r
                       in order to test the existence of a specific capability\r
                       instance.\r
\r
  @retval RETURN_SUCCESS    The capability instance identified by (Domain,\r
                            CapId, Instance) has been found.\r
\r
  @retval RETURN_NOT_FOUND  The requested (Domain, CapId, Instance) capability\r
                            instance does not exist.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapListFindCap (\r
  IN  PCI_CAP_LIST   *CapList,\r
  IN  PCI_CAP_DOMAIN Domain,\r
  IN  UINT16         CapId,\r
  IN  UINT16         Instance,\r
  OUT PCI_CAP        **Cap    OPTIONAL\r
  );\r
\r
\r
/**\r
  Locate the first instance of the capability given by (Domain, CapId) such\r
  that the instance's Version is greater than or equal to MinVersion.\r
\r
  This is a convenience function that may save client code calls to\r
  PciCapListFindCap() and PciCapGetInfo().\r
\r
  @param[in] CapList     The PCI_CAP_LIST object produced by PciCapListInit().\r
\r
  @param[in] Domain      Distinguishes whether CapId is 8-bit wide and\r
                         interpreted in normal config space, or 16-bit wide and\r
                         interpreted in extended config space. Capability ID\r
                         definitions are relative to domain.\r
\r
  @param[in] CapId       Capability identifier to look up.\r
\r
  @param[in] MinVersion  The minimum version that the capability instance is\r
                         required to have. Note that all capability instances\r
                         in Domain=PciCapNormal have Version=0.\r
\r
  @param[out] Cap        The first capability instance that matches the search\r
                         criteria. Cap is owned by CapList and becomes invalid\r
                         when CapList is freed with PciCapListUninit().\r
                         PciCapListFindCapVersion() may be called with Cap set\r
                         to NULL, in order just to test whether the search\r
                         criteria are satisfiable.\r
\r
  @retval RETURN_SUCCESS    The first capability instance matching (Domain,\r
                            CapId, MinVersion) has been located.\r
\r
  @retval RETURN_NOT_FOUND  No capability instance matches (Domain, CapId,\r
                            MinVersion).\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapListFindCapVersion (\r
  IN  PCI_CAP_LIST   *CapList,\r
  IN  PCI_CAP_DOMAIN Domain,\r
  IN  UINT16         CapId,\r
  IN  UINT8          MinVersion,\r
  OUT PCI_CAP        **Cap      OPTIONAL\r
  );\r
\r
\r
/**\r
  Get information about a PCI Capability instance.\r
\r
  @param[in] Cap    The capability instance to get info about, located with\r
                    PciCapListFindCap*().\r
\r
  @param[out] Info  A PCI_CAP_INFO structure that describes the properties of\r
                    Cap.\r
\r
  @retval RETURN_SUCCESS  Fields of Info have been set.\r
\r
  @return                 Unspecified error codes, if filling in Info failed\r
                          for some reason.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapGetInfo (\r
  IN  PCI_CAP      *Cap,\r
  OUT PCI_CAP_INFO *Info\r
  );\r
\r
\r
/**\r
  Read a slice of a capability instance.\r
\r
  The function performs as few config space accesses as possible (without\r
  attempting 64-bit wide accesses). PciCapRead() performs bounds checking on\r
  SourceOffsetInCap and Size, and only invokes PciDevice->ReadConfig() if the\r
  requested transfer falls within Cap.\r
\r
  @param[in] PciDevice           Implementation-specific unique representation\r
                                 of the PCI device in the PCI hierarchy.\r
\r
  @param[in] Cap                 The capability instance to read, located with\r
                                 PciCapListFindCap*().\r
\r
  @param[in] SourceOffsetInCap   Source offset relative to the capability\r
                                 header to start reading from. A zero value\r
                                 refers to the first byte of the capability\r
                                 header.\r
\r
  @param[out] DestinationBuffer  Buffer to store the read data to.\r
\r
  @param[in] Size                The number of bytes to transfer.\r
\r
  @retval RETURN_SUCCESS          Size bytes have been transferred from Cap to\r
                                  DestinationBuffer.\r
\r
  @retval RETURN_BAD_BUFFER_SIZE  Reading Size bytes starting from\r
                                  SourceOffsetInCap would not (entirely) be\r
                                  contained within Cap, as suggested by\r
                                  PCI_CAP_INFO.MaxSizeHint. No bytes have been\r
                                  read.\r
\r
  @return                         Error codes propagated from\r
                                  PciDevice->ReadConfig(). Fewer than Size\r
                                  bytes may have been read.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapRead (\r
  IN  PCI_CAP_DEV *PciDevice,\r
  IN  PCI_CAP     *Cap,\r
  IN  UINT16      SourceOffsetInCap,\r
  OUT VOID        *DestinationBuffer,\r
  IN  UINT16      Size\r
  );\r
\r
\r
/**\r
  Write a slice of a capability instance.\r
\r
  The function performs as few config space accesses as possible (without\r
  attempting 64-bit wide accesses). PciCapWrite() performs bounds checking on\r
  DestinationOffsetInCap and Size, and only invokes PciDevice->WriteConfig() if\r
  the requested transfer falls within Cap.\r
\r
  @param[in] PciDevice               Implementation-specific unique\r
                                     representation of the PCI device in the\r
                                     PCI hierarchy.\r
\r
  @param[in] Cap                     The capability instance to write, located\r
                                     with PciCapListFindCap*().\r
\r
  @param[in] DestinationOffsetInCap  Destination offset relative to the\r
                                     capability header to start writing at. A\r
                                     zero value refers to the first byte of the\r
                                     capability header.\r
\r
  @param[in] SourceBuffer            Buffer to read the data to be stored from.\r
\r
  @param[in] Size                    The number of bytes to transfer.\r
\r
  @retval RETURN_SUCCESS          Size bytes have been transferred from\r
                                  SourceBuffer to Cap.\r
\r
  @retval RETURN_BAD_BUFFER_SIZE  Writing Size bytes starting at\r
                                  DestinationOffsetInCap would not (entirely)\r
                                  be contained within Cap, as suggested by\r
                                  PCI_CAP_INFO.MaxSizeHint. No bytes have been\r
                                  written.\r
\r
  @return                         Error codes propagated from\r
                                  PciDevice->WriteConfig(). Fewer than Size\r
                                  bytes may have been written.\r
**/\r
RETURN_STATUS\r
EFIAPI\r
PciCapWrite (\r
  IN PCI_CAP_DEV *PciDevice,\r
  IN PCI_CAP     *Cap,\r
  IN UINT16      DestinationOffsetInCap,\r
  IN VOID        *SourceBuffer,\r
  IN UINT16      Size\r
  );\r
\r
#endif // __PCI_CAP_LIB_H__\r
Commit	Line	Data
392a3146 LE	1	/** @file\r
	2	Library class to work with PCI capabilities in PCI config space.\r
	3	\r
	4	Provides functions to parse capabilities lists, and to locate, describe, read\r
	5	and write capabilities. PCI config space access is abstracted away.\r
	6	\r
	7	Copyright (C) 2018, Red Hat, Inc.\r
	8	\r
b26f0cf9	9	SPDX-License-Identifier: BSD-2-Clause-Patent\r
392a3146 LE	10	**/\r
	11	\r
	12	#ifndef __PCI_CAP_LIB_H__\r
	13	#define __PCI_CAP_LIB_H__\r
	14	\r
	15	#include <Uefi/UefiBaseType.h>\r
	16	\r
	17	//\r
	18	// Base structure for representing a PCI device -- down to the PCI function\r
	19	// level -- for the purposes of this library class. This is a forward\r
	20	// declaration that is completed below. Concrete implementations are supposed\r
	21	// to inherit and extend this type.\r
	22	//\r
	23	typedef struct PCI_CAP_DEV PCI_CAP_DEV;\r
	24	\r
	25	/**\r
	26	Read the config space of a given PCI device (both normal and extended).\r
	27	\r
	28	PCI_CAP_DEV_READ_CONFIG performs as few config space accesses as possible\r
	29	(without attempting 64-bit wide accesses).\r
	30	\r
	31	PCI_CAP_DEV_READ_CONFIG returns an unspecified error if accessing Size bytes\r
	32	from SourceOffset exceeds the config space limit of the PCI device. Fewer\r
	33	than Size bytes may have been read in this case.\r
	34	\r
	35	@param[in] PciDevice Implementation-specific unique representation\r
	36	of the PCI device in the PCI hierarchy.\r
	37	\r
	38	@param[in] SourceOffset Source offset in the config space of the PCI\r
	39	device to start reading from.\r
	40	\r
	41	@param[out] DestinationBuffer Buffer to store the read data to.\r
	42	\r
	43	@param[in] Size The number of bytes to transfer.\r
	44	\r
	45	@retval RETURN_SUCCESS Size bytes have been transferred from config space to\r
	46	DestinationBuffer.\r
	47	\r
	48	@return Unspecified error codes. Fewer than Size bytes may\r
	49	have been read.\r
	50	**/\r
	51	typedef\r
	52	RETURN_STATUS\r
	53	(EFIAPI *PCI_CAP_DEV_READ_CONFIG) (\r
	54	IN PCI_CAP_DEV *PciDevice,\r
	55	IN UINT16 SourceOffset,\r
	56	OUT VOID *DestinationBuffer,\r
	57	IN UINT16 Size\r
	58	);\r
	59	\r
	60	/**\r
	61	Write the config space of a given PCI device (both normal and extended).\r
	62	\r
	63	PCI_CAP_DEV_WRITE_CONFIG performs as few config space accesses as possible\r
	64	(without attempting 64-bit wide accesses).\r
	65	\r
	66	PCI_CAP_DEV_WRITE_CONFIG returns an unspecified error if accessing Size bytes\r
	67	at DestinationOffset exceeds the config space limit of the PCI device. Fewer\r
	68	than Size bytes may have been written in this case.\r
	69	\r
	70	@param[in] PciDevice Implementation-specific unique representation\r
	71	of the PCI device in the PCI hierarchy.\r
	72	\r
	73	@param[in] DestinationOffset Destination offset in the config space of the\r
74	PCI device to start writing at.\r
75	\r
76	@param[in] SourceBuffer Buffer to read the data to be stored from.\r
77	\r
78	@param[in] Size The number of bytes to transfer.\r
79	\r
80	@retval RETURN_SUCCESS Size bytes have been transferred from SourceBuffer to\r
81	config space.\r
82	\r
83	@return Unspecified error codes. Fewer than Size bytes may\r
84	have been written.\r
85	**/\r
86	typedef\r
87	RETURN_STATUS\r
88	(EFIAPI *PCI_CAP_DEV_WRITE_CONFIG) (\r
89	IN PCI_CAP_DEV *PciDevice,\r
90	IN UINT16 DestinationOffset,\r
91	IN VOID *SourceBuffer,\r
92	IN UINT16 Size\r
93	);\r
94	\r
95	//\r
96	// Complete the PCI_CAP_DEV type here. The base abstraction only requires\r
97	// config space accessors.\r
98	//\r
99	struct PCI_CAP_DEV {\r
100	PCI_CAP_DEV_READ_CONFIG ReadConfig;\r
101	PCI_CAP_DEV_WRITE_CONFIG WriteConfig;\r
102	};\r
103	\r
104	//\r
105	// Opaque data structure representing parsed PCI Capabilities Lists.\r
106	//\r
107	typedef struct PCI_CAP_LIST PCI_CAP_LIST;\r
108	\r
109	//\r
110	// Opaque data structure representing a PCI Capability in a parsed Capability\r
111	// List.\r
112	//\r
113	typedef struct PCI_CAP PCI_CAP;\r
114	\r
115	//\r
116	// Distinguishes whether a Capability ID is 8-bit wide and interpreted in\r
117	// normal config space, or 16-bit wide and interpreted in extended config\r
118	// space. Capability ID definitions are relative to domain.\r
119	//\r
120	typedef enum {\r
121	PciCapNormal,\r
122	PciCapExtended\r
123	} PCI_CAP_DOMAIN;\r
124	\r
125	//\r
126	// Public data structure that PciCapGetInfo() fills in about a PCI_CAP object.\r
127	//\r
128	typedef struct {\r
129	PCI_CAP_DOMAIN Domain;\r
130	UINT16 CapId;\r
131	//\r
132	// The capability identified by Domain and CapId may have multiple instances\r
133	// in config space. NumInstances provides the total count of occurrences of\r
134	// the capability. It is always positive.\r
135	//\r
136	UINT16 NumInstances;\r
137	//\r
138	// Instance is the serial number, in capabilities list traversal order (not\r
139	// necessarily config space offset order), of the one capability instance\r
140	// that PciCapGetInfo() is reporting about. Instance is always smaller than\r
141	// NumInstances.\r
142	//\r
143	UINT16 Instance;\r
144	//\r
145	// The offset in config space at which the capability header of the\r
146	// capability instance starts.\r
147	//\r
148	UINT16 Offset;\r
149	//\r
150	// The deduced maximum size of the capability instance, including the\r
151	// capability header. This hint is an upper bound, calculated -- without\r
152	// regard to the internal structure of the capability -- from (a) the next\r
153	// lowest offset in configuration space that is known to be used by another\r
154	// capability, and (b) from the end of the config space identified by Domain,\r
155	// whichever is lower.\r
156	//\r
157	UINT16 MaxSizeHint;\r
158	//\r
159	// The version number of the capability instance. Always zero when Domain is\r
160	// PciCapNormal.\r
161	//\r
162	UINT8 Version;\r
163	} PCI_CAP_INFO;\r
164	\r
165	\r
166	/**\r
167	Parse the capabilities lists (both normal and extended, as applicable) of a\r
168	PCI device.\r
169	\r
170	If the PCI device has no capabilities, that per se will not fail\r
171	PciCapListInit(); an empty capabilities list will be represented.\r
172	\r
173	If the PCI device is found to be PCI Express, then an attempt will be made to\r
174	parse the extended capabilities list as well. If the first extended config\r
175	space access -- via PciDevice->ReadConfig() with SourceOffset=0x100 and\r
176	Size=4 -- fails, that per se will not fail PciCapListInit(); the device will\r
177	be assumed to have no extended capabilities.\r
178	\r
179	@param[in] PciDevice Implementation-specific unique representation of the\r
180	PCI device in the PCI hierarchy.\r
181	\r
182	@param[out] CapList Opaque data structure that holds an in-memory\r
183	representation of the parsed capabilities lists of\r
184	PciDevice.\r
185	\r
186	@retval RETURN_SUCCESS The capabilities lists have been parsed from\r
187	config space.\r
188	\r
189	@retval RETURN_OUT_OF_RESOURCES Memory allocation failed.\r
190	\r
191	@retval RETURN_DEVICE_ERROR A loop or some other kind of invalid pointer\r
192	was detected in the capabilities lists of\r
193	PciDevice.\r
194	\r
195	@return Error codes propagated from\r
196	PciDevice->ReadConfig().\r
197	**/\r
198	RETURN_STATUS\r
199	EFIAPI\r
200	PciCapListInit (\r
201	IN PCI_CAP_DEV *PciDevice,\r
202	OUT PCI_CAP_LIST **CapList\r
203	);\r
204	\r
205	\r
206	/**\r
207	Free the resources used by CapList.\r
208	\r
209	@param[in] CapList The PCI_CAP_LIST object to free, originally produced by\r
210	PciCapListInit().\r
211	**/\r
212	VOID\r
213	EFIAPI\r
214	PciCapListUninit (\r
215	IN PCI_CAP_LIST *CapList\r
216	);\r
217	\r
218	\r
219	/**\r
220	Locate a capability instance in the parsed capabilities lists.\r
221	\r
222	@param[in] CapList The PCI_CAP_LIST object produced by PciCapListInit().\r
223	\r
224	@param[in] Domain Distinguishes whether CapId is 8-bit wide and\r
225	interpreted in normal config space, or 16-bit wide and\r
226	interpreted in extended config space. Capability ID\r
227	definitions are relative to domain.\r
228	\r
229	@param[in] CapId Capability identifier to look up.\r
230	\r
231	@param[in] Instance Domain and CapId may identify a multi-instance\r
232	capability. When Instance is zero, the first instance of\r
233	the capability is located (in list traversal order --\r
234	which may not mean increasing config space offset\r
235	order). Higher Instance values locate subsequent\r
236	instances of the same capability (in list traversal\r
237	order).\r
238	\r
239	@param[out] Cap The capability instance that matches the search\r
240	criteria. Cap is owned by CapList and becomes invalid\r
241	when CapList is freed with PciCapListUninit().\r
242	PciCapListFindCap() may be called with Cap set to NULL,\r
243	in order to test the existence of a specific capability\r
244	instance.\r
245	\r
246	@retval RETURN_SUCCESS The capability instance identified by (Domain,\r
247	CapId, Instance) has been found.\r
248	\r
249	@retval RETURN_NOT_FOUND The requested (Domain, CapId, Instance) capability\r
250	instance does not exist.\r
251	**/\r
252	RETURN_STATUS\r
253	EFIAPI\r
254	PciCapListFindCap (\r
255	IN PCI_CAP_LIST *CapList,\r
256	IN PCI_CAP_DOMAIN Domain,\r
257	IN UINT16 CapId,\r
258	IN UINT16 Instance,\r
259	OUT PCI_CAP **Cap OPTIONAL\r
260	);\r
261	\r
262	\r
263	/**\r
264	Locate the first instance of the capability given by (Domain, CapId) such\r
265	that the instance's Version is greater than or equal to MinVersion.\r
266	\r
267	This is a convenience function that may save client code calls to\r
268	PciCapListFindCap() and PciCapGetInfo().\r
269	\r
270	@param[in] CapList The PCI_CAP_LIST object produced by PciCapListInit().\r
271	\r
272	@param[in] Domain Distinguishes whether CapId is 8-bit wide and\r
273	interpreted in normal config space, or 16-bit wide and\r
274	interpreted in extended config space. Capability ID\r
275	definitions are relative to domain.\r
276	\r
277	@param[in] CapId Capability identifier to look up.\r
278	\r
279	@param[in] MinVersion The minimum version that the capability instance is\r
280	required to have. Note that all capability instances\r
281	in Domain=PciCapNormal have Version=0.\r
282	\r
283	@param[out] Cap The first capability instance that matches the search\r
284	criteria. Cap is owned by CapList and becomes invalid\r
285	when CapList is freed with PciCapListUninit().\r
286	PciCapListFindCapVersion() may be called with Cap set\r
287	to NULL, in order just to test whether the search\r
288	criteria are satisfiable.\r
289	\r
290	@retval RETURN_SUCCESS The first capability instance matching (Domain,\r
291	CapId, MinVersion) has been located.\r
292	\r
293	@retval RETURN_NOT_FOUND No capability instance matches (Domain, CapId,\r
294	MinVersion).\r
295	**/\r
296	RETURN_STATUS\r
297	EFIAPI\r
298	PciCapListFindCapVersion (\r
299	IN PCI_CAP_LIST *CapList,\r
300	IN PCI_CAP_DOMAIN Domain,\r
301	IN UINT16 CapId,\r
302	IN UINT8 MinVersion,\r
303	OUT PCI_CAP **Cap OPTIONAL\r
304	);\r
305	\r
306	\r
307	/**\r
308	Get information about a PCI Capability instance.\r
309	\r
310	@param[in] Cap The capability instance to get info about, located with\r
311	PciCapListFindCap*().\r
312	\r
313	@param[out] Info A PCI_CAP_INFO structure that describes the properties of\r
314	Cap.\r
315	\r
316	@retval RETURN_SUCCESS Fields of Info have been set.\r
317	\r
318	@return Unspecified error codes, if filling in Info failed\r
319	for some reason.\r
320	**/\r
321	RETURN_STATUS\r
322	EFIAPI\r
323	PciCapGetInfo (\r
324	IN PCI_CAP *Cap,\r
325	OUT PCI_CAP_INFO *Info\r
326	);\r
327	\r
328	\r
329	/**\r
330	Read a slice of a capability instance.\r
331	\r
332	The function performs as few config space accesses as possible (without\r
333	attempting 64-bit wide accesses). PciCapRead() performs bounds checking on\r
334	SourceOffsetInCap and Size, and only invokes PciDevice->ReadConfig() if the\r
335	requested transfer falls within Cap.\r
336	\r
337	@param[in] PciDevice Implementation-specific unique representation\r
338	of the PCI device in the PCI hierarchy.\r
339	\r
340	@param[in] Cap The capability instance to read, located with\r
341	PciCapListFindCap*().\r
342	\r
343	@param[in] SourceOffsetInCap Source offset relative to the capability\r
344	header to start reading from. A zero value\r
345	refers to the first byte of the capability\r
346	header.\r
347	\r
348	@param[out] DestinationBuffer Buffer to store the read data to.\r
349	\r
350	@param[in] Size The number of bytes to transfer.\r
351	\r
352	@retval RETURN_SUCCESS Size bytes have been transferred from Cap to\r
353	DestinationBuffer.\r
354	\r
355	@retval RETURN_BAD_BUFFER_SIZE Reading Size bytes starting from\r
356	SourceOffsetInCap would not (entirely) be\r
357	contained within Cap, as suggested by\r
358	PCI_CAP_INFO.MaxSizeHint. No bytes have been\r
359	read.\r
360	\r
361	@return Error codes propagated from\r
362	PciDevice->ReadConfig(). Fewer than Size\r
363	bytes may have been read.\r
364	**/\r
365	RETURN_STATUS\r
366	EFIAPI\r
367	PciCapRead (\r
368	IN PCI_CAP_DEV *PciDevice,\r
369	IN PCI_CAP *Cap,\r
370	IN UINT16 SourceOffsetInCap,\r
371	OUT VOID *DestinationBuffer,\r
372	IN UINT16 Size\r
373	);\r
374	\r
375	\r
376	/**\r
377	Write a slice of a capability instance.\r
378	\r
379	The function performs as few config space accesses as possible (without\r
380	attempting 64-bit wide accesses). PciCapWrite() performs bounds checking on\r
381	DestinationOffsetInCap and Size, and only invokes PciDevice->WriteConfig() if\r
382	the requested transfer falls within Cap.\r
383	\r
384	@param[in] PciDevice Implementation-specific unique\r
385	representation of the PCI device in the\r
386	PCI hierarchy.\r
387	\r
388	@param[in] Cap The capability instance to write, located\r
389	with PciCapListFindCap*().\r
390	\r
391	@param[in] DestinationOffsetInCap Destination offset relative to the\r
392	capability header to start writing at. A\r
393	zero value refers to the first byte of the\r
394	capability header.\r
395	\r
396	@param[in] SourceBuffer Buffer to read the data to be stored from.\r
397	\r
398	@param[in] Size The number of bytes to transfer.\r
399	\r
400	@retval RETURN_SUCCESS Size bytes have been transferred from\r
401	SourceBuffer to Cap.\r
402	\r
403	@retval RETURN_BAD_BUFFER_SIZE Writing Size bytes starting at\r
404	DestinationOffsetInCap would not (entirely)\r
405	be contained within Cap, as suggested by\r
406	PCI_CAP_INFO.MaxSizeHint. No bytes have been\r
407	written.\r
408	\r
409	@return Error codes propagated from\r
410	PciDevice->WriteConfig(). Fewer than Size\r
411	bytes may have been written.\r
412	**/\r
413	RETURN_STATUS\r
414	EFIAPI\r
415	PciCapWrite (\r
416	IN PCI_CAP_DEV *PciDevice,\r
417	IN PCI_CAP *Cap,\r
418	IN UINT16 DestinationOffsetInCap,\r
419	IN VOID *SourceBuffer,\r
420	IN UINT16 Size\r
421	);\r
422	\r
423	#endif // __PCI_CAP_LIB_H__\r