[mirror_edk2.git] / OvmfPkg / IncompatiblePciDeviceSupportDxe / IncompatiblePciDeviceSupport.c

/** @file\r
  A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
  MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
  is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
\r
  Copyright (C) 2016, Red Hat, Inc.\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
\r
  This program and the accompanying materials are licensed and made available\r
  under the terms and conditions of the BSD License which accompanies this\r
  distribution. The full text of the license may be found at\r
  http://opensource.org/licenses/bsd-license.php\r
\r
  THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
  WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
**/\r
\r
#include <IndustryStandard/Acpi10.h>\r
#include <IndustryStandard/Pci22.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/LegacyBios.h>\r
\r
//\r
// The Legacy BIOS protocol has been located.\r
//\r
STATIC BOOLEAN mLegacyBiosInstalled;\r
\r
//\r
// The protocol interface this driver produces.\r
//\r
STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
                                                 mIncompatiblePciDeviceSupport;\r
\r
//\r
// Configuration template for the CheckDevice() protocol member function.\r
//\r
// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
// the Platform Init 1.4a Spec, Volume 5.\r
//\r
// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
// PCI Bus UEFI_DRIVER.\r
//\r
#pragma pack (1)\r
typedef struct {\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;\r
  EFI_ACPI_END_TAG_DESCRIPTOR       EndDesc;\r
} MMIO64_PREFERENCE;\r
#pragma pack ()\r
\r
STATIC CONST MMIO64_PREFERENCE mConfiguration = {\r
  //\r
  // AddressSpaceDesc\r
  //\r
  {\r
    ACPI_ADDRESS_SPACE_DESCRIPTOR,                 // Desc\r
    (UINT16)(                                      // Len\r
      sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
      OFFSET_OF (\r
        EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
        ResType\r
        )\r
      ),\r
    ACPI_ADDRESS_SPACE_TYPE_MEM,                   // ResType\r
    0,                                             // GenFlag\r
    0,                                             // SpecificFlag\r
    64,                                            // AddrSpaceGranularity:\r
                                                   //   aperture selection hint\r
                                                   //   for BAR allocation\r
    0,                                             // AddrRangeMin\r
    0,                                             // AddrRangeMax:\r
                                                   //   no special alignment\r
                                                   //   for affected BARs\r
    MAX_UINT64,                                    // AddrTranslationOffset:\r
                                                   //   hint covers all\r
                                                   //   eligible BARs\r
    0                                              // AddrLen:\r
                                                   //   use probed BAR size\r
  },\r
  //\r
  // EndDesc\r
  //\r
  {\r
    ACPI_END_TAG_DESCRIPTOR,                       // Desc\r
    0                                              // Checksum: to be ignored\r
  }\r
};\r
\r
//\r
// The CheckDevice() member function has been called.\r
//\r
STATIC BOOLEAN mCheckDeviceCalled;\r
\r
\r
/**\r
  Notification callback for Legacy BIOS protocol installation.\r
\r
  @param[in] Event    Event whose notification function is being invoked.\r
\r
  @param[in] Context  The pointer to the notification function's context, which\r
                      is implementation-dependent.\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
LegacyBiosInstalled (\r
  IN EFI_EVENT Event,\r
  IN VOID      *Context\r
  )\r
{\r
  EFI_STATUS               Status;\r
  EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;\r
\r
  ASSERT (!mCheckDeviceCalled);\r
\r
  Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid,\r
                  NULL /* Registration */, (VOID **)&LegacyBios);\r
  if (EFI_ERROR (Status)) {\r
    return;\r
  }\r
\r
  mLegacyBiosInstalled = TRUE;\r
\r
  //\r
  // Close the event and deregister this callback.\r
  //\r
  Status = gBS->CloseEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
\r
/**\r
  Returns a list of ACPI resource descriptors that detail the special resource\r
  configuration requirements for an incompatible PCI device.\r
\r
  Prior to bus enumeration, the PCI bus driver will look for the presence of\r
  the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
  protocol can be present in the system. For each PCI device that the PCI bus\r
  driver discovers, the PCI bus driver calls this function with the device's\r
  vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
  ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
  SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
  ID values that are not (UINTN)-1 will be used to identify the current device.\r
\r
  This function will only return EFI_SUCCESS. However, if the device is an\r
  incompatible PCI device, a list of ACPI resource descriptors will be returned\r
  in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
  The PCI bus driver does not need to allocate memory for Configuration.\r
  However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
  driver then can configure this device with the information that is derived\r
  from this list of resource nodes, rather than the result of BAR probing.\r
\r
  Only the following two resource descriptor types from the ACPI Specification\r
  may be used to describe the incompatible PCI device resource requirements:\r
  - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
  - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
\r
  The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
  ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
  is described with one or more QWORD Address Space Descriptors, followed by an\r
  End Tag. See the ACPI Specification for details on the field values.\r
\r
  @param[in]  This                Pointer to the\r
                                  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
                                  instance.\r
\r
  @param[in]  VendorId            A unique ID to identify the manufacturer of\r
                                  the PCI device.  See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  DeviceId            A unique ID to identify the particular PCI\r
                                  device. See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  RevisionId          A PCI device-specific revision identifier.\r
                                  See the Conventional PCI Specification 3.0\r
                                  for details.\r
\r
  @param[in]  SubsystemVendorId   Specifies the subsystem vendor ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[in]  SubsystemDeviceId   Specifies the subsystem device ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[out] Configuration       A list of ACPI resource descriptors that\r
                                  detail the configuration requirement.\r
\r
  @retval EFI_SUCCESS   The function always returns EFI_SUCCESS.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
CheckDevice (\r
  IN  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL  *This,\r
  IN  UINTN                                         VendorId,\r
  IN  UINTN                                         DeviceId,\r
  IN  UINTN                                         RevisionId,\r
  IN  UINTN                                         SubsystemVendorId,\r
  IN  UINTN                                         SubsystemDeviceId,\r
  OUT VOID                                          **Configuration\r
  )\r
{\r
  mCheckDeviceCalled = TRUE;\r
\r
  //\r
  // Unlike the general description of this protocol member suggests, there is\r
  // nothing incompatible about the PCI devices that we'll match here. We'll\r
  // match all PCI devices, and generate exactly one QWORD Address Space\r
  // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
  // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
  // BAR is present on the device.\r
  //\r
  // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
  // (via a CSM) could dispatch a legacy option ROM on the device, which might\r
  // have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
  // address space. But, if we don't support legacy option ROMs at all, then\r
  // this problem cannot arise.\r
  //\r
  if (mLegacyBiosInstalled) {\r
    //\r
    // Don't interfere with resource degradation.\r
    //\r
    *Configuration = NULL;\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // This member function is mis-specified actually: it is supposed to allocate\r
  // memory, but as specified, it could not return an error status. Thankfully,\r
  // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
  // UpdatePciInfo() function.\r
  //\r
  *Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
  if (*Configuration == NULL) {\r
    DEBUG ((EFI_D_WARN,\r
      "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
      __FUNCTION__, (UINT32)VendorId, (UINT32)DeviceId, (UINT8)RevisionId));\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
  return EFI_SUCCESS;\r
}\r
\r
\r
/**\r
  Entry point for this driver.\r
\r
  @param[in] ImageHandle  Image handle of this driver.\r
  @param[in] SystemTable  Pointer to SystemTable.\r
\r
  @retval EFI_SUCESS       Driver has loaded successfully.\r
  @retval EFI_UNSUPPORTED  PCI resource allocation has been disabled.\r
  @retval EFI_UNSUPPORTED  There is no 64-bit PCI MMIO aperture.\r
  @return                  Error codes from lower level functions.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DriverInitialize (\r
  IN EFI_HANDLE       ImageHandle,\r
  IN EFI_SYSTEM_TABLE *SystemTable\r
  )\r
{\r
  EFI_STATUS Status;\r
  EFI_EVENT  Event;\r
  VOID       *Registration;\r
\r
  //\r
  // If the PCI Bus driver is not supposed to allocate resources, then it makes\r
  // no sense to install a protocol that influences the resource allocation.\r
  //\r
  // Similarly, if there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs\r
  // have to be allocated under 4 GB unconditionally.\r
  //\r
  if (PcdGetBool (PcdPciDisableBusEnumeration) ||\r
      PcdGet64 (PcdPciMmio64Size) == 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Otherwise, create a protocol notify to see if a CSM is present. (With the\r
  // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
  // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
  //\r
  // If the Legacy BIOS Protocol is present at the time of this driver starting\r
  // up, we can mark immediately that the PCI Bus driver should perform the\r
  // usual 64-bit MMIO BAR degradation.\r
  //\r
  // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
  // installed later. However, if it doesn't show up until the first\r
  // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
  // PCI Bus driver, then it never will:\r
  //\r
  // 1. The following drivers are dispatched in some unspecified order:\r
  //    - PCI Host Bridge DXE_DRIVER,\r
  //    - PCI Bus UEFI_DRIVER,\r
  //    - this DXE_DRIVER,\r
  //    - Legacy BIOS DXE_DRIVER.\r
  //\r
  // 2. The DXE_CORE enters BDS.\r
  //\r
  // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
  //    the PCI Host Bridge DXE_DRIVER).\r
  //\r
  // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
  //    DXE_DRIVER (CheckDevice()).\r
  //\r
  // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
  //    sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
  //\r
  // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
  // its protocol after the firmware enters BDS, which cannot happen.\r
  //\r
  Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
                  LegacyBiosInstalled, NULL /* Context */, &Event);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = gBS->RegisterProtocolNotify (&gEfiLegacyBiosProtocolGuid, Event,\r
                  &Registration);\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  Status = gBS->SignalEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
  Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
                  &gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
                  &mIncompatiblePciDeviceSupport, NULL);\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
CloseEvent:\r
  if (!mLegacyBiosInstalled) {\r
    EFI_STATUS CloseStatus;\r
\r
    CloseStatus = gBS->CloseEvent (Event);\r
    ASSERT_EFI_ERROR (CloseStatus);\r
  }\r
\r
  return Status;\r
}\r
Commit	Line	Data
855743f7 LE	1	/** @file\r
	2	A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
	3	MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
	4	is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
	5	\r
	6	Copyright (C) 2016, Red Hat, Inc.\r
a419fd0d	7	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
855743f7 LE	8	\r
	9	This program and the accompanying materials are licensed and made available\r
	10	under the terms and conditions of the BSD License which accompanies this\r
	11	distribution. The full text of the license may be found at\r
	12	http://opensource.org/licenses/bsd-license.php\r
	13	\r
	14	THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS, WITHOUT\r
	15	WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r
	16	**/\r
	17	\r
	18	#include <IndustryStandard/Acpi10.h>\r
	19	#include <IndustryStandard/Pci22.h>\r
	20	\r
	21	#include <Library/DebugLib.h>\r
	22	#include <Library/MemoryAllocationLib.h>\r
	23	#include <Library/PcdLib.h>\r
	24	#include <Library/UefiBootServicesTableLib.h>\r
	25	\r
	26	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	27	#include <Protocol/LegacyBios.h>\r
	28	\r
	29	//\r
	30	// The Legacy BIOS protocol has been located.\r
	31	//\r
	32	STATIC BOOLEAN mLegacyBiosInstalled;\r
	33	\r
	34	//\r
	35	// The protocol interface this driver produces.\r
	36	//\r
	37	STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
	38	mIncompatiblePciDeviceSupport;\r
	39	\r
	40	//\r
	41	// Configuration template for the CheckDevice() protocol member function.\r
	42	//\r
	43	// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
	44	// the Platform Init 1.4a Spec, Volume 5.\r
	45	//\r
	46	// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
	47	// PCI Bus UEFI_DRIVER.\r
	48	//\r
	49	#pragma pack (1)\r
	50	typedef struct {\r
	51	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;\r
	52	EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
	53	} MMIO64_PREFERENCE;\r
	54	#pragma pack ()\r
	55	\r
	56	STATIC CONST MMIO64_PREFERENCE mConfiguration = {\r
	57	//\r
	58	// AddressSpaceDesc\r
	59	//\r
	60	{\r
	61	ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc\r
	62	(UINT16)( // Len\r
	63	sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
	64	OFFSET_OF (\r
	65	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
	66	ResType\r
	67	)\r
	68	),\r
	69	ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType\r
a419fd0d RN	70	0, // GenFlag\r
a419fd0d RN	71	0, // SpecificFlag\r
855743f7 LE	72	64, // AddrSpaceGranularity:\r
	73	// aperture selection hint\r
	74	// for BAR allocation\r
a419fd0d RN	75	0, // AddrRangeMin\r
a419fd0d RN	76	0, // AddrRangeMax:\r
855743f7 LE	77	// no special alignment\r
855743f7 LE	78	// for affected BARs\r
a419fd0d	79	MAX_UINT64, // AddrTranslationOffset:\r
855743f7 LE	80	// hint covers all\r
855743f7 LE	81	// eligible BARs\r
a419fd0d	82	0 // AddrLen:\r
855743f7 LE	83	// use probed BAR size\r
	84	},\r
	85	//\r
	86	// EndDesc\r
	87	//\r
	88	{\r
	89	ACPI_END_TAG_DESCRIPTOR, // Desc\r
	90	0 // Checksum: to be ignored\r
	91	}\r
	92	};\r
	93	\r
	94	//\r
	95	// The CheckDevice() member function has been called.\r
	96	//\r
	97	STATIC BOOLEAN mCheckDeviceCalled;\r
	98	\r
	99	\r
	100	/**\r
	101	Notification callback for Legacy BIOS protocol installation.\r
	102	\r
	103	@param[in] Event Event whose notification function is being invoked.\r
	104	\r
	105	@param[in] Context The pointer to the notification function's context, which\r
	106	is implementation-dependent.\r
	107	**/\r
	108	STATIC\r
	109	VOID\r
	110	EFIAPI\r
	111	LegacyBiosInstalled (\r
	112	IN EFI_EVENT Event,\r
	113	IN VOID *Context\r
	114	)\r
	115	{\r
	116	EFI_STATUS Status;\r
	117	EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;\r
	118	\r
	119	ASSERT (!mCheckDeviceCalled);\r
	120	\r
	121	Status = gBS->LocateProtocol (&gEfiLegacyBiosProtocolGuid,\r
	122	NULL /* Registration /, (VOID *)&LegacyBios);\r
	123	if (EFI_ERROR (Status)) {\r
	124	return;\r
	125	}\r
	126	\r
	127	mLegacyBiosInstalled = TRUE;\r
	128	\r
	129	//\r
	130	// Close the event and deregister this callback.\r
	131	//\r
	132	Status = gBS->CloseEvent (Event);\r
	133	ASSERT_EFI_ERROR (Status);\r
	134	}\r
	135	\r
	136	\r
	137	/**\r
	138	Returns a list of ACPI resource descriptors that detail the special resource\r
	139	configuration requirements for an incompatible PCI device.\r
	140	\r
	141	Prior to bus enumeration, the PCI bus driver will look for the presence of\r
	142	the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
	143	protocol can be present in the system. For each PCI device that the PCI bus\r
	144	driver discovers, the PCI bus driver calls this function with the device's\r
	145	vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
	146	ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
147	SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
148	ID values that are not (UINTN)-1 will be used to identify the current device.\r
149	\r
150	This function will only return EFI_SUCCESS. However, if the device is an\r
151	incompatible PCI device, a list of ACPI resource descriptors will be returned\r
152	in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
153	The PCI bus driver does not need to allocate memory for Configuration.\r
154	However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
155	driver then can configure this device with the information that is derived\r
156	from this list of resource nodes, rather than the result of BAR probing.\r
157	\r
158	Only the following two resource descriptor types from the ACPI Specification\r
159	may be used to describe the incompatible PCI device resource requirements:\r
160	- QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
161	- End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
162	\r
163	The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
164	ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
165	is described with one or more QWORD Address Space Descriptors, followed by an\r
166	End Tag. See the ACPI Specification for details on the field values.\r
167	\r
168	@param[in] This Pointer to the\r
169	EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
170	instance.\r
171	\r
172	@param[in] VendorId A unique ID to identify the manufacturer of\r
173	the PCI device. See the Conventional PCI\r
174	Specification 3.0 for details.\r
175	\r
176	@param[in] DeviceId A unique ID to identify the particular PCI\r
177	device. See the Conventional PCI\r
178	Specification 3.0 for details.\r
179	\r
180	@param[in] RevisionId A PCI device-specific revision identifier.\r
181	See the Conventional PCI Specification 3.0\r
182	for details.\r
183	\r
184	@param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the\r
185	Conventional PCI Specification 3.0 for\r
186	details.\r
187	\r
188	@param[in] SubsystemDeviceId Specifies the subsystem device ID. See the\r
189	Conventional PCI Specification 3.0 for\r
190	details.\r
191	\r
192	@param[out] Configuration A list of ACPI resource descriptors that\r
193	detail the configuration requirement.\r
194	\r
195	@retval EFI_SUCCESS The function always returns EFI_SUCCESS.\r
196	**/\r
197	STATIC\r
198	EFI_STATUS\r
199	EFIAPI\r
200	CheckDevice (\r
201	IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,\r
202	IN UINTN VendorId,\r
203	IN UINTN DeviceId,\r
204	IN UINTN RevisionId,\r
205	IN UINTN SubsystemVendorId,\r
206	IN UINTN SubsystemDeviceId,\r
207	OUT VOID **Configuration\r
208	)\r
209	{\r
210	mCheckDeviceCalled = TRUE;\r
211	\r
212	//\r
213	// Unlike the general description of this protocol member suggests, there is\r
214	// nothing incompatible about the PCI devices that we'll match here. We'll\r
215	// match all PCI devices, and generate exactly one QWORD Address Space\r
216	// Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
217	// not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
218	// BAR is present on the device.\r
219	//\r
220	// The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
221	// (via a CSM) could dispatch a legacy option ROM on the device, which might\r
222	// have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
223	// address space. But, if we don't support legacy option ROMs at all, then\r
224	// this problem cannot arise.\r
225	//\r
226	if (mLegacyBiosInstalled) {\r
227	//\r
228	// Don't interfere with resource degradation.\r
229	//\r
230	*Configuration = NULL;\r
231	return EFI_SUCCESS;\r
232	}\r
233	\r
234	//\r
235	// This member function is mis-specified actually: it is supposed to allocate\r
236	// memory, but as specified, it could not return an error status. Thankfully,\r
237	// the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
238	// UpdatePciInfo() function.\r
239	//\r
240	*Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
241	if (*Configuration == NULL) {\r
242	DEBUG ((EFI_D_WARN,\r
243	"%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
244	__FUNCTION__, (UINT32)VendorId, (UINT32)DeviceId, (UINT8)RevisionId));\r
245	return EFI_OUT_OF_RESOURCES;\r
246	}\r
247	return EFI_SUCCESS;\r
248	}\r
249	\r
250	\r
251	/**\r
252	Entry point for this driver.\r
253	\r
254	@param[in] ImageHandle Image handle of this driver.\r
255	@param[in] SystemTable Pointer to SystemTable.\r
256	\r
257	@retval EFI_SUCESS Driver has loaded successfully.\r
258	@retval EFI_UNSUPPORTED PCI resource allocation has been disabled.\r
259	@retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.\r
260	@return Error codes from lower level functions.\r
261	\r
262	**/\r
263	EFI_STATUS\r
264	EFIAPI\r
265	DriverInitialize (\r
266	IN EFI_HANDLE ImageHandle,\r
267	IN EFI_SYSTEM_TABLE *SystemTable\r
268	)\r
269	{\r
270	EFI_STATUS Status;\r
271	EFI_EVENT Event;\r
272	VOID *Registration;\r
273	\r
274	//\r
275	// If the PCI Bus driver is not supposed to allocate resources, then it makes\r
276	// no sense to install a protocol that influences the resource allocation.\r
277	//\r
278	// Similarly, if there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs\r
279	// have to be allocated under 4 GB unconditionally.\r
280	//\r
281	if (PcdGetBool (PcdPciDisableBusEnumeration) \|\|\r
282	PcdGet64 (PcdPciMmio64Size) == 0) {\r
283	return EFI_UNSUPPORTED;\r
284	}\r
285	\r
286	//\r
287	// Otherwise, create a protocol notify to see if a CSM is present. (With the\r
288	// CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
289	// MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
290	//\r
291	// If the Legacy BIOS Protocol is present at the time of this driver starting\r
292	// up, we can mark immediately that the PCI Bus driver should perform the\r
293	// usual 64-bit MMIO BAR degradation.\r
294	//\r
295	// Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
296	// installed later. However, if it doesn't show up until the first\r
297	// EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
298	// PCI Bus driver, then it never will:\r
299	//\r
300	// 1. The following drivers are dispatched in some unspecified order:\r
301	// - PCI Host Bridge DXE_DRIVER,\r
302	// - PCI Bus UEFI_DRIVER,\r
303	// - this DXE_DRIVER,\r
304	// - Legacy BIOS DXE_DRIVER.\r
305	//\r
306	// 2. The DXE_CORE enters BDS.\r
307	//\r
308	// 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
309	// the PCI Host Bridge DXE_DRIVER).\r
310	//\r
311	// 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
312	// DXE_DRIVER (CheckDevice()).\r
313	//\r
314	// 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
315	// sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
316	//\r
317	// For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
318	// its protocol after the firmware enters BDS, which cannot happen.\r
319	//\r
320	Status = gBS->CreateEvent (EVT_NOTIFY_SIGNAL, TPL_CALLBACK,\r
321	LegacyBiosInstalled, NULL /* Context */, &Event);\r
322	if (EFI_ERROR (Status)) {\r
323	return Status;\r
324	}\r
325	\r
326	Status = gBS->RegisterProtocolNotify (&gEfiLegacyBiosProtocolGuid, Event,\r
327	&Registration);\r
328	if (EFI_ERROR (Status)) {\r
329	goto CloseEvent;\r
330	}\r
331	\r
332	Status = gBS->SignalEvent (Event);\r
333	ASSERT_EFI_ERROR (Status);\r
334	\r
335	mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
336	Status = gBS->InstallMultipleProtocolInterfaces (&ImageHandle,\r
337	&gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
338	&mIncompatiblePciDeviceSupport, NULL);\r
339	if (EFI_ERROR (Status)) {\r
340	goto CloseEvent;\r
341	}\r
342	\r
343	return EFI_SUCCESS;\r
344	\r
345	CloseEvent:\r
346	if (!mLegacyBiosInstalled) {\r
347	EFI_STATUS CloseStatus;\r
348	\r
349	CloseStatus = gBS->CloseEvent (Event);\r
350	ASSERT_EFI_ERROR (CloseStatus);\r
351	}\r
352	\r
353	return Status;\r
354	}\r