[mirror_edk2.git] / OvmfPkg / IncompatiblePciDeviceSupportDxe / IncompatiblePciDeviceSupport.c

/** @file\r
  A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
  MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
  is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
\r
  Copyright (C) 2016, Red Hat, Inc.\r
  Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
**/\r
\r
#include <IndustryStandard/Acpi10.h>\r
#include <IndustryStandard/Pci22.h>\r
\r
#include <Library/DebugLib.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiBootServicesTableLib.h>\r
\r
#include <Protocol/IncompatiblePciDeviceSupport.h>\r
#include <Protocol/LegacyBios.h>\r
\r
//\r
// The Legacy BIOS protocol has been located.\r
//\r
STATIC BOOLEAN  mLegacyBiosInstalled;\r
\r
//\r
// The protocol interface this driver produces.\r
//\r
STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
  mIncompatiblePciDeviceSupport;\r
\r
//\r
// Configuration template for the CheckDevice() protocol member function.\r
//\r
// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
// the Platform Init 1.4a Spec, Volume 5.\r
//\r
// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
// PCI Bus UEFI_DRIVER.\r
//\r
#pragma pack (1)\r
typedef struct {\r
  EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR    AddressSpaceDesc;\r
  EFI_ACPI_END_TAG_DESCRIPTOR          EndDesc;\r
} MMIO64_PREFERENCE;\r
#pragma pack ()\r
\r
STATIC CONST MMIO64_PREFERENCE  mConfiguration = {\r
  //\r
  // AddressSpaceDesc\r
  //\r
  {\r
    ACPI_ADDRESS_SPACE_DESCRIPTOR,                 // Desc\r
    (UINT16)(                                      // Len\r
                                                   sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
                                                   OFFSET_OF (\r
                                                     EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
                                                     ResType\r
                                                     )\r
                                                   ),\r
    ACPI_ADDRESS_SPACE_TYPE_MEM,                   // ResType\r
    0,                                             // GenFlag\r
    0,                                             // SpecificFlag\r
    64,                                            // AddrSpaceGranularity:\r
                                                   //   aperture selection hint\r
                                                   //   for BAR allocation\r
    0,                                             // AddrRangeMin\r
    0,                                             // AddrRangeMax:\r
                                                   //   no special alignment\r
                                                   //   for affected BARs\r
    MAX_UINT64,                                    // AddrTranslationOffset:\r
                                                   //   hint covers all\r
                                                   //   eligible BARs\r
    0                                              // AddrLen:\r
                                                   //   use probed BAR size\r
  },\r
  //\r
  // EndDesc\r
  //\r
  {\r
    ACPI_END_TAG_DESCRIPTOR,                       // Desc\r
    0                                              // Checksum: to be ignored\r
  }\r
};\r
\r
//\r
// The CheckDevice() member function has been called.\r
//\r
STATIC BOOLEAN  mCheckDeviceCalled;\r
\r
/**\r
  Notification callback for Legacy BIOS protocol installation.\r
\r
  @param[in] Event    Event whose notification function is being invoked.\r
\r
  @param[in] Context  The pointer to the notification function's context, which\r
                      is implementation-dependent.\r
**/\r
STATIC\r
VOID\r
EFIAPI\r
LegacyBiosInstalled (\r
  IN EFI_EVENT  Event,\r
  IN VOID       *Context\r
  )\r
{\r
  EFI_STATUS                Status;\r
  EFI_LEGACY_BIOS_PROTOCOL  *LegacyBios;\r
\r
  ASSERT (!mCheckDeviceCalled);\r
\r
  Status = gBS->LocateProtocol (\r
                  &gEfiLegacyBiosProtocolGuid,\r
                  NULL /* Registration */,\r
                  (VOID **)&LegacyBios\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    return;\r
  }\r
\r
  mLegacyBiosInstalled = TRUE;\r
\r
  //\r
  // Close the event and deregister this callback.\r
  //\r
  Status = gBS->CloseEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
}\r
\r
/**\r
  Returns a list of ACPI resource descriptors that detail the special resource\r
  configuration requirements for an incompatible PCI device.\r
\r
  Prior to bus enumeration, the PCI bus driver will look for the presence of\r
  the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
  protocol can be present in the system. For each PCI device that the PCI bus\r
  driver discovers, the PCI bus driver calls this function with the device's\r
  vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
  ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
  SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
  ID values that are not (UINTN)-1 will be used to identify the current device.\r
\r
  This function will only return EFI_SUCCESS. However, if the device is an\r
  incompatible PCI device, a list of ACPI resource descriptors will be returned\r
  in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
  The PCI bus driver does not need to allocate memory for Configuration.\r
  However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
  driver then can configure this device with the information that is derived\r
  from this list of resource nodes, rather than the result of BAR probing.\r
\r
  Only the following two resource descriptor types from the ACPI Specification\r
  may be used to describe the incompatible PCI device resource requirements:\r
  - QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
  - End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
\r
  The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
  ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
  is described with one or more QWORD Address Space Descriptors, followed by an\r
  End Tag. See the ACPI Specification for details on the field values.\r
\r
  @param[in]  This                Pointer to the\r
                                  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
                                  instance.\r
\r
  @param[in]  VendorId            A unique ID to identify the manufacturer of\r
                                  the PCI device.  See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  DeviceId            A unique ID to identify the particular PCI\r
                                  device. See the Conventional PCI\r
                                  Specification 3.0 for details.\r
\r
  @param[in]  RevisionId          A PCI device-specific revision identifier.\r
                                  See the Conventional PCI Specification 3.0\r
                                  for details.\r
\r
  @param[in]  SubsystemVendorId   Specifies the subsystem vendor ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[in]  SubsystemDeviceId   Specifies the subsystem device ID. See the\r
                                  Conventional PCI Specification 3.0 for\r
                                  details.\r
\r
  @param[out] Configuration       A list of ACPI resource descriptors that\r
                                  detail the configuration requirement.\r
\r
  @retval EFI_SUCCESS   The function always returns EFI_SUCCESS.\r
**/\r
STATIC\r
EFI_STATUS\r
EFIAPI\r
CheckDevice (\r
  IN  EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL  *This,\r
  IN  UINTN                                         VendorId,\r
  IN  UINTN                                         DeviceId,\r
  IN  UINTN                                         RevisionId,\r
  IN  UINTN                                         SubsystemVendorId,\r
  IN  UINTN                                         SubsystemDeviceId,\r
  OUT VOID                                          **Configuration\r
  )\r
{\r
  mCheckDeviceCalled = TRUE;\r
\r
  //\r
  // Unlike the general description of this protocol member suggests, there is\r
  // nothing incompatible about the PCI devices that we'll match here. We'll\r
  // match all PCI devices, and generate exactly one QWORD Address Space\r
  // Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
  // not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
  // BAR is present on the device.\r
  //\r
  // The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
  // (via a CSM) could dispatch a legacy option ROM on the device, which might\r
  // have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
  // address space. But, if we don't support legacy option ROMs at all, then\r
  // this problem cannot arise.\r
  //\r
  if (mLegacyBiosInstalled) {\r
    //\r
    // Don't interfere with resource degradation.\r
    //\r
    *Configuration = NULL;\r
    return EFI_SUCCESS;\r
  }\r
\r
  //\r
  // This member function is mis-specified actually: it is supposed to allocate\r
  // memory, but as specified, it could not return an error status. Thankfully,\r
  // the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
  // UpdatePciInfo() function.\r
  //\r
  *Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
  if (*Configuration == NULL) {\r
    DEBUG ((\r
      DEBUG_WARN,\r
      "%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
      __FUNCTION__,\r
      (UINT32)VendorId,\r
      (UINT32)DeviceId,\r
      (UINT8)RevisionId\r
      ));\r
    return EFI_OUT_OF_RESOURCES;\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Entry point for this driver.\r
\r
  @param[in] ImageHandle  Image handle of this driver.\r
  @param[in] SystemTable  Pointer to SystemTable.\r
\r
  @retval EFI_SUCESS       Driver has loaded successfully.\r
  @retval EFI_UNSUPPORTED  PCI resource allocation has been disabled.\r
  @retval EFI_UNSUPPORTED  There is no 64-bit PCI MMIO aperture.\r
  @return                  Error codes from lower level functions.\r
\r
**/\r
EFI_STATUS\r
EFIAPI\r
DriverInitialize (\r
  IN EFI_HANDLE        ImageHandle,\r
  IN EFI_SYSTEM_TABLE  *SystemTable\r
  )\r
{\r
  EFI_STATUS  Status;\r
  EFI_EVENT   Event;\r
  VOID        *Registration;\r
\r
  //\r
  // If there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs have to be\r
  // allocated under 4 GB unconditionally.\r
  //\r
  if (PcdGet64 (PcdPciMmio64Size) == 0) {\r
    return EFI_UNSUPPORTED;\r
  }\r
\r
  //\r
  // Otherwise, create a protocol notify to see if a CSM is present. (With the\r
  // CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
  // MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
  //\r
  // If the Legacy BIOS Protocol is present at the time of this driver starting\r
  // up, we can mark immediately that the PCI Bus driver should perform the\r
  // usual 64-bit MMIO BAR degradation.\r
  //\r
  // Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
  // installed later. However, if it doesn't show up until the first\r
  // EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
  // PCI Bus driver, then it never will:\r
  //\r
  // 1. The following drivers are dispatched in some unspecified order:\r
  //    - PCI Host Bridge DXE_DRIVER,\r
  //    - PCI Bus UEFI_DRIVER,\r
  //    - this DXE_DRIVER,\r
  //    - Legacy BIOS DXE_DRIVER.\r
  //\r
  // 2. The DXE_CORE enters BDS.\r
  //\r
  // 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
  //    the PCI Host Bridge DXE_DRIVER).\r
  //\r
  // 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
  //    DXE_DRIVER (CheckDevice()).\r
  //\r
  // 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
  //    sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
  //\r
  // For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
  // its protocol after the firmware enters BDS, which cannot happen.\r
  //\r
  Status = gBS->CreateEvent (\r
                  EVT_NOTIFY_SIGNAL,\r
                  TPL_CALLBACK,\r
                  LegacyBiosInstalled,\r
                  NULL /* Context */,\r
                  &Event\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  Status = gBS->RegisterProtocolNotify (\r
                  &gEfiLegacyBiosProtocolGuid,\r
                  Event,\r
                  &Registration\r
                  );\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  Status = gBS->SignalEvent (Event);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
  Status                                    = gBS->InstallMultipleProtocolInterfaces (\r
                                                     &ImageHandle,\r
                                                     &gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
                                                     &mIncompatiblePciDeviceSupport,\r
                                                     NULL\r
                                                     );\r
  if (EFI_ERROR (Status)) {\r
    goto CloseEvent;\r
  }\r
\r
  return EFI_SUCCESS;\r
\r
CloseEvent:\r
  if (!mLegacyBiosInstalled) {\r
    EFI_STATUS  CloseStatus;\r
\r
    CloseStatus = gBS->CloseEvent (Event);\r
    ASSERT_EFI_ERROR (CloseStatus);\r
  }\r
\r
  return Status;\r
}\r
Commit	Line	Data
855743f7 LE	1	/** @file\r
	2	A simple DXE_DRIVER that causes the PCI Bus UEFI_DRIVER to allocate 64-bit\r
	3	MMIO BARs above 4 GB, regardless of option ROM availability (as long as a CSM\r
	4	is not present), conserving 32-bit MMIO aperture for 32-bit BARs.\r
	5	\r
	6	Copyright (C) 2016, Red Hat, Inc.\r
a419fd0d	7	Copyright (c) 2017, Intel Corporation. All rights reserved.<BR>\r
855743f7	8	\r
b26f0cf9	9	SPDX-License-Identifier: BSD-2-Clause-Patent\r
855743f7 LE	10	**/\r
	11	\r
	12	#include <IndustryStandard/Acpi10.h>\r
	13	#include <IndustryStandard/Pci22.h>\r
	14	\r
	15	#include <Library/DebugLib.h>\r
	16	#include <Library/MemoryAllocationLib.h>\r
	17	#include <Library/PcdLib.h>\r
	18	#include <Library/UefiBootServicesTableLib.h>\r
	19	\r
	20	#include <Protocol/IncompatiblePciDeviceSupport.h>\r
	21	#include <Protocol/LegacyBios.h>\r
	22	\r
	23	//\r
	24	// The Legacy BIOS protocol has been located.\r
	25	//\r
ac0a286f	26	STATIC BOOLEAN mLegacyBiosInstalled;\r
855743f7 LE	27	\r
	28	//\r
	29	// The protocol interface this driver produces.\r
	30	//\r
	31	STATIC EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
ac0a286f	32	mIncompatiblePciDeviceSupport;\r
855743f7 LE	33	\r
	34	//\r
	35	// Configuration template for the CheckDevice() protocol member function.\r
	36	//\r
	37	// Refer to Table 20 "ACPI 2.0 & 3.0 QWORD Address Space Descriptor Usage" in\r
	38	// the Platform Init 1.4a Spec, Volume 5.\r
	39	//\r
	40	// This structure is interpreted by the UpdatePciInfo() function in the edk2\r
	41	// PCI Bus UEFI_DRIVER.\r
	42	//\r
	43	#pragma pack (1)\r
	44	typedef struct {\r
ac0a286f MK	45	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR AddressSpaceDesc;\r
ac0a286f MK	46	EFI_ACPI_END_TAG_DESCRIPTOR EndDesc;\r
855743f7 LE	47	} MMIO64_PREFERENCE;\r
	48	#pragma pack ()\r
	49	\r
ac0a286f	50	STATIC CONST MMIO64_PREFERENCE mConfiguration = {\r
855743f7 LE	51	//\r
	52	// AddressSpaceDesc\r
	53	//\r
	54	{\r
	55	ACPI_ADDRESS_SPACE_DESCRIPTOR, // Desc\r
	56	(UINT16)( // Len\r
ac0a286f MK	57	sizeof (EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR) -\r
	58	OFFSET_OF (\r
	59	EFI_ACPI_ADDRESS_SPACE_DESCRIPTOR,\r
	60	ResType\r
	61	)\r
	62	),\r
855743f7	63	ACPI_ADDRESS_SPACE_TYPE_MEM, // ResType\r
a419fd0d RN	64	0, // GenFlag\r
a419fd0d RN	65	0, // SpecificFlag\r
855743f7 LE	66	64, // AddrSpaceGranularity:\r
	67	// aperture selection hint\r
	68	// for BAR allocation\r
a419fd0d RN	69	0, // AddrRangeMin\r
a419fd0d RN	70	0, // AddrRangeMax:\r
855743f7 LE	71	// no special alignment\r
855743f7 LE	72	// for affected BARs\r
a419fd0d	73	MAX_UINT64, // AddrTranslationOffset:\r
855743f7 LE	74	// hint covers all\r
855743f7 LE	75	// eligible BARs\r
a419fd0d	76	0 // AddrLen:\r
855743f7 LE	77	// use probed BAR size\r
	78	},\r
	79	//\r
	80	// EndDesc\r
	81	//\r
	82	{\r
	83	ACPI_END_TAG_DESCRIPTOR, // Desc\r
	84	0 // Checksum: to be ignored\r
	85	}\r
	86	};\r
	87	\r
	88	//\r
	89	// The CheckDevice() member function has been called.\r
	90	//\r
ac0a286f	91	STATIC BOOLEAN mCheckDeviceCalled;\r
855743f7 LE	92	\r
	93	/**\r
	94	Notification callback for Legacy BIOS protocol installation.\r
	95	\r
	96	@param[in] Event Event whose notification function is being invoked.\r
	97	\r
	98	@param[in] Context The pointer to the notification function's context, which\r
	99	is implementation-dependent.\r
	100	**/\r
	101	STATIC\r
	102	VOID\r
	103	EFIAPI\r
	104	LegacyBiosInstalled (\r
ac0a286f MK	105	IN EFI_EVENT Event,\r
ac0a286f MK	106	IN VOID *Context\r
855743f7 LE	107	)\r
855743f7 LE	108	{\r
ac0a286f MK	109	EFI_STATUS Status;\r
ac0a286f MK	110	EFI_LEGACY_BIOS_PROTOCOL *LegacyBios;\r
855743f7 LE	111	\r
	112	ASSERT (!mCheckDeviceCalled);\r
	113	\r
ac0a286f MK	114	Status = gBS->LocateProtocol (\r
	115	&gEfiLegacyBiosProtocolGuid,\r
	116	NULL /* Registration */,\r
	117	(VOID **)&LegacyBios\r
	118	);\r
855743f7 LE	119	if (EFI_ERROR (Status)) {\r
	120	return;\r
	121	}\r
	122	\r
	123	mLegacyBiosInstalled = TRUE;\r
	124	\r
	125	//\r
	126	// Close the event and deregister this callback.\r
	127	//\r
	128	Status = gBS->CloseEvent (Event);\r
	129	ASSERT_EFI_ERROR (Status);\r
	130	}\r
	131	\r
855743f7 LE	132	/**\r
	133	Returns a list of ACPI resource descriptors that detail the special resource\r
	134	configuration requirements for an incompatible PCI device.\r
	135	\r
	136	Prior to bus enumeration, the PCI bus driver will look for the presence of\r
	137	the EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL. Only one instance of this\r
	138	protocol can be present in the system. For each PCI device that the PCI bus\r
	139	driver discovers, the PCI bus driver calls this function with the device's\r
	140	vendor ID, device ID, revision ID, subsystem vendor ID, and subsystem device\r
	141	ID. If the VendorId, DeviceId, RevisionId, SubsystemVendorId, or\r
	142	SubsystemDeviceId value is set to (UINTN)-1, that field will be ignored. The\r
	143	ID values that are not (UINTN)-1 will be used to identify the current device.\r
	144	\r
	145	This function will only return EFI_SUCCESS. However, if the device is an\r
	146	incompatible PCI device, a list of ACPI resource descriptors will be returned\r
	147	in Configuration. Otherwise, NULL will be returned in Configuration instead.\r
	148	The PCI bus driver does not need to allocate memory for Configuration.\r
	149	However, it is the PCI bus driver's responsibility to free it. The PCI bus\r
	150	driver then can configure this device with the information that is derived\r
	151	from this list of resource nodes, rather than the result of BAR probing.\r
	152	\r
	153	Only the following two resource descriptor types from the ACPI Specification\r
	154	may be used to describe the incompatible PCI device resource requirements:\r
	155	- QWORD Address Space Descriptor (ACPI 2.0, section 6.4.3.5.1; also ACPI 3.0)\r
	156	- End Tag (ACPI 2.0, section 6.4.2.8; also ACPI 3.0)\r
	157	\r
	158	The QWORD Address Space Descriptor can describe memory, I/O, and bus number\r
	159	ranges for dynamic or fixed resources. The configuration of a PCI root bridge\r
	160	is described with one or more QWORD Address Space Descriptors, followed by an\r
	161	End Tag. See the ACPI Specification for details on the field values.\r
	162	\r
	163	@param[in] This Pointer to the\r
	164	EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL\r
	165	instance.\r
	166	\r
	167	@param[in] VendorId A unique ID to identify the manufacturer of\r
	168	the PCI device. See the Conventional PCI\r
	169	Specification 3.0 for details.\r
	170	\r
	171	@param[in] DeviceId A unique ID to identify the particular PCI\r
	172	device. See the Conventional PCI\r
	173	Specification 3.0 for details.\r
	174	\r
	175	@param[in] RevisionId A PCI device-specific revision identifier.\r
	176	See the Conventional PCI Specification 3.0\r
	177	for details.\r
	178	\r
	179	@param[in] SubsystemVendorId Specifies the subsystem vendor ID. See the\r
	180	Conventional PCI Specification 3.0 for\r
	181	details.\r
	182	\r
	183	@param[in] SubsystemDeviceId Specifies the subsystem device ID. See the\r
	184	Conventional PCI Specification 3.0 for\r
	185	details.\r
	186	\r
	187	@param[out] Configuration A list of ACPI resource descriptors that\r
	188	detail the configuration requirement.\r
	189	\r
	190	@retval EFI_SUCCESS The function always returns EFI_SUCCESS.\r
	191	**/\r
	192	STATIC\r
	193	EFI_STATUS\r
	194	EFIAPI\r
	195	CheckDevice (\r
196	IN EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL *This,\r
197	IN UINTN VendorId,\r
198	IN UINTN DeviceId,\r
199	IN UINTN RevisionId,\r
200	IN UINTN SubsystemVendorId,\r
201	IN UINTN SubsystemDeviceId,\r
202	OUT VOID **Configuration\r
203	)\r
204	{\r
205	mCheckDeviceCalled = TRUE;\r
206	\r
207	//\r
208	// Unlike the general description of this protocol member suggests, there is\r
209	// nothing incompatible about the PCI devices that we'll match here. We'll\r
210	// match all PCI devices, and generate exactly one QWORD Address Space\r
211	// Descriptor for each. That descriptor will instruct the PCI Bus UEFI_DRIVER\r
212	// not to degrade 64-bit MMIO BARs for the device, even if a PCI option ROM\r
213	// BAR is present on the device.\r
214	//\r
215	// The concern captured in the PCI Bus UEFI_DRIVER is that a legacy BIOS boot\r
216	// (via a CSM) could dispatch a legacy option ROM on the device, which might\r
217	// have trouble with MMIO BARs that have been allocated outside of the 32-bit\r
218	// address space. But, if we don't support legacy option ROMs at all, then\r
219	// this problem cannot arise.\r
220	//\r
221	if (mLegacyBiosInstalled) {\r
222	//\r
223	// Don't interfere with resource degradation.\r
224	//\r
225	*Configuration = NULL;\r
226	return EFI_SUCCESS;\r
227	}\r
228	\r
229	//\r
230	// This member function is mis-specified actually: it is supposed to allocate\r
231	// memory, but as specified, it could not return an error status. Thankfully,\r
232	// the edk2 PCI Bus UEFI_DRIVER actually handles error codes; see the\r
233	// UpdatePciInfo() function.\r
234	//\r
235	*Configuration = AllocateCopyPool (sizeof mConfiguration, &mConfiguration);\r
236	if (*Configuration == NULL) {\r
ac0a286f MK	237	DEBUG ((\r
ac0a286f MK	238	DEBUG_WARN,\r
855743f7	239	"%a: 64-bit MMIO BARs may be degraded for PCI 0x%04x:0x%04x (rev %d)\n",\r
ac0a286f MK	240	__FUNCTION__,\r
	241	(UINT32)VendorId,\r
	242	(UINT32)DeviceId,\r
	243	(UINT8)RevisionId\r
	244	));\r
855743f7 LE	245	return EFI_OUT_OF_RESOURCES;\r
855743f7 LE	246	}\r
ac0a286f	247	\r
855743f7 LE	248	return EFI_SUCCESS;\r
	249	}\r
	250	\r
855743f7 LE	251	/**\r
	252	Entry point for this driver.\r
	253	\r
	254	@param[in] ImageHandle Image handle of this driver.\r
	255	@param[in] SystemTable Pointer to SystemTable.\r
	256	\r
	257	@retval EFI_SUCESS Driver has loaded successfully.\r
	258	@retval EFI_UNSUPPORTED PCI resource allocation has been disabled.\r
	259	@retval EFI_UNSUPPORTED There is no 64-bit PCI MMIO aperture.\r
	260	@return Error codes from lower level functions.\r
	261	\r
	262	**/\r
	263	EFI_STATUS\r
	264	EFIAPI\r
	265	DriverInitialize (\r
ac0a286f MK	266	IN EFI_HANDLE ImageHandle,\r
ac0a286f MK	267	IN EFI_SYSTEM_TABLE *SystemTable\r
855743f7 LE	268	)\r
855743f7 LE	269	{\r
ac0a286f MK	270	EFI_STATUS Status;\r
	271	EFI_EVENT Event;\r
	272	VOID *Registration;\r
855743f7 LE	273	\r
855743f7 LE	274	//\r
984c93ec LE	275	// If there is no 64-bit PCI MMIO aperture, then 64-bit MMIO BARs have to be\r
984c93ec LE	276	// allocated under 4 GB unconditionally.\r
855743f7	277	//\r
984c93ec	278	if (PcdGet64 (PcdPciMmio64Size) == 0) {\r
855743f7 LE	279	return EFI_UNSUPPORTED;\r
	280	}\r
	281	\r
	282	//\r
	283	// Otherwise, create a protocol notify to see if a CSM is present. (With the\r
	284	// CSM absent, the PCI Bus driver won't have to worry about allocating 64-bit\r
	285	// MMIO BARs in the 32-bit MMIO aperture, for the sake of a legacy BIOS.)\r
	286	//\r
	287	// If the Legacy BIOS Protocol is present at the time of this driver starting\r
	288	// up, we can mark immediately that the PCI Bus driver should perform the\r
	289	// usual 64-bit MMIO BAR degradation.\r
	290	//\r
	291	// Otherwise, if the Legacy BIOS Protocol is absent at startup, it may be\r
	292	// installed later. However, if it doesn't show up until the first\r
	293	// EFI_INCOMPATIBLE_PCI_DEVICE_SUPPORT_PROTOCOL.CheckDevice() call from the\r
	294	// PCI Bus driver, then it never will:\r
	295	//\r
	296	// 1. The following drivers are dispatched in some unspecified order:\r
	297	// - PCI Host Bridge DXE_DRIVER,\r
	298	// - PCI Bus UEFI_DRIVER,\r
	299	// - this DXE_DRIVER,\r
	300	// - Legacy BIOS DXE_DRIVER.\r
	301	//\r
	302	// 2. The DXE_CORE enters BDS.\r
	303	//\r
	304	// 3. The platform BDS connects the PCI Root Bridge IO instances (produced by\r
	305	// the PCI Host Bridge DXE_DRIVER).\r
	306	//\r
	307	// 4. The PCI Bus UEFI_DRIVER enumerates resources and calls into this\r
	308	// DXE_DRIVER (CheckDevice()).\r
	309	//\r
	310	// 5. This driver remembers if EFI_LEGACY_BIOS_PROTOCOL has been installed\r
	311	// sometime during step 1 (produced by the Legacy BIOS DXE_DRIVER).\r
	312	//\r
	313	// For breaking this order, the Legacy BIOS DXE_DRIVER would have to install\r
	314	// its protocol after the firmware enters BDS, which cannot happen.\r
	315	//\r
ac0a286f MK	316	Status = gBS->CreateEvent (\r
	317	EVT_NOTIFY_SIGNAL,\r
	318	TPL_CALLBACK,\r
	319	LegacyBiosInstalled,\r
	320	NULL /* Context */,\r
	321	&Event\r
	322	);\r
855743f7 LE	323	if (EFI_ERROR (Status)) {\r
	324	return Status;\r
	325	}\r
	326	\r
ac0a286f MK	327	Status = gBS->RegisterProtocolNotify (\r
	328	&gEfiLegacyBiosProtocolGuid,\r
	329	Event,\r
	330	&Registration\r
	331	);\r
855743f7 LE	332	if (EFI_ERROR (Status)) {\r
	333	goto CloseEvent;\r
	334	}\r
	335	\r
	336	Status = gBS->SignalEvent (Event);\r
	337	ASSERT_EFI_ERROR (Status);\r
	338	\r
	339	mIncompatiblePciDeviceSupport.CheckDevice = CheckDevice;\r
ac0a286f MK	340	Status = gBS->InstallMultipleProtocolInterfaces (\r
	341	&ImageHandle,\r
	342	&gEfiIncompatiblePciDeviceSupportProtocolGuid,\r
	343	&mIncompatiblePciDeviceSupport,\r
	344	NULL\r
	345	);\r
855743f7 LE	346	if (EFI_ERROR (Status)) {\r
	347	goto CloseEvent;\r
	348	}\r
	349	\r
	350	return EFI_SUCCESS;\r
	351	\r
	352	CloseEvent:\r
	353	if (!mLegacyBiosInstalled) {\r
ac0a286f	354	EFI_STATUS CloseStatus;\r
855743f7 LE	355	\r
	356	CloseStatus = gBS->CloseEvent (Event);\r
	357	ASSERT_EFI_ERROR (CloseStatus);\r
	358	}\r
	359	\r
	360	return Status;\r
	361	}\r