OvmfPkg: Refactor ProcessHobList

[mirror_edk2.git] / OvmfPkg / IntelTdx / Sec / SecMain.c

/** @file\r
  Main SEC phase code.  Transitions to PEI.\r
\r
  Copyright (c) 2008 - 2015, Intel Corporation. All rights reserved.<BR>\r
  (C) Copyright 2016 Hewlett Packard Enterprise Development LP<BR>\r
  Copyright (c) 2020, Advanced Micro Devices, Inc. All rights reserved.<BR>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
#include <PiPei.h>\r
\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/UefiCpuLib.h>\r
#include <Library/DebugAgentLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/PeCoffLib.h>\r
#include <Library/PeCoffGetEntryPointLib.h>\r
#include <Library/LocalApicLib.h>\r
#include <Library/CpuExceptionHandlerLib.h>\r
#include <IndustryStandard/Tdx.h>\r
#include <Library/TdxHelperLib.h>\r
#include <Library/CcProbeLib.h>\r
#include <Library/PeilessStartupLib.h>\r
\r
#define SEC_IDT_ENTRY_COUNT  34\r
\r
typedef struct _SEC_IDT_TABLE {\r
  EFI_PEI_SERVICES            *PeiService;\r
  IA32_IDT_GATE_DESCRIPTOR    IdtTable[SEC_IDT_ENTRY_COUNT];\r
} SEC_IDT_TABLE;\r
\r
//\r
// Template of an IDT entry pointing to 10:FFFFFFE4h.\r
//\r
IA32_IDT_GATE_DESCRIPTOR  mIdtEntryTemplate = {\r
  {                                      // Bits\r
    0xffe4,                              // OffsetLow\r
    0x10,                                // Selector\r
    0x0,                                 // Reserved_0\r
    IA32_IDT_GATE_TYPE_INTERRUPT_32,     // GateType\r
    0xffff                               // OffsetHigh\r
  }\r
};\r
\r
VOID\r
EFIAPI\r
SecCoreStartupWithStack (\r
  IN EFI_FIRMWARE_VOLUME_HEADER  *BootFv,\r
  IN VOID                        *TopOfCurrentStack\r
  )\r
{\r
  EFI_SEC_PEI_HAND_OFF  SecCoreData;\r
  SEC_IDT_TABLE         IdtTableInStack;\r
  IA32_DESCRIPTOR       IdtDescriptor;\r
  UINT32                Index;\r
  volatile UINT8        *Table;\r
\r
  if (CcProbe () == CcGuestTypeIntelTdx) {\r
    //\r
    // For Td guests, the memory map info is in TdHobLib. It should be processed\r
    // first so that the memory is accepted. Otherwise access to the unaccepted\r
    // memory will trigger tripple fault.\r
    //\r
    if (TdxHelperProcessTdHob () != EFI_SUCCESS) {\r
      CpuDeadLoop ();\r
    }\r
  }\r
\r
  //\r
  // To ensure SMM can't be compromised on S3 resume, we must force re-init of\r
  // the BaseExtractGuidedSectionLib. Since this is before library contructors\r
  // are called, we must use a loop rather than SetMem.\r
  //\r
  Table = (UINT8 *)(UINTN)FixedPcdGet64 (PcdGuidedExtractHandlerTableAddress);\r
  for (Index = 0;\r
       Index < FixedPcdGet32 (PcdGuidedExtractHandlerTableSize);\r
       ++Index)\r
  {\r
    Table[Index] = 0;\r
  }\r
\r
  //\r
  // Initialize IDT - Since this is before library constructors are called,\r
  // we use a loop rather than CopyMem.\r
  //\r
  IdtTableInStack.PeiService = NULL;\r
\r
  for (Index = 0; Index < SEC_IDT_ENTRY_COUNT; Index++) {\r
    //\r
    // Declare the local variables that actually move the data elements as\r
    // volatile to prevent the optimizer from replacing this function with\r
    // the intrinsic memcpy()\r
    //\r
    CONST UINT8     *Src;\r
    volatile UINT8  *Dst;\r
    UINTN           Byte;\r
\r
    Src = (CONST UINT8 *)&mIdtEntryTemplate;\r
    Dst = (volatile UINT8 *)&IdtTableInStack.IdtTable[Index];\r
\r
    for (Byte = 0; Byte < sizeof (mIdtEntryTemplate); Byte++) {\r
      Dst[Byte] = Src[Byte];\r
    }\r
  }\r
\r
  IdtDescriptor.Base  = (UINTN)&IdtTableInStack.IdtTable;\r
  IdtDescriptor.Limit = (UINT16)(sizeof (IdtTableInStack.IdtTable) - 1);\r
\r
  ProcessLibraryConstructorList (NULL, NULL);\r
\r
  //\r
  // Load the IDTR.\r
  //\r
  AsmWriteIdtr (&IdtDescriptor);\r
\r
  if (CcProbe () == CcGuestTypeIntelTdx) {\r
    //\r
    // InitializeCpuExceptionHandlers () should be called in Td guests so that\r
    // #VE exceptions can be handled correctly.\r
    //\r
    InitializeCpuExceptionHandlers (NULL);\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "SecCoreStartupWithStack(0x%x, 0x%x)\n",\r
    (UINT32)(UINTN)BootFv,\r
    (UINT32)(UINTN)TopOfCurrentStack\r
    ));\r
\r
  //\r
  // Initialize floating point operating environment\r
  // to be compliant with UEFI spec.\r
  //\r
  InitializeFloatingPointUnits ();\r
\r
  //\r
  // ASSERT that the Page Tables were set by the reset vector code to\r
  // the address we expect.\r
  //\r
  ASSERT (AsmReadCr3 () == (UINTN)PcdGet32 (PcdOvmfSecPageTablesBase));\r
\r
  //\r
  // |-------------|       <-- TopOfCurrentStack\r
  // |   Stack     | 32k\r
  // |-------------|\r
  // |    Heap     | 32k\r
  // |-------------|       <-- SecCoreData.TemporaryRamBase\r
  //\r
\r
  ASSERT (\r
    (UINTN)(PcdGet32 (PcdOvmfSecPeiTempRamBase) +\r
            PcdGet32 (PcdOvmfSecPeiTempRamSize)) ==\r
    (UINTN)TopOfCurrentStack\r
    );\r
\r
  //\r
  // Initialize SEC hand-off state\r
  //\r
  SecCoreData.DataSize = sizeof (EFI_SEC_PEI_HAND_OFF);\r
\r
  SecCoreData.TemporaryRamSize = (UINTN)PcdGet32 (PcdOvmfSecPeiTempRamSize);\r
  SecCoreData.TemporaryRamBase = (VOID *)((UINT8 *)TopOfCurrentStack - SecCoreData.TemporaryRamSize);\r
\r
  SecCoreData.PeiTemporaryRamBase = SecCoreData.TemporaryRamBase;\r
  SecCoreData.PeiTemporaryRamSize = SecCoreData.TemporaryRamSize >> 1;\r
\r
  SecCoreData.StackBase = (UINT8 *)SecCoreData.TemporaryRamBase + SecCoreData.PeiTemporaryRamSize;\r
  SecCoreData.StackSize = SecCoreData.TemporaryRamSize >> 1;\r
\r
  SecCoreData.BootFirmwareVolumeBase = BootFv;\r
  SecCoreData.BootFirmwareVolumeSize = (UINTN)BootFv->FvLength;\r
\r
  //\r
  // Make sure the 8259 is masked before initializing the Debug Agent and the debug timer is enabled\r
  //\r
  IoWrite8 (0x21, 0xff);\r
  IoWrite8 (0xA1, 0xff);\r
\r
  //\r
  // Initialize Local APIC Timer hardware and disable Local APIC Timer\r
  // interrupts before initializing the Debug Agent and the debug timer is\r
  // enabled.\r
  //\r
  InitializeApicTimer (0, MAX_UINT32, TRUE, 5);\r
  DisableApicTimerInterrupt ();\r
\r
  PeilessStartup (&SecCoreData);\r
\r
  ASSERT (FALSE);\r
  CpuDeadLoop ();\r
}\r