projects / mirror_edk2.git / blame
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| 7523788f LE |
1 | /** @file\r |
| 2 | PCI Library functions that use\r | |
| 3 | (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering\r | |
| 4 | on top of one PCI CF8 Library instance; or\r | |
| 5 | (b) PCI Library functions that use the 256 MB PCI Express MMIO window to\r | |
| 6 | perform PCI Configuration cycles, layering on PCI Express Library.\r | |
| 7 | \r | |
| 8 | The decision is made in the entry point function, based on the OVMF platform\r | |
| 9 | type, and then adhered to during the lifetime of the client module.\r | |
| 10 | \r | |
| 11 | Copyright (C) 2016, Red Hat, Inc.\r | |
| 12 | \r | |
| 13 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
| 14 | This program and the accompanying materials\r | |
| 15 | are licensed and made available under the terms and conditions of the BSD License\r | |
| 16 | which accompanies this distribution. The full text of the license may be found at\r | |
| 17 | http://opensource.org/licenses/bsd-license.php.\r | |
| 18 | \r | |
| 19 | THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,\r | |
| 20 | WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.\r | |
| 21 | \r | |
| 22 | **/\r | |
| 23 | \r | |
| 24 | \r | |
| 25 | #include <Base.h>\r | |
| 26 | \r | |
| 27 | #include <IndustryStandard/Q35MchIch9.h>\r | |
| 28 | \r | |
| 29 | #include <Library/PciLib.h>\r | |
| 30 | #include <Library/PciCf8Lib.h>\r | |
| 31 | #include <Library/PciExpressLib.h>\r | |
| 32 | #include <Library/PcdLib.h>\r | |
| 33 | \r | |
| 34 | STATIC BOOLEAN mRunningOnQ35;\r | |
| 35 | \r | |
| 36 | RETURN_STATUS\r | |
| 37 | EFIAPI\r | |
| 38 | InitializeConfigAccessMethod (\r | |
| 39 | VOID\r | |
| 40 | )\r | |
| 41 | {\r | |
| 42 | mRunningOnQ35 = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==\r | |
| 43 | INTEL_Q35_MCH_DEVICE_ID);\r | |
| 44 | return RETURN_SUCCESS;\r | |
| 45 | }\r | |
| 46 | \r | |
| 47 | /**\r | |
| 48 | Registers a PCI device so PCI configuration registers may be accessed after \r | |
| 49 | SetVirtualAddressMap().\r | |
| 50 | \r | |
| 51 | Registers the PCI device specified by Address so all the PCI configuration registers \r | |
| 52 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
| 53 | \r | |
| 54 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 55 | \r | |
| 56 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 57 | Register.\r | |
| 58 | \r | |
| 59 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
| 60 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
| 61 | after ExitBootServices().\r | |
| 62 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
| 63 | at runtime could not be mapped.\r | |
| 64 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
| 65 | complete the registration.\r | |
| 66 | \r | |
| 67 | **/\r | |
| 68 | RETURN_STATUS\r | |
| 69 | EFIAPI\r | |
| 70 | PciRegisterForRuntimeAccess (\r | |
| 71 | IN UINTN Address\r | |
| 72 | )\r | |
| 73 | {\r | |
| 74 | return mRunningOnQ35 ?\r | |
| 75 | PciExpressRegisterForRuntimeAccess (Address) :\r | |
| 76 | PciCf8RegisterForRuntimeAccess (Address);\r | |
| 77 | }\r | |
| 78 | \r | |
| 79 | /**\r | |
| 80 | Reads an 8-bit PCI configuration register.\r | |
| 81 | \r | |
| 82 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
| 83 | This function must guarantee that all PCI read and write operations are\r | |
| 84 | serialized.\r | |
| 85 | \r | |
| 86 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 87 | \r | |
| 88 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 89 | Register.\r | |
| 90 | \r | |
| 91 | @return The read value from the PCI configuration register.\r | |
| 92 | \r | |
| 93 | **/\r | |
| 94 | UINT8\r | |
| 95 | EFIAPI\r | |
| 96 | PciRead8 (\r | |
| 97 | IN UINTN Address\r | |
| 98 | )\r | |
| 99 | {\r | |
| 100 | return mRunningOnQ35 ?\r | |
| 101 | PciExpressRead8 (Address) :\r | |
| 102 | PciCf8Read8 (Address);\r | |
| 103 | }\r | |
| 104 | \r | |
| 105 | /**\r | |
| 106 | Writes an 8-bit PCI configuration register.\r | |
| 107 | \r | |
| 108 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
| 109 | value specified by Value. Value is returned. This function must guarantee\r | |
| 110 | that all PCI read and write operations are serialized.\r | |
| 111 | \r | |
| 112 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 113 | \r | |
| 114 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 115 | Register.\r | |
| 116 | @param Value The value to write.\r | |
| 117 | \r | |
| 118 | @return The value written to the PCI configuration register.\r | |
| 119 | \r | |
| 120 | **/\r | |
| 121 | UINT8\r | |
| 122 | EFIAPI\r | |
| 123 | PciWrite8 (\r | |
| 124 | IN UINTN Address,\r | |
| 125 | IN UINT8 Value\r | |
| 126 | )\r | |
| 127 | {\r | |
| 128 | return mRunningOnQ35 ?\r | |
| 129 | PciExpressWrite8 (Address, Value) :\r | |
| 130 | PciCf8Write8 (Address, Value);\r | |
| 131 | }\r | |
| 132 | \r | |
| 133 | /**\r | |
| 134 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
| 135 | an 8-bit value.\r | |
| 136 | \r | |
| 137 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 138 | bitwise OR between the read result and the value specified by\r | |
| 139 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 140 | specified by Address. The value written to the PCI configuration register is\r | |
| 141 | returned. This function must guarantee that all PCI read and write operations\r | |
| 142 | are serialized.\r | |
| 143 | \r | |
| 144 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 145 | \r | |
| 146 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 147 | Register.\r | |
| 148 | @param OrData The value to OR with the PCI configuration register.\r | |
| 149 | \r | |
| 150 | @return The value written back to the PCI configuration register.\r | |
| 151 | \r | |
| 152 | **/\r | |
| 153 | UINT8\r | |
| 154 | EFIAPI\r | |
| 155 | PciOr8 (\r | |
| 156 | IN UINTN Address,\r | |
| 157 | IN UINT8 OrData\r | |
| 158 | )\r | |
| 159 | {\r | |
| 160 | return mRunningOnQ35 ?\r | |
| 161 | PciExpressOr8 (Address, OrData) :\r | |
| 162 | PciCf8Or8 (Address, OrData);\r | |
| 163 | }\r | |
| 164 | \r | |
| 165 | /**\r | |
| 166 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 167 | value.\r | |
| 168 | \r | |
| 169 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 170 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 171 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 172 | Address. The value written to the PCI configuration register is returned.\r | |
| 173 | This function must guarantee that all PCI read and write operations are\r | |
| 174 | serialized.\r | |
| 175 | \r | |
| 176 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 177 | \r | |
| 178 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 179 | Register.\r | |
| 180 | @param AndData The value to AND with the PCI configuration register.\r | |
| 181 | \r | |
| 182 | @return The value written back to the PCI configuration register.\r | |
| 183 | \r | |
| 184 | **/\r | |
| 185 | UINT8\r | |
| 186 | EFIAPI\r | |
| 187 | PciAnd8 (\r | |
| 188 | IN UINTN Address,\r | |
| 189 | IN UINT8 AndData\r | |
| 190 | )\r | |
| 191 | {\r | |
| 192 | return mRunningOnQ35 ?\r | |
| 193 | PciExpressAnd8 (Address, AndData) :\r | |
| 194 | PciCf8And8 (Address, AndData);\r | |
| 195 | }\r | |
| 196 | \r | |
| 197 | /**\r | |
| 198 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 199 | value, followed a bitwise OR with another 8-bit value.\r | |
| 200 | \r | |
| 201 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 202 | bitwise AND between the read result and the value specified by AndData,\r | |
| 203 | performs a bitwise OR between the result of the AND operation and\r | |
| 204 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
| 205 | configuration register specified by Address. The value written to the PCI\r | |
| 206 | configuration register is returned. This function must guarantee that all PCI\r | |
| 207 | read and write operations are serialized.\r | |
| 208 | \r | |
| 209 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 210 | \r | |
| 211 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 212 | Register.\r | |
| 213 | @param AndData The value to AND with the PCI configuration register.\r | |
| 214 | @param OrData The value to OR with the result of the AND operation.\r | |
| 215 | \r | |
| 216 | @return The value written back to the PCI configuration register.\r | |
| 217 | \r | |
| 218 | **/\r | |
| 219 | UINT8\r | |
| 220 | EFIAPI\r | |
| 221 | PciAndThenOr8 (\r | |
| 222 | IN UINTN Address,\r | |
| 223 | IN UINT8 AndData,\r | |
| 224 | IN UINT8 OrData\r | |
| 225 | )\r | |
| 226 | {\r | |
| 227 | return mRunningOnQ35 ?\r | |
| 228 | PciExpressAndThenOr8 (Address, AndData, OrData) :\r | |
| 229 | PciCf8AndThenOr8 (Address, AndData, OrData);\r | |
| 230 | }\r | |
| 231 | \r | |
| 232 | /**\r | |
| 233 | Reads a bit field of a PCI configuration register.\r | |
| 234 | \r | |
| 235 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
| 236 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 237 | returned.\r | |
| 238 | \r | |
| 239 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 240 | If StartBit is greater than 7, then ASSERT().\r | |
| 241 | If EndBit is greater than 7, then ASSERT().\r | |
| 242 | If EndBit is less than StartBit, then ASSERT().\r | |
| 243 | \r | |
| 244 | @param Address The PCI configuration register to read.\r | |
| 245 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 246 | Range 0..7.\r | |
| 247 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 248 | Range 0..7.\r | |
| 249 | \r | |
| 250 | @return The value of the bit field read from the PCI configuration register.\r | |
| 251 | \r | |
| 252 | **/\r | |
| 253 | UINT8\r | |
| 254 | EFIAPI\r | |
| 255 | PciBitFieldRead8 (\r | |
| 256 | IN UINTN Address,\r | |
| 257 | IN UINTN StartBit,\r | |
| 258 | IN UINTN EndBit\r | |
| 259 | )\r | |
| 260 | {\r | |
| 261 | return mRunningOnQ35 ?\r | |
| 262 | PciExpressBitFieldRead8 (Address, StartBit, EndBit) :\r | |
| 263 | PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r | |
| 264 | }\r | |
| 265 | \r | |
| 266 | /**\r | |
| 267 | Writes a bit field to a PCI configuration register.\r | |
| 268 | \r | |
| 269 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 270 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 271 | destination PCI configuration register are preserved. The new value of the\r | |
| 272 | 8-bit register is returned.\r | |
| 273 | \r | |
| 274 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 275 | If StartBit is greater than 7, then ASSERT().\r | |
| 276 | If EndBit is greater than 7, then ASSERT().\r | |
| 277 | If EndBit is less than StartBit, then ASSERT().\r | |
| 278 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 279 | \r | |
| 280 | @param Address The PCI configuration register to write.\r | |
| 281 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 282 | Range 0..7.\r | |
| 283 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 284 | Range 0..7.\r | |
| 285 | @param Value The new value of the bit field.\r | |
| 286 | \r | |
| 287 | @return The value written back to the PCI configuration register.\r | |
| 288 | \r | |
| 289 | **/\r | |
| 290 | UINT8\r | |
| 291 | EFIAPI\r | |
| 292 | PciBitFieldWrite8 (\r | |
| 293 | IN UINTN Address,\r | |
| 294 | IN UINTN StartBit,\r | |
| 295 | IN UINTN EndBit,\r | |
| 296 | IN UINT8 Value\r | |
| 297 | )\r | |
| 298 | {\r | |
| 299 | return mRunningOnQ35 ?\r | |
| 300 | PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value) :\r | |
| 301 | PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
| 302 | }\r | |
| 303 | \r | |
| 304 | /**\r | |
| 305 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
| 306 | writes the result back to the bit field in the 8-bit port.\r | |
| 307 | \r | |
| 308 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 309 | bitwise OR between the read result and the value specified by\r | |
| 310 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 311 | specified by Address. The value written to the PCI configuration register is\r | |
| 312 | returned. This function must guarantee that all PCI read and write operations\r | |
| 313 | are serialized. Extra left bits in OrData are stripped.\r | |
| 314 | \r | |
| 315 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 316 | If StartBit is greater than 7, then ASSERT().\r | |
| 317 | If EndBit is greater than 7, then ASSERT().\r | |
| 318 | If EndBit is less than StartBit, then ASSERT().\r | |
| 319 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 320 | \r | |
| 321 | @param Address The PCI configuration register to write.\r | |
| 322 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 323 | Range 0..7.\r | |
| 324 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 325 | Range 0..7.\r | |
| 326 | @param OrData The value to OR with the PCI configuration register.\r | |
| 327 | \r | |
| 328 | @return The value written back to the PCI configuration register.\r | |
| 329 | \r | |
| 330 | **/\r | |
| 331 | UINT8\r | |
| 332 | EFIAPI\r | |
| 333 | PciBitFieldOr8 (\r | |
| 334 | IN UINTN Address,\r | |
| 335 | IN UINTN StartBit,\r | |
| 336 | IN UINTN EndBit,\r | |
| 337 | IN UINT8 OrData\r | |
| 338 | )\r | |
| 339 | {\r | |
| 340 | return mRunningOnQ35 ?\r | |
| 341 | PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData) :\r | |
| 342 | PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
| 343 | }\r | |
| 344 | \r | |
| 345 | /**\r | |
| 346 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
| 347 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
| 348 | \r | |
| 349 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 350 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 351 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 352 | Address. The value written to the PCI configuration register is returned.\r | |
| 353 | This function must guarantee that all PCI read and write operations are\r | |
| 354 | serialized. Extra left bits in AndData are stripped.\r | |
| 355 | \r | |
| 356 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 357 | If StartBit is greater than 7, then ASSERT().\r | |
| 358 | If EndBit is greater than 7, then ASSERT().\r | |
| 359 | If EndBit is less than StartBit, then ASSERT().\r | |
| 360 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 361 | \r | |
| 362 | @param Address The PCI configuration register to write.\r | |
| 363 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 364 | Range 0..7.\r | |
| 365 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 366 | Range 0..7.\r | |
| 367 | @param AndData The value to AND with the PCI configuration register.\r | |
| 368 | \r | |
| 369 | @return The value written back to the PCI configuration register.\r | |
| 370 | \r | |
| 371 | **/\r | |
| 372 | UINT8\r | |
| 373 | EFIAPI\r | |
| 374 | PciBitFieldAnd8 (\r | |
| 375 | IN UINTN Address,\r | |
| 376 | IN UINTN StartBit,\r | |
| 377 | IN UINTN EndBit,\r | |
| 378 | IN UINT8 AndData\r | |
| 379 | )\r | |
| 380 | {\r | |
| 381 | return mRunningOnQ35 ?\r | |
| 382 | PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData) :\r | |
| 383 | PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
| 384 | }\r | |
| 385 | \r | |
| 386 | /**\r | |
| 387 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
| 388 | bitwise OR, and writes the result back to the bit field in the\r | |
| 389 | 8-bit port.\r | |
| 390 | \r | |
| 391 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 392 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 393 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
| 394 | configuration register specified by Address. The value written to the PCI\r | |
| 395 | configuration register is returned. This function must guarantee that all PCI\r | |
| 396 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 397 | OrData are stripped.\r | |
| 398 | \r | |
| 399 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 400 | If StartBit is greater than 7, then ASSERT().\r | |
| 401 | If EndBit is greater than 7, then ASSERT().\r | |
| 402 | If EndBit is less than StartBit, then ASSERT().\r | |
| 403 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 404 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 405 | \r | |
| 406 | @param Address The PCI configuration register to write.\r | |
| 407 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 408 | Range 0..7.\r | |
| 409 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 410 | Range 0..7.\r | |
| 411 | @param AndData The value to AND with the PCI configuration register.\r | |
| 412 | @param OrData The value to OR with the result of the AND operation.\r | |
| 413 | \r | |
| 414 | @return The value written back to the PCI configuration register.\r | |
| 415 | \r | |
| 416 | **/\r | |
| 417 | UINT8\r | |
| 418 | EFIAPI\r | |
| 419 | PciBitFieldAndThenOr8 (\r | |
| 420 | IN UINTN Address,\r | |
| 421 | IN UINTN StartBit,\r | |
| 422 | IN UINTN EndBit,\r | |
| 423 | IN UINT8 AndData,\r | |
| 424 | IN UINT8 OrData\r | |
| 425 | )\r | |
| 426 | {\r | |
| 427 | return mRunningOnQ35 ?\r | |
| 428 | PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 429 | PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 430 | }\r | |
| 431 | \r | |
| 432 | /**\r | |
| 433 | Reads a 16-bit PCI configuration register.\r | |
| 434 | \r | |
| 435 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
| 436 | This function must guarantee that all PCI read and write operations are\r | |
| 437 | serialized.\r | |
| 438 | \r | |
| 439 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 440 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 441 | \r | |
| 442 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 443 | Register.\r | |
| 444 | \r | |
| 445 | @return The read value from the PCI configuration register.\r | |
| 446 | \r | |
| 447 | **/\r | |
| 448 | UINT16\r | |
| 449 | EFIAPI\r | |
| 450 | PciRead16 (\r | |
| 451 | IN UINTN Address\r | |
| 452 | )\r | |
| 453 | {\r | |
| 454 | return mRunningOnQ35 ?\r | |
| 455 | PciExpressRead16 (Address) :\r | |
| 456 | PciCf8Read16 (Address);\r | |
| 457 | }\r | |
| 458 | \r | |
| 459 | /**\r | |
| 460 | Writes a 16-bit PCI configuration register.\r | |
| 461 | \r | |
| 462 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
| 463 | value specified by Value. Value is returned. This function must guarantee\r | |
| 464 | that all PCI read and write operations are serialized.\r | |
| 465 | \r | |
| 466 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 467 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 468 | \r | |
| 469 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 470 | Register.\r | |
| 471 | @param Value The value to write.\r | |
| 472 | \r | |
| 473 | @return The value written to the PCI configuration register.\r | |
| 474 | \r | |
| 475 | **/\r | |
| 476 | UINT16\r | |
| 477 | EFIAPI\r | |
| 478 | PciWrite16 (\r | |
| 479 | IN UINTN Address,\r | |
| 480 | IN UINT16 Value\r | |
| 481 | )\r | |
| 482 | {\r | |
| 483 | return mRunningOnQ35 ?\r | |
| 484 | PciExpressWrite16 (Address, Value) :\r | |
| 485 | PciCf8Write16 (Address, Value);\r | |
| 486 | }\r | |
| 487 | \r | |
| 488 | /**\r | |
| 489 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
| 490 | a 16-bit value.\r | |
| 491 | \r | |
| 492 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 493 | bitwise OR between the read result and the value specified by\r | |
| 494 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 495 | specified by Address. The value written to the PCI configuration register is\r | |
| 496 | returned. This function must guarantee that all PCI read and write operations\r | |
| 497 | are serialized.\r | |
| 498 | \r | |
| 499 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 500 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 501 | \r | |
| 502 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 503 | Register.\r | |
| 504 | @param OrData The value to OR with the PCI configuration register.\r | |
| 505 | \r | |
| 506 | @return The value written back to the PCI configuration register.\r | |
| 507 | \r | |
| 508 | **/\r | |
| 509 | UINT16\r | |
| 510 | EFIAPI\r | |
| 511 | PciOr16 (\r | |
| 512 | IN UINTN Address,\r | |
| 513 | IN UINT16 OrData\r | |
| 514 | )\r | |
| 515 | {\r | |
| 516 | return mRunningOnQ35 ?\r | |
| 517 | PciExpressOr16 (Address, OrData) :\r | |
| 518 | PciCf8Or16 (Address, OrData);\r | |
| 519 | }\r | |
| 520 | \r | |
| 521 | /**\r | |
| 522 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 523 | value.\r | |
| 524 | \r | |
| 525 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 526 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 527 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 528 | Address. The value written to the PCI configuration register is returned.\r | |
| 529 | This function must guarantee that all PCI read and write operations are\r | |
| 530 | serialized.\r | |
| 531 | \r | |
| 532 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 533 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 534 | \r | |
| 535 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 536 | Register.\r | |
| 537 | @param AndData The value to AND with the PCI configuration register.\r | |
| 538 | \r | |
| 539 | @return The value written back to the PCI configuration register.\r | |
| 540 | \r | |
| 541 | **/\r | |
| 542 | UINT16\r | |
| 543 | EFIAPI\r | |
| 544 | PciAnd16 (\r | |
| 545 | IN UINTN Address,\r | |
| 546 | IN UINT16 AndData\r | |
| 547 | )\r | |
| 548 | {\r | |
| 549 | return mRunningOnQ35 ?\r | |
| 550 | PciExpressAnd16 (Address, AndData) :\r | |
| 551 | PciCf8And16 (Address, AndData);\r | |
| 552 | }\r | |
| 553 | \r | |
| 554 | /**\r | |
| 555 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 556 | value, followed a bitwise OR with another 16-bit value.\r | |
| 557 | \r | |
| 558 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 559 | bitwise AND between the read result and the value specified by AndData,\r | |
| 560 | performs a bitwise OR between the result of the AND operation and\r | |
| 561 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
| 562 | configuration register specified by Address. The value written to the PCI\r | |
| 563 | configuration register is returned. This function must guarantee that all PCI\r | |
| 564 | read and write operations are serialized.\r | |
| 565 | \r | |
| 566 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 567 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 568 | \r | |
| 569 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 570 | Register.\r | |
| 571 | @param AndData The value to AND with the PCI configuration register.\r | |
| 572 | @param OrData The value to OR with the result of the AND operation.\r | |
| 573 | \r | |
| 574 | @return The value written back to the PCI configuration register.\r | |
| 575 | \r | |
| 576 | **/\r | |
| 577 | UINT16\r | |
| 578 | EFIAPI\r | |
| 579 | PciAndThenOr16 (\r | |
| 580 | IN UINTN Address,\r | |
| 581 | IN UINT16 AndData,\r | |
| 582 | IN UINT16 OrData\r | |
| 583 | )\r | |
| 584 | {\r | |
| 585 | return mRunningOnQ35 ?\r | |
| 586 | PciExpressAndThenOr16 (Address, AndData, OrData) :\r | |
| 587 | PciCf8AndThenOr16 (Address, AndData, OrData);\r | |
| 588 | }\r | |
| 589 | \r | |
| 590 | /**\r | |
| 591 | Reads a bit field of a PCI configuration register.\r | |
| 592 | \r | |
| 593 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
| 594 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 595 | returned.\r | |
| 596 | \r | |
| 597 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 598 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 599 | If StartBit is greater than 15, then ASSERT().\r | |
| 600 | If EndBit is greater than 15, then ASSERT().\r | |
| 601 | If EndBit is less than StartBit, then ASSERT().\r | |
| 602 | \r | |
| 603 | @param Address The PCI configuration register to read.\r | |
| 604 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 605 | Range 0..15.\r | |
| 606 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 607 | Range 0..15.\r | |
| 608 | \r | |
| 609 | @return The value of the bit field read from the PCI configuration register.\r | |
| 610 | \r | |
| 611 | **/\r | |
| 612 | UINT16\r | |
| 613 | EFIAPI\r | |
| 614 | PciBitFieldRead16 (\r | |
| 615 | IN UINTN Address,\r | |
| 616 | IN UINTN StartBit,\r | |
| 617 | IN UINTN EndBit\r | |
| 618 | )\r | |
| 619 | {\r | |
| 620 | return mRunningOnQ35 ?\r | |
| 621 | PciExpressBitFieldRead16 (Address, StartBit, EndBit) :\r | |
| 622 | PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r | |
| 623 | }\r | |
| 624 | \r | |
| 625 | /**\r | |
| 626 | Writes a bit field to a PCI configuration register.\r | |
| 627 | \r | |
| 628 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 629 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 630 | destination PCI configuration register are preserved. The new value of the\r | |
| 631 | 16-bit register is returned.\r | |
| 632 | \r | |
| 633 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 634 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 635 | If StartBit is greater than 15, then ASSERT().\r | |
| 636 | If EndBit is greater than 15, then ASSERT().\r | |
| 637 | If EndBit is less than StartBit, then ASSERT().\r | |
| 638 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 639 | \r | |
| 640 | @param Address The PCI configuration register to write.\r | |
| 641 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 642 | Range 0..15.\r | |
| 643 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 644 | Range 0..15.\r | |
| 645 | @param Value The new value of the bit field.\r | |
| 646 | \r | |
| 647 | @return The value written back to the PCI configuration register.\r | |
| 648 | \r | |
| 649 | **/\r | |
| 650 | UINT16\r | |
| 651 | EFIAPI\r | |
| 652 | PciBitFieldWrite16 (\r | |
| 653 | IN UINTN Address,\r | |
| 654 | IN UINTN StartBit,\r | |
| 655 | IN UINTN EndBit,\r | |
| 656 | IN UINT16 Value\r | |
| 657 | )\r | |
| 658 | {\r | |
| 659 | return mRunningOnQ35 ?\r | |
| 660 | PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value) :\r | |
| 661 | PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
| 662 | }\r | |
| 663 | \r | |
| 664 | /**\r | |
| 665 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
| 666 | writes the result back to the bit field in the 16-bit port.\r | |
| 667 | \r | |
| 668 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 669 | bitwise OR between the read result and the value specified by\r | |
| 670 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 671 | specified by Address. The value written to the PCI configuration register is\r | |
| 672 | returned. This function must guarantee that all PCI read and write operations\r | |
| 673 | are serialized. Extra left bits in OrData are stripped.\r | |
| 674 | \r | |
| 675 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 676 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 677 | If StartBit is greater than 15, then ASSERT().\r | |
| 678 | If EndBit is greater than 15, then ASSERT().\r | |
| 679 | If EndBit is less than StartBit, then ASSERT().\r | |
| 680 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 681 | \r | |
| 682 | @param Address The PCI configuration register to write.\r | |
| 683 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 684 | Range 0..15.\r | |
| 685 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 686 | Range 0..15.\r | |
| 687 | @param OrData The value to OR with the PCI configuration register.\r | |
| 688 | \r | |
| 689 | @return The value written back to the PCI configuration register.\r | |
| 690 | \r | |
| 691 | **/\r | |
| 692 | UINT16\r | |
| 693 | EFIAPI\r | |
| 694 | PciBitFieldOr16 (\r | |
| 695 | IN UINTN Address,\r | |
| 696 | IN UINTN StartBit,\r | |
| 697 | IN UINTN EndBit,\r | |
| 698 | IN UINT16 OrData\r | |
| 699 | )\r | |
| 700 | {\r | |
| 701 | return mRunningOnQ35 ?\r | |
| 702 | PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData) :\r | |
| 703 | PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
| 704 | }\r | |
| 705 | \r | |
| 706 | /**\r | |
| 707 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
| 708 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
| 709 | \r | |
| 710 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 711 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 712 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 713 | Address. The value written to the PCI configuration register is returned.\r | |
| 714 | This function must guarantee that all PCI read and write operations are\r | |
| 715 | serialized. Extra left bits in AndData are stripped.\r | |
| 716 | \r | |
| 717 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 718 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 719 | If StartBit is greater than 15, then ASSERT().\r | |
| 720 | If EndBit is greater than 15, then ASSERT().\r | |
| 721 | If EndBit is less than StartBit, then ASSERT().\r | |
| 722 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 723 | \r | |
| 724 | @param Address The PCI configuration register to write.\r | |
| 725 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 726 | Range 0..15.\r | |
| 727 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 728 | Range 0..15.\r | |
| 729 | @param AndData The value to AND with the PCI configuration register.\r | |
| 730 | \r | |
| 731 | @return The value written back to the PCI configuration register.\r | |
| 732 | \r | |
| 733 | **/\r | |
| 734 | UINT16\r | |
| 735 | EFIAPI\r | |
| 736 | PciBitFieldAnd16 (\r | |
| 737 | IN UINTN Address,\r | |
| 738 | IN UINTN StartBit,\r | |
| 739 | IN UINTN EndBit,\r | |
| 740 | IN UINT16 AndData\r | |
| 741 | )\r | |
| 742 | {\r | |
| 743 | return mRunningOnQ35 ?\r | |
| 744 | PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData) :\r | |
| 745 | PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
| 746 | }\r | |
| 747 | \r | |
| 748 | /**\r | |
| 749 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
| 750 | bitwise OR, and writes the result back to the bit field in the\r | |
| 751 | 16-bit port.\r | |
| 752 | \r | |
| 753 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 754 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 755 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
| 756 | configuration register specified by Address. The value written to the PCI\r | |
| 757 | configuration register is returned. This function must guarantee that all PCI\r | |
| 758 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 759 | OrData are stripped.\r | |
| 760 | \r | |
| 761 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 762 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 763 | If StartBit is greater than 15, then ASSERT().\r | |
| 764 | If EndBit is greater than 15, then ASSERT().\r | |
| 765 | If EndBit is less than StartBit, then ASSERT().\r | |
| 766 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 767 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 768 | \r | |
| 769 | @param Address The PCI configuration register to write.\r | |
| 770 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 771 | Range 0..15.\r | |
| 772 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 773 | Range 0..15.\r | |
| 774 | @param AndData The value to AND with the PCI configuration register.\r | |
| 775 | @param OrData The value to OR with the result of the AND operation.\r | |
| 776 | \r | |
| 777 | @return The value written back to the PCI configuration register.\r | |
| 778 | \r | |
| 779 | **/\r | |
| 780 | UINT16\r | |
| 781 | EFIAPI\r | |
| 782 | PciBitFieldAndThenOr16 (\r | |
| 783 | IN UINTN Address,\r | |
| 784 | IN UINTN StartBit,\r | |
| 785 | IN UINTN EndBit,\r | |
| 786 | IN UINT16 AndData,\r | |
| 787 | IN UINT16 OrData\r | |
| 788 | )\r | |
| 789 | {\r | |
| 790 | return mRunningOnQ35 ?\r | |
| 791 | PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 792 | PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 793 | }\r | |
| 794 | \r | |
| 795 | /**\r | |
| 796 | Reads a 32-bit PCI configuration register.\r | |
| 797 | \r | |
| 798 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
| 799 | This function must guarantee that all PCI read and write operations are\r | |
| 800 | serialized.\r | |
| 801 | \r | |
| 802 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 803 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 804 | \r | |
| 805 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 806 | Register.\r | |
| 807 | \r | |
| 808 | @return The read value from the PCI configuration register.\r | |
| 809 | \r | |
| 810 | **/\r | |
| 811 | UINT32\r | |
| 812 | EFIAPI\r | |
| 813 | PciRead32 (\r | |
| 814 | IN UINTN Address\r | |
| 815 | )\r | |
| 816 | {\r | |
| 817 | return mRunningOnQ35 ?\r | |
| 818 | PciExpressRead32 (Address) :\r | |
| 819 | PciCf8Read32 (Address);\r | |
| 820 | }\r | |
| 821 | \r | |
| 822 | /**\r | |
| 823 | Writes a 32-bit PCI configuration register.\r | |
| 824 | \r | |
| 825 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
| 826 | value specified by Value. Value is returned. This function must guarantee\r | |
| 827 | that all PCI read and write operations are serialized.\r | |
| 828 | \r | |
| 829 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 830 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 831 | \r | |
| 832 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 833 | Register.\r | |
| 834 | @param Value The value to write.\r | |
| 835 | \r | |
| 836 | @return The value written to the PCI configuration register.\r | |
| 837 | \r | |
| 838 | **/\r | |
| 839 | UINT32\r | |
| 840 | EFIAPI\r | |
| 841 | PciWrite32 (\r | |
| 842 | IN UINTN Address,\r | |
| 843 | IN UINT32 Value\r | |
| 844 | )\r | |
| 845 | {\r | |
| 846 | return mRunningOnQ35 ?\r | |
| 847 | PciExpressWrite32 (Address, Value) :\r | |
| 848 | PciCf8Write32 (Address, Value);\r | |
| 849 | }\r | |
| 850 | \r | |
| 851 | /**\r | |
| 852 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
| 853 | a 32-bit value.\r | |
| 854 | \r | |
| 855 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 856 | bitwise OR between the read result and the value specified by\r | |
| 857 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 858 | specified by Address. The value written to the PCI configuration register is\r | |
| 859 | returned. This function must guarantee that all PCI read and write operations\r | |
| 860 | are serialized.\r | |
| 861 | \r | |
| 862 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 863 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 864 | \r | |
| 865 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 866 | Register.\r | |
| 867 | @param OrData The value to OR with the PCI configuration register.\r | |
| 868 | \r | |
| 869 | @return The value written back to the PCI configuration register.\r | |
| 870 | \r | |
| 871 | **/\r | |
| 872 | UINT32\r | |
| 873 | EFIAPI\r | |
| 874 | PciOr32 (\r | |
| 875 | IN UINTN Address,\r | |
| 876 | IN UINT32 OrData\r | |
| 877 | )\r | |
| 878 | {\r | |
| 879 | return mRunningOnQ35 ?\r | |
| 880 | PciExpressOr32 (Address, OrData) :\r | |
| 881 | PciCf8Or32 (Address, OrData);\r | |
| 882 | }\r | |
| 883 | \r | |
| 884 | /**\r | |
| 885 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 886 | value.\r | |
| 887 | \r | |
| 888 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 889 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 890 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 891 | Address. The value written to the PCI configuration register is returned.\r | |
| 892 | This function must guarantee that all PCI read and write operations are\r | |
| 893 | serialized.\r | |
| 894 | \r | |
| 895 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 896 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 897 | \r | |
| 898 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 899 | Register.\r | |
| 900 | @param AndData The value to AND with the PCI configuration register.\r | |
| 901 | \r | |
| 902 | @return The value written back to the PCI configuration register.\r | |
| 903 | \r | |
| 904 | **/\r | |
| 905 | UINT32\r | |
| 906 | EFIAPI\r | |
| 907 | PciAnd32 (\r | |
| 908 | IN UINTN Address,\r | |
| 909 | IN UINT32 AndData\r | |
| 910 | )\r | |
| 911 | {\r | |
| 912 | return mRunningOnQ35 ?\r | |
| 913 | PciExpressAnd32 (Address, AndData) :\r | |
| 914 | PciCf8And32 (Address, AndData);\r | |
| 915 | }\r | |
| 916 | \r | |
| 917 | /**\r | |
| 918 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 919 | value, followed a bitwise OR with another 32-bit value.\r | |
| 920 | \r | |
| 921 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 922 | bitwise AND between the read result and the value specified by AndData,\r | |
| 923 | performs a bitwise OR between the result of the AND operation and\r | |
| 924 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
| 925 | configuration register specified by Address. The value written to the PCI\r | |
| 926 | configuration register is returned. This function must guarantee that all PCI\r | |
| 927 | read and write operations are serialized.\r | |
| 928 | \r | |
| 929 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 930 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 931 | \r | |
| 932 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 933 | Register.\r | |
| 934 | @param AndData The value to AND with the PCI configuration register.\r | |
| 935 | @param OrData The value to OR with the result of the AND operation.\r | |
| 936 | \r | |
| 937 | @return The value written back to the PCI configuration register.\r | |
| 938 | \r | |
| 939 | **/\r | |
| 940 | UINT32\r | |
| 941 | EFIAPI\r | |
| 942 | PciAndThenOr32 (\r | |
| 943 | IN UINTN Address,\r | |
| 944 | IN UINT32 AndData,\r | |
| 945 | IN UINT32 OrData\r | |
| 946 | )\r | |
| 947 | {\r | |
| 948 | return mRunningOnQ35 ?\r | |
| 949 | PciExpressAndThenOr32 (Address, AndData, OrData) :\r | |
| 950 | PciCf8AndThenOr32 (Address, AndData, OrData);\r | |
| 951 | }\r | |
| 952 | \r | |
| 953 | /**\r | |
| 954 | Reads a bit field of a PCI configuration register.\r | |
| 955 | \r | |
| 956 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
| 957 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 958 | returned.\r | |
| 959 | \r | |
| 960 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 961 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 962 | If StartBit is greater than 31, then ASSERT().\r | |
| 963 | If EndBit is greater than 31, then ASSERT().\r | |
| 964 | If EndBit is less than StartBit, then ASSERT().\r | |
| 965 | \r | |
| 966 | @param Address The PCI configuration register to read.\r | |
| 967 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 968 | Range 0..31.\r | |
| 969 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 970 | Range 0..31.\r | |
| 971 | \r | |
| 972 | @return The value of the bit field read from the PCI configuration register.\r | |
| 973 | \r | |
| 974 | **/\r | |
| 975 | UINT32\r | |
| 976 | EFIAPI\r | |
| 977 | PciBitFieldRead32 (\r | |
| 978 | IN UINTN Address,\r | |
| 979 | IN UINTN StartBit,\r | |
| 980 | IN UINTN EndBit\r | |
| 981 | )\r | |
| 982 | {\r | |
| 983 | return mRunningOnQ35 ?\r | |
| 984 | PciExpressBitFieldRead32 (Address, StartBit, EndBit) :\r | |
| 985 | PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r | |
| 986 | }\r | |
| 987 | \r | |
| 988 | /**\r | |
| 989 | Writes a bit field to a PCI configuration register.\r | |
| 990 | \r | |
| 991 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 992 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 993 | destination PCI configuration register are preserved. The new value of the\r | |
| 994 | 32-bit register is returned.\r | |
| 995 | \r | |
| 996 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 997 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 998 | If StartBit is greater than 31, then ASSERT().\r | |
| 999 | If EndBit is greater than 31, then ASSERT().\r | |
| 1000 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1001 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1002 | \r | |
| 1003 | @param Address The PCI configuration register to write.\r | |
| 1004 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1005 | Range 0..31.\r | |
| 1006 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1007 | Range 0..31.\r | |
| 1008 | @param Value The new value of the bit field.\r | |
| 1009 | \r | |
| 1010 | @return The value written back to the PCI configuration register.\r | |
| 1011 | \r | |
| 1012 | **/\r | |
| 1013 | UINT32\r | |
| 1014 | EFIAPI\r | |
| 1015 | PciBitFieldWrite32 (\r | |
| 1016 | IN UINTN Address,\r | |
| 1017 | IN UINTN StartBit,\r | |
| 1018 | IN UINTN EndBit,\r | |
| 1019 | IN UINT32 Value\r | |
| 1020 | )\r | |
| 1021 | {\r | |
| 1022 | return mRunningOnQ35 ?\r | |
| 1023 | PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value) :\r | |
| 1024 | PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
| 1025 | }\r | |
| 1026 | \r | |
| 1027 | /**\r | |
| 1028 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
| 1029 | writes the result back to the bit field in the 32-bit port.\r | |
| 1030 | \r | |
| 1031 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1032 | bitwise OR between the read result and the value specified by\r | |
| 1033 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 1034 | specified by Address. The value written to the PCI configuration register is\r | |
| 1035 | returned. This function must guarantee that all PCI read and write operations\r | |
| 1036 | are serialized. Extra left bits in OrData are stripped.\r | |
| 1037 | \r | |
| 1038 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1039 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1040 | If StartBit is greater than 31, then ASSERT().\r | |
| 1041 | If EndBit is greater than 31, then ASSERT().\r | |
| 1042 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1043 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1044 | \r | |
| 1045 | @param Address The PCI configuration register to write.\r | |
| 1046 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1047 | Range 0..31.\r | |
| 1048 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1049 | Range 0..31.\r | |
| 1050 | @param OrData The value to OR with the PCI configuration register.\r | |
| 1051 | \r | |
| 1052 | @return The value written back to the PCI configuration register.\r | |
| 1053 | \r | |
| 1054 | **/\r | |
| 1055 | UINT32\r | |
| 1056 | EFIAPI\r | |
| 1057 | PciBitFieldOr32 (\r | |
| 1058 | IN UINTN Address,\r | |
| 1059 | IN UINTN StartBit,\r | |
| 1060 | IN UINTN EndBit,\r | |
| 1061 | IN UINT32 OrData\r | |
| 1062 | )\r | |
| 1063 | {\r | |
| 1064 | return mRunningOnQ35 ?\r | |
| 1065 | PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData) :\r | |
| 1066 | PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
| 1067 | }\r | |
| 1068 | \r | |
| 1069 | /**\r | |
| 1070 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
| 1071 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
| 1072 | \r | |
| 1073 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1074 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 1075 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 1076 | Address. The value written to the PCI configuration register is returned.\r | |
| 1077 | This function must guarantee that all PCI read and write operations are\r | |
| 1078 | serialized. Extra left bits in AndData are stripped.\r | |
| 1079 | \r | |
| 1080 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1081 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1082 | If StartBit is greater than 31, then ASSERT().\r | |
| 1083 | If EndBit is greater than 31, then ASSERT().\r | |
| 1084 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1085 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1086 | \r | |
| 1087 | @param Address The PCI configuration register to write.\r | |
| 1088 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1089 | Range 0..31.\r | |
| 1090 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1091 | Range 0..31.\r | |
| 1092 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1093 | \r | |
| 1094 | @return The value written back to the PCI configuration register.\r | |
| 1095 | \r | |
| 1096 | **/\r | |
| 1097 | UINT32\r | |
| 1098 | EFIAPI\r | |
| 1099 | PciBitFieldAnd32 (\r | |
| 1100 | IN UINTN Address,\r | |
| 1101 | IN UINTN StartBit,\r | |
| 1102 | IN UINTN EndBit,\r | |
| 1103 | IN UINT32 AndData\r | |
| 1104 | )\r | |
| 1105 | {\r | |
| 1106 | return mRunningOnQ35 ?\r | |
| 1107 | PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData) :\r | |
| 1108 | PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
| 1109 | }\r | |
| 1110 | \r | |
| 1111 | /**\r | |
| 1112 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
| 1113 | bitwise OR, and writes the result back to the bit field in the\r | |
| 1114 | 32-bit port.\r | |
| 1115 | \r | |
| 1116 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1117 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 1118 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
| 1119 | configuration register specified by Address. The value written to the PCI\r | |
| 1120 | configuration register is returned. This function must guarantee that all PCI\r | |
| 1121 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 1122 | OrData are stripped.\r | |
| 1123 | \r | |
| 1124 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1125 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1126 | If StartBit is greater than 31, then ASSERT().\r | |
| 1127 | If EndBit is greater than 31, then ASSERT().\r | |
| 1128 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1129 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1130 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1131 | \r | |
| 1132 | @param Address The PCI configuration register to write.\r | |
| 1133 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1134 | Range 0..31.\r | |
| 1135 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1136 | Range 0..31.\r | |
| 1137 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1138 | @param OrData The value to OR with the result of the AND operation.\r | |
| 1139 | \r | |
| 1140 | @return The value written back to the PCI configuration register.\r | |
| 1141 | \r | |
| 1142 | **/\r | |
| 1143 | UINT32\r | |
| 1144 | EFIAPI\r | |
| 1145 | PciBitFieldAndThenOr32 (\r | |
| 1146 | IN UINTN Address,\r | |
| 1147 | IN UINTN StartBit,\r | |
| 1148 | IN UINTN EndBit,\r | |
| 1149 | IN UINT32 AndData,\r | |
| 1150 | IN UINT32 OrData\r | |
| 1151 | )\r | |
| 1152 | {\r | |
| 1153 | return mRunningOnQ35 ?\r | |
| 1154 | PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 1155 | PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 1156 | }\r | |
| 1157 | \r | |
| 1158 | /**\r | |
| 1159 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
| 1160 | \r | |
| 1161 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
| 1162 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
| 1163 | configuration registers from a single PCI function to be read. Size is\r | |
| 1164 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
| 1165 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
| 1166 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
| 1167 | end of the range.\r | |
| 1168 | \r | |
| 1169 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1170 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1171 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1172 | \r | |
| 1173 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1174 | Function and Register.\r | |
| 1175 | @param Size The size in bytes of the transfer.\r | |
| 1176 | @param Buffer The pointer to a buffer receiving the data read.\r | |
| 1177 | \r | |
| 1178 | @return Size\r | |
| 1179 | \r | |
| 1180 | **/\r | |
| 1181 | UINTN\r | |
| 1182 | EFIAPI\r | |
| 1183 | PciReadBuffer (\r | |
| 1184 | IN UINTN StartAddress,\r | |
| 1185 | IN UINTN Size,\r | |
| 1186 | OUT VOID *Buffer\r | |
| 1187 | )\r | |
| 1188 | {\r | |
| 1189 | return mRunningOnQ35 ?\r | |
| 1190 | PciExpressReadBuffer (StartAddress, Size, Buffer) :\r | |
| 1191 | PciCf8ReadBuffer (StartAddress, Size, Buffer);\r | |
| 1192 | }\r | |
| 1193 | \r | |
| 1194 | /**\r | |
| 1195 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
| 1196 | configuration space.\r | |
| 1197 | \r | |
| 1198 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
| 1199 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
| 1200 | configuration registers from a single PCI function to be written. Size is\r | |
| 1201 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
| 1202 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
| 1203 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
| 1204 | and the end of the range.\r | |
| 1205 | \r | |
| 1206 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1207 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1208 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1209 | \r | |
| 1210 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1211 | Function and Register.\r | |
| 1212 | @param Size The size in bytes of the transfer.\r | |
| 1213 | @param Buffer The pointer to a buffer containing the data to write.\r | |
| 1214 | \r | |
| 1215 | @return Size written to StartAddress.\r | |
| 1216 | \r | |
| 1217 | **/\r | |
| 1218 | UINTN\r | |
| 1219 | EFIAPI\r | |
| 1220 | PciWriteBuffer (\r | |
| 1221 | IN UINTN StartAddress,\r | |
| 1222 | IN UINTN Size,\r | |
| 1223 | IN VOID *Buffer\r | |
| 1224 | )\r | |
| 1225 | {\r | |
| 1226 | return mRunningOnQ35 ?\r | |
| 1227 | PciExpressWriteBuffer (StartAddress, Size, Buffer) :\r | |
| 1228 | PciCf8WriteBuffer (StartAddress, Size, Buffer);\r | |
| 1229 | }\r |