projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 7523788f LE |
1 | /** @file\r |
| 2 | PCI Library functions that use\r | |
| 3 | (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering\r | |
| 4 | on top of one PCI CF8 Library instance; or\r | |
| 5 | (b) PCI Library functions that use the 256 MB PCI Express MMIO window to\r | |
| 6 | perform PCI Configuration cycles, layering on PCI Express Library.\r | |
| 7 | \r | |
| 8 | The decision is made in the entry point function, based on the OVMF platform\r | |
| 9 | type, and then adhered to during the lifetime of the client module.\r | |
| 10 | \r | |
| 11 | Copyright (C) 2016, Red Hat, Inc.\r | |
| 12 | \r | |
| 13 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
| b26f0cf9 | 14 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 7523788f LE |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 7523788f LE |
18 | #include <Base.h>\r |
| 19 | \r | |
| 20 | #include <IndustryStandard/Q35MchIch9.h>\r | |
| 21 | \r | |
| 22 | #include <Library/PciLib.h>\r | |
| 23 | #include <Library/PciCf8Lib.h>\r | |
| 24 | #include <Library/PciExpressLib.h>\r | |
| 25 | #include <Library/PcdLib.h>\r | |
| 26 | \r | |
| ac0a286f | 27 | STATIC BOOLEAN mRunningOnQ35;\r |
| 7523788f LE |
28 | \r |
| 29 | RETURN_STATUS\r | |
| 30 | EFIAPI\r | |
| 31 | InitializeConfigAccessMethod (\r | |
| 32 | VOID\r | |
| 33 | )\r | |
| 34 | {\r | |
| 35 | mRunningOnQ35 = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==\r | |
| 36 | INTEL_Q35_MCH_DEVICE_ID);\r | |
| 37 | return RETURN_SUCCESS;\r | |
| 38 | }\r | |
| 39 | \r | |
| 40 | /**\r | |
| 4040754d | 41 | Registers a PCI device so PCI configuration registers may be accessed after\r |
| 7523788f | 42 | SetVirtualAddressMap().\r |
| 4040754d LL |
43 | \r |
| 44 | Registers the PCI device specified by Address so all the PCI configuration registers\r | |
| 7523788f | 45 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r |
| 4040754d | 46 | \r |
| 7523788f LE |
47 | If Address > 0x0FFFFFFF, then ASSERT().\r |
| 48 | \r | |
| 49 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 50 | Register.\r | |
| 4040754d | 51 | \r |
| 7523788f | 52 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r |
| 4040754d | 53 | @retval RETURN_UNSUPPORTED An attempt was made to call this function\r |
| 7523788f LE |
54 | after ExitBootServices().\r |
| 55 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
| 56 | at runtime could not be mapped.\r | |
| 57 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
| 58 | complete the registration.\r | |
| 59 | \r | |
| 60 | **/\r | |
| 61 | RETURN_STATUS\r | |
| 62 | EFIAPI\r | |
| 63 | PciRegisterForRuntimeAccess (\r | |
| 64 | IN UINTN Address\r | |
| 65 | )\r | |
| 66 | {\r | |
| 67 | return mRunningOnQ35 ?\r | |
| 68 | PciExpressRegisterForRuntimeAccess (Address) :\r | |
| 69 | PciCf8RegisterForRuntimeAccess (Address);\r | |
| 70 | }\r | |
| 71 | \r | |
| 72 | /**\r | |
| 73 | Reads an 8-bit PCI configuration register.\r | |
| 74 | \r | |
| 75 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
| 76 | This function must guarantee that all PCI read and write operations are\r | |
| 77 | serialized.\r | |
| 78 | \r | |
| 79 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 80 | \r | |
| 81 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 82 | Register.\r | |
| 83 | \r | |
| 84 | @return The read value from the PCI configuration register.\r | |
| 85 | \r | |
| 86 | **/\r | |
| 87 | UINT8\r | |
| 88 | EFIAPI\r | |
| 89 | PciRead8 (\r | |
| ac0a286f | 90 | IN UINTN Address\r |
| 7523788f LE |
91 | )\r |
| 92 | {\r | |
| 93 | return mRunningOnQ35 ?\r | |
| 94 | PciExpressRead8 (Address) :\r | |
| 95 | PciCf8Read8 (Address);\r | |
| 96 | }\r | |
| 97 | \r | |
| 98 | /**\r | |
| 99 | Writes an 8-bit PCI configuration register.\r | |
| 100 | \r | |
| 101 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
| 102 | value specified by Value. Value is returned. This function must guarantee\r | |
| 103 | that all PCI read and write operations are serialized.\r | |
| 104 | \r | |
| 105 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 106 | \r | |
| 107 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 108 | Register.\r | |
| 109 | @param Value The value to write.\r | |
| 110 | \r | |
| 111 | @return The value written to the PCI configuration register.\r | |
| 112 | \r | |
| 113 | **/\r | |
| 114 | UINT8\r | |
| 115 | EFIAPI\r | |
| 116 | PciWrite8 (\r | |
| ac0a286f MK |
117 | IN UINTN Address,\r |
| 118 | IN UINT8 Value\r | |
| 7523788f LE |
119 | )\r |
| 120 | {\r | |
| 121 | return mRunningOnQ35 ?\r | |
| 122 | PciExpressWrite8 (Address, Value) :\r | |
| 123 | PciCf8Write8 (Address, Value);\r | |
| 124 | }\r | |
| 125 | \r | |
| 126 | /**\r | |
| 127 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
| 128 | an 8-bit value.\r | |
| 129 | \r | |
| 130 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 131 | bitwise OR between the read result and the value specified by\r | |
| 132 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 133 | specified by Address. The value written to the PCI configuration register is\r | |
| 134 | returned. This function must guarantee that all PCI read and write operations\r | |
| 135 | are serialized.\r | |
| 136 | \r | |
| 137 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 138 | \r | |
| 139 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 140 | Register.\r | |
| 141 | @param OrData The value to OR with the PCI configuration register.\r | |
| 142 | \r | |
| 143 | @return The value written back to the PCI configuration register.\r | |
| 144 | \r | |
| 145 | **/\r | |
| 146 | UINT8\r | |
| 147 | EFIAPI\r | |
| 148 | PciOr8 (\r | |
| ac0a286f MK |
149 | IN UINTN Address,\r |
| 150 | IN UINT8 OrData\r | |
| 7523788f LE |
151 | )\r |
| 152 | {\r | |
| 153 | return mRunningOnQ35 ?\r | |
| 154 | PciExpressOr8 (Address, OrData) :\r | |
| 155 | PciCf8Or8 (Address, OrData);\r | |
| 156 | }\r | |
| 157 | \r | |
| 158 | /**\r | |
| 159 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 160 | value.\r | |
| 161 | \r | |
| 162 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 163 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 164 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 165 | Address. The value written to the PCI configuration register is returned.\r | |
| 166 | This function must guarantee that all PCI read and write operations are\r | |
| 167 | serialized.\r | |
| 168 | \r | |
| 169 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 170 | \r | |
| 171 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 172 | Register.\r | |
| 173 | @param AndData The value to AND with the PCI configuration register.\r | |
| 174 | \r | |
| 175 | @return The value written back to the PCI configuration register.\r | |
| 176 | \r | |
| 177 | **/\r | |
| 178 | UINT8\r | |
| 179 | EFIAPI\r | |
| 180 | PciAnd8 (\r | |
| ac0a286f MK |
181 | IN UINTN Address,\r |
| 182 | IN UINT8 AndData\r | |
| 7523788f LE |
183 | )\r |
| 184 | {\r | |
| 185 | return mRunningOnQ35 ?\r | |
| 186 | PciExpressAnd8 (Address, AndData) :\r | |
| 187 | PciCf8And8 (Address, AndData);\r | |
| 188 | }\r | |
| 189 | \r | |
| 190 | /**\r | |
| 191 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 192 | value, followed a bitwise OR with another 8-bit value.\r | |
| 193 | \r | |
| 194 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 195 | bitwise AND between the read result and the value specified by AndData,\r | |
| 196 | performs a bitwise OR between the result of the AND operation and\r | |
| 197 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
| 198 | configuration register specified by Address. The value written to the PCI\r | |
| 199 | configuration register is returned. This function must guarantee that all PCI\r | |
| 200 | read and write operations are serialized.\r | |
| 201 | \r | |
| 202 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 203 | \r | |
| 204 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 205 | Register.\r | |
| 206 | @param AndData The value to AND with the PCI configuration register.\r | |
| 207 | @param OrData The value to OR with the result of the AND operation.\r | |
| 208 | \r | |
| 209 | @return The value written back to the PCI configuration register.\r | |
| 210 | \r | |
| 211 | **/\r | |
| 212 | UINT8\r | |
| 213 | EFIAPI\r | |
| 214 | PciAndThenOr8 (\r | |
| ac0a286f MK |
215 | IN UINTN Address,\r |
| 216 | IN UINT8 AndData,\r | |
| 217 | IN UINT8 OrData\r | |
| 7523788f LE |
218 | )\r |
| 219 | {\r | |
| 220 | return mRunningOnQ35 ?\r | |
| 221 | PciExpressAndThenOr8 (Address, AndData, OrData) :\r | |
| 222 | PciCf8AndThenOr8 (Address, AndData, OrData);\r | |
| 223 | }\r | |
| 224 | \r | |
| 225 | /**\r | |
| 226 | Reads a bit field of a PCI configuration register.\r | |
| 227 | \r | |
| 228 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
| 229 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 230 | returned.\r | |
| 231 | \r | |
| 232 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 233 | If StartBit is greater than 7, then ASSERT().\r | |
| 234 | If EndBit is greater than 7, then ASSERT().\r | |
| 235 | If EndBit is less than StartBit, then ASSERT().\r | |
| 236 | \r | |
| 237 | @param Address The PCI configuration register to read.\r | |
| 238 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 239 | Range 0..7.\r | |
| 240 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 241 | Range 0..7.\r | |
| 242 | \r | |
| 243 | @return The value of the bit field read from the PCI configuration register.\r | |
| 244 | \r | |
| 245 | **/\r | |
| 246 | UINT8\r | |
| 247 | EFIAPI\r | |
| 248 | PciBitFieldRead8 (\r | |
| ac0a286f MK |
249 | IN UINTN Address,\r |
| 250 | IN UINTN StartBit,\r | |
| 251 | IN UINTN EndBit\r | |
| 7523788f LE |
252 | )\r |
| 253 | {\r | |
| 254 | return mRunningOnQ35 ?\r | |
| 255 | PciExpressBitFieldRead8 (Address, StartBit, EndBit) :\r | |
| 256 | PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r | |
| 257 | }\r | |
| 258 | \r | |
| 259 | /**\r | |
| 260 | Writes a bit field to a PCI configuration register.\r | |
| 261 | \r | |
| 262 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 263 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 264 | destination PCI configuration register are preserved. The new value of the\r | |
| 265 | 8-bit register is returned.\r | |
| 266 | \r | |
| 267 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 268 | If StartBit is greater than 7, then ASSERT().\r | |
| 269 | If EndBit is greater than 7, then ASSERT().\r | |
| 270 | If EndBit is less than StartBit, then ASSERT().\r | |
| 271 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 272 | \r | |
| 273 | @param Address The PCI configuration register to write.\r | |
| 274 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 275 | Range 0..7.\r | |
| 276 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 277 | Range 0..7.\r | |
| 278 | @param Value The new value of the bit field.\r | |
| 279 | \r | |
| 280 | @return The value written back to the PCI configuration register.\r | |
| 281 | \r | |
| 282 | **/\r | |
| 283 | UINT8\r | |
| 284 | EFIAPI\r | |
| 285 | PciBitFieldWrite8 (\r | |
| ac0a286f MK |
286 | IN UINTN Address,\r |
| 287 | IN UINTN StartBit,\r | |
| 288 | IN UINTN EndBit,\r | |
| 289 | IN UINT8 Value\r | |
| 7523788f LE |
290 | )\r |
| 291 | {\r | |
| 292 | return mRunningOnQ35 ?\r | |
| 293 | PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value) :\r | |
| 294 | PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
| 295 | }\r | |
| 296 | \r | |
| 297 | /**\r | |
| 298 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
| 299 | writes the result back to the bit field in the 8-bit port.\r | |
| 300 | \r | |
| 301 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 302 | bitwise OR between the read result and the value specified by\r | |
| 303 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 304 | specified by Address. The value written to the PCI configuration register is\r | |
| 305 | returned. This function must guarantee that all PCI read and write operations\r | |
| 306 | are serialized. Extra left bits in OrData are stripped.\r | |
| 307 | \r | |
| 308 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 309 | If StartBit is greater than 7, then ASSERT().\r | |
| 310 | If EndBit is greater than 7, then ASSERT().\r | |
| 311 | If EndBit is less than StartBit, then ASSERT().\r | |
| 312 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 313 | \r | |
| 314 | @param Address The PCI configuration register to write.\r | |
| 315 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 316 | Range 0..7.\r | |
| 317 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 318 | Range 0..7.\r | |
| 319 | @param OrData The value to OR with the PCI configuration register.\r | |
| 320 | \r | |
| 321 | @return The value written back to the PCI configuration register.\r | |
| 322 | \r | |
| 323 | **/\r | |
| 324 | UINT8\r | |
| 325 | EFIAPI\r | |
| 326 | PciBitFieldOr8 (\r | |
| ac0a286f MK |
327 | IN UINTN Address,\r |
| 328 | IN UINTN StartBit,\r | |
| 329 | IN UINTN EndBit,\r | |
| 330 | IN UINT8 OrData\r | |
| 7523788f LE |
331 | )\r |
| 332 | {\r | |
| 333 | return mRunningOnQ35 ?\r | |
| 334 | PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData) :\r | |
| 335 | PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
| 336 | }\r | |
| 337 | \r | |
| 338 | /**\r | |
| 339 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
| 340 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
| 341 | \r | |
| 342 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 343 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 344 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 345 | Address. The value written to the PCI configuration register is returned.\r | |
| 346 | This function must guarantee that all PCI read and write operations are\r | |
| 347 | serialized. Extra left bits in AndData are stripped.\r | |
| 348 | \r | |
| 349 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 350 | If StartBit is greater than 7, then ASSERT().\r | |
| 351 | If EndBit is greater than 7, then ASSERT().\r | |
| 352 | If EndBit is less than StartBit, then ASSERT().\r | |
| 353 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 354 | \r | |
| 355 | @param Address The PCI configuration register to write.\r | |
| 356 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 357 | Range 0..7.\r | |
| 358 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 359 | Range 0..7.\r | |
| 360 | @param AndData The value to AND with the PCI configuration register.\r | |
| 361 | \r | |
| 362 | @return The value written back to the PCI configuration register.\r | |
| 363 | \r | |
| 364 | **/\r | |
| 365 | UINT8\r | |
| 366 | EFIAPI\r | |
| 367 | PciBitFieldAnd8 (\r | |
| ac0a286f MK |
368 | IN UINTN Address,\r |
| 369 | IN UINTN StartBit,\r | |
| 370 | IN UINTN EndBit,\r | |
| 371 | IN UINT8 AndData\r | |
| 7523788f LE |
372 | )\r |
| 373 | {\r | |
| 374 | return mRunningOnQ35 ?\r | |
| 375 | PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData) :\r | |
| 376 | PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
| 377 | }\r | |
| 378 | \r | |
| 379 | /**\r | |
| 380 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
| 381 | bitwise OR, and writes the result back to the bit field in the\r | |
| 382 | 8-bit port.\r | |
| 383 | \r | |
| 384 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 385 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 386 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
| 387 | configuration register specified by Address. The value written to the PCI\r | |
| 388 | configuration register is returned. This function must guarantee that all PCI\r | |
| 389 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 390 | OrData are stripped.\r | |
| 391 | \r | |
| 392 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 393 | If StartBit is greater than 7, then ASSERT().\r | |
| 394 | If EndBit is greater than 7, then ASSERT().\r | |
| 395 | If EndBit is less than StartBit, then ASSERT().\r | |
| 396 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 397 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 398 | \r | |
| 399 | @param Address The PCI configuration register to write.\r | |
| 400 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 401 | Range 0..7.\r | |
| 402 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 403 | Range 0..7.\r | |
| 404 | @param AndData The value to AND with the PCI configuration register.\r | |
| 405 | @param OrData The value to OR with the result of the AND operation.\r | |
| 406 | \r | |
| 407 | @return The value written back to the PCI configuration register.\r | |
| 408 | \r | |
| 409 | **/\r | |
| 410 | UINT8\r | |
| 411 | EFIAPI\r | |
| 412 | PciBitFieldAndThenOr8 (\r | |
| ac0a286f MK |
413 | IN UINTN Address,\r |
| 414 | IN UINTN StartBit,\r | |
| 415 | IN UINTN EndBit,\r | |
| 416 | IN UINT8 AndData,\r | |
| 417 | IN UINT8 OrData\r | |
| 7523788f LE |
418 | )\r |
| 419 | {\r | |
| 420 | return mRunningOnQ35 ?\r | |
| 421 | PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 422 | PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 423 | }\r | |
| 424 | \r | |
| 425 | /**\r | |
| 426 | Reads a 16-bit PCI configuration register.\r | |
| 427 | \r | |
| 428 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
| 429 | This function must guarantee that all PCI read and write operations are\r | |
| 430 | serialized.\r | |
| 431 | \r | |
| 432 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 433 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 434 | \r | |
| 435 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 436 | Register.\r | |
| 437 | \r | |
| 438 | @return The read value from the PCI configuration register.\r | |
| 439 | \r | |
| 440 | **/\r | |
| 441 | UINT16\r | |
| 442 | EFIAPI\r | |
| 443 | PciRead16 (\r | |
| ac0a286f | 444 | IN UINTN Address\r |
| 7523788f LE |
445 | )\r |
| 446 | {\r | |
| 447 | return mRunningOnQ35 ?\r | |
| 448 | PciExpressRead16 (Address) :\r | |
| 449 | PciCf8Read16 (Address);\r | |
| 450 | }\r | |
| 451 | \r | |
| 452 | /**\r | |
| 453 | Writes a 16-bit PCI configuration register.\r | |
| 454 | \r | |
| 455 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
| 456 | value specified by Value. Value is returned. This function must guarantee\r | |
| 457 | that all PCI read and write operations are serialized.\r | |
| 458 | \r | |
| 459 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 460 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 461 | \r | |
| 462 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 463 | Register.\r | |
| 464 | @param Value The value to write.\r | |
| 465 | \r | |
| 466 | @return The value written to the PCI configuration register.\r | |
| 467 | \r | |
| 468 | **/\r | |
| 469 | UINT16\r | |
| 470 | EFIAPI\r | |
| 471 | PciWrite16 (\r | |
| ac0a286f MK |
472 | IN UINTN Address,\r |
| 473 | IN UINT16 Value\r | |
| 7523788f LE |
474 | )\r |
| 475 | {\r | |
| 476 | return mRunningOnQ35 ?\r | |
| 477 | PciExpressWrite16 (Address, Value) :\r | |
| 478 | PciCf8Write16 (Address, Value);\r | |
| 479 | }\r | |
| 480 | \r | |
| 481 | /**\r | |
| 482 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
| 483 | a 16-bit value.\r | |
| 484 | \r | |
| 485 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 486 | bitwise OR between the read result and the value specified by\r | |
| 487 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 488 | specified by Address. The value written to the PCI configuration register is\r | |
| 489 | returned. This function must guarantee that all PCI read and write operations\r | |
| 490 | are serialized.\r | |
| 491 | \r | |
| 492 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 493 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 494 | \r | |
| 495 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 496 | Register.\r | |
| 497 | @param OrData The value to OR with the PCI configuration register.\r | |
| 498 | \r | |
| 499 | @return The value written back to the PCI configuration register.\r | |
| 500 | \r | |
| 501 | **/\r | |
| 502 | UINT16\r | |
| 503 | EFIAPI\r | |
| 504 | PciOr16 (\r | |
| ac0a286f MK |
505 | IN UINTN Address,\r |
| 506 | IN UINT16 OrData\r | |
| 7523788f LE |
507 | )\r |
| 508 | {\r | |
| 509 | return mRunningOnQ35 ?\r | |
| 510 | PciExpressOr16 (Address, OrData) :\r | |
| 511 | PciCf8Or16 (Address, OrData);\r | |
| 512 | }\r | |
| 513 | \r | |
| 514 | /**\r | |
| 515 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 516 | value.\r | |
| 517 | \r | |
| 518 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 519 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 520 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 521 | Address. The value written to the PCI configuration register is returned.\r | |
| 522 | This function must guarantee that all PCI read and write operations are\r | |
| 523 | serialized.\r | |
| 524 | \r | |
| 525 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 526 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 527 | \r | |
| 528 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 529 | Register.\r | |
| 530 | @param AndData The value to AND with the PCI configuration register.\r | |
| 531 | \r | |
| 532 | @return The value written back to the PCI configuration register.\r | |
| 533 | \r | |
| 534 | **/\r | |
| 535 | UINT16\r | |
| 536 | EFIAPI\r | |
| 537 | PciAnd16 (\r | |
| ac0a286f MK |
538 | IN UINTN Address,\r |
| 539 | IN UINT16 AndData\r | |
| 7523788f LE |
540 | )\r |
| 541 | {\r | |
| 542 | return mRunningOnQ35 ?\r | |
| 543 | PciExpressAnd16 (Address, AndData) :\r | |
| 544 | PciCf8And16 (Address, AndData);\r | |
| 545 | }\r | |
| 546 | \r | |
| 547 | /**\r | |
| 548 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 549 | value, followed a bitwise OR with another 16-bit value.\r | |
| 550 | \r | |
| 551 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 552 | bitwise AND between the read result and the value specified by AndData,\r | |
| 553 | performs a bitwise OR between the result of the AND operation and\r | |
| 554 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
| 555 | configuration register specified by Address. The value written to the PCI\r | |
| 556 | configuration register is returned. This function must guarantee that all PCI\r | |
| 557 | read and write operations are serialized.\r | |
| 558 | \r | |
| 559 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 560 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 561 | \r | |
| 562 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 563 | Register.\r | |
| 564 | @param AndData The value to AND with the PCI configuration register.\r | |
| 565 | @param OrData The value to OR with the result of the AND operation.\r | |
| 566 | \r | |
| 567 | @return The value written back to the PCI configuration register.\r | |
| 568 | \r | |
| 569 | **/\r | |
| 570 | UINT16\r | |
| 571 | EFIAPI\r | |
| 572 | PciAndThenOr16 (\r | |
| ac0a286f MK |
573 | IN UINTN Address,\r |
| 574 | IN UINT16 AndData,\r | |
| 575 | IN UINT16 OrData\r | |
| 7523788f LE |
576 | )\r |
| 577 | {\r | |
| 578 | return mRunningOnQ35 ?\r | |
| 579 | PciExpressAndThenOr16 (Address, AndData, OrData) :\r | |
| 580 | PciCf8AndThenOr16 (Address, AndData, OrData);\r | |
| 581 | }\r | |
| 582 | \r | |
| 583 | /**\r | |
| 584 | Reads a bit field of a PCI configuration register.\r | |
| 585 | \r | |
| 586 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
| 587 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 588 | returned.\r | |
| 589 | \r | |
| 590 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 591 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 592 | If StartBit is greater than 15, then ASSERT().\r | |
| 593 | If EndBit is greater than 15, then ASSERT().\r | |
| 594 | If EndBit is less than StartBit, then ASSERT().\r | |
| 595 | \r | |
| 596 | @param Address The PCI configuration register to read.\r | |
| 597 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 598 | Range 0..15.\r | |
| 599 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 600 | Range 0..15.\r | |
| 601 | \r | |
| 602 | @return The value of the bit field read from the PCI configuration register.\r | |
| 603 | \r | |
| 604 | **/\r | |
| 605 | UINT16\r | |
| 606 | EFIAPI\r | |
| 607 | PciBitFieldRead16 (\r | |
| ac0a286f MK |
608 | IN UINTN Address,\r |
| 609 | IN UINTN StartBit,\r | |
| 610 | IN UINTN EndBit\r | |
| 7523788f LE |
611 | )\r |
| 612 | {\r | |
| 613 | return mRunningOnQ35 ?\r | |
| 614 | PciExpressBitFieldRead16 (Address, StartBit, EndBit) :\r | |
| 615 | PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r | |
| 616 | }\r | |
| 617 | \r | |
| 618 | /**\r | |
| 619 | Writes a bit field to a PCI configuration register.\r | |
| 620 | \r | |
| 621 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 622 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 623 | destination PCI configuration register are preserved. The new value of the\r | |
| 624 | 16-bit register is returned.\r | |
| 625 | \r | |
| 626 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 627 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 628 | If StartBit is greater than 15, then ASSERT().\r | |
| 629 | If EndBit is greater than 15, then ASSERT().\r | |
| 630 | If EndBit is less than StartBit, then ASSERT().\r | |
| 631 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 632 | \r | |
| 633 | @param Address The PCI configuration register to write.\r | |
| 634 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 635 | Range 0..15.\r | |
| 636 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 637 | Range 0..15.\r | |
| 638 | @param Value The new value of the bit field.\r | |
| 639 | \r | |
| 640 | @return The value written back to the PCI configuration register.\r | |
| 641 | \r | |
| 642 | **/\r | |
| 643 | UINT16\r | |
| 644 | EFIAPI\r | |
| 645 | PciBitFieldWrite16 (\r | |
| ac0a286f MK |
646 | IN UINTN Address,\r |
| 647 | IN UINTN StartBit,\r | |
| 648 | IN UINTN EndBit,\r | |
| 649 | IN UINT16 Value\r | |
| 7523788f LE |
650 | )\r |
| 651 | {\r | |
| 652 | return mRunningOnQ35 ?\r | |
| 653 | PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value) :\r | |
| 654 | PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
| 655 | }\r | |
| 656 | \r | |
| 657 | /**\r | |
| 658 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
| 659 | writes the result back to the bit field in the 16-bit port.\r | |
| 660 | \r | |
| 661 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 662 | bitwise OR between the read result and the value specified by\r | |
| 663 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 664 | specified by Address. The value written to the PCI configuration register is\r | |
| 665 | returned. This function must guarantee that all PCI read and write operations\r | |
| 666 | are serialized. Extra left bits in OrData are stripped.\r | |
| 667 | \r | |
| 668 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 669 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 670 | If StartBit is greater than 15, then ASSERT().\r | |
| 671 | If EndBit is greater than 15, then ASSERT().\r | |
| 672 | If EndBit is less than StartBit, then ASSERT().\r | |
| 673 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 674 | \r | |
| 675 | @param Address The PCI configuration register to write.\r | |
| 676 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 677 | Range 0..15.\r | |
| 678 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 679 | Range 0..15.\r | |
| 680 | @param OrData The value to OR with the PCI configuration register.\r | |
| 681 | \r | |
| 682 | @return The value written back to the PCI configuration register.\r | |
| 683 | \r | |
| 684 | **/\r | |
| 685 | UINT16\r | |
| 686 | EFIAPI\r | |
| 687 | PciBitFieldOr16 (\r | |
| ac0a286f MK |
688 | IN UINTN Address,\r |
| 689 | IN UINTN StartBit,\r | |
| 690 | IN UINTN EndBit,\r | |
| 691 | IN UINT16 OrData\r | |
| 7523788f LE |
692 | )\r |
| 693 | {\r | |
| 694 | return mRunningOnQ35 ?\r | |
| 695 | PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData) :\r | |
| 696 | PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
| 697 | }\r | |
| 698 | \r | |
| 699 | /**\r | |
| 700 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
| 701 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
| 702 | \r | |
| 703 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 704 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 705 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 706 | Address. The value written to the PCI configuration register is returned.\r | |
| 707 | This function must guarantee that all PCI read and write operations are\r | |
| 708 | serialized. Extra left bits in AndData are stripped.\r | |
| 709 | \r | |
| 710 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 711 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 712 | If StartBit is greater than 15, then ASSERT().\r | |
| 713 | If EndBit is greater than 15, then ASSERT().\r | |
| 714 | If EndBit is less than StartBit, then ASSERT().\r | |
| 715 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 716 | \r | |
| 717 | @param Address The PCI configuration register to write.\r | |
| 718 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 719 | Range 0..15.\r | |
| 720 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 721 | Range 0..15.\r | |
| 722 | @param AndData The value to AND with the PCI configuration register.\r | |
| 723 | \r | |
| 724 | @return The value written back to the PCI configuration register.\r | |
| 725 | \r | |
| 726 | **/\r | |
| 727 | UINT16\r | |
| 728 | EFIAPI\r | |
| 729 | PciBitFieldAnd16 (\r | |
| ac0a286f MK |
730 | IN UINTN Address,\r |
| 731 | IN UINTN StartBit,\r | |
| 732 | IN UINTN EndBit,\r | |
| 733 | IN UINT16 AndData\r | |
| 7523788f LE |
734 | )\r |
| 735 | {\r | |
| 736 | return mRunningOnQ35 ?\r | |
| 737 | PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData) :\r | |
| 738 | PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
| 739 | }\r | |
| 740 | \r | |
| 741 | /**\r | |
| 742 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
| 743 | bitwise OR, and writes the result back to the bit field in the\r | |
| 744 | 16-bit port.\r | |
| 745 | \r | |
| 746 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 747 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 748 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
| 749 | configuration register specified by Address. The value written to the PCI\r | |
| 750 | configuration register is returned. This function must guarantee that all PCI\r | |
| 751 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 752 | OrData are stripped.\r | |
| 753 | \r | |
| 754 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 755 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 756 | If StartBit is greater than 15, then ASSERT().\r | |
| 757 | If EndBit is greater than 15, then ASSERT().\r | |
| 758 | If EndBit is less than StartBit, then ASSERT().\r | |
| 759 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 760 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 761 | \r | |
| 762 | @param Address The PCI configuration register to write.\r | |
| 763 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 764 | Range 0..15.\r | |
| 765 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 766 | Range 0..15.\r | |
| 767 | @param AndData The value to AND with the PCI configuration register.\r | |
| 768 | @param OrData The value to OR with the result of the AND operation.\r | |
| 769 | \r | |
| 770 | @return The value written back to the PCI configuration register.\r | |
| 771 | \r | |
| 772 | **/\r | |
| 773 | UINT16\r | |
| 774 | EFIAPI\r | |
| 775 | PciBitFieldAndThenOr16 (\r | |
| ac0a286f MK |
776 | IN UINTN Address,\r |
| 777 | IN UINTN StartBit,\r | |
| 778 | IN UINTN EndBit,\r | |
| 779 | IN UINT16 AndData,\r | |
| 780 | IN UINT16 OrData\r | |
| 7523788f LE |
781 | )\r |
| 782 | {\r | |
| 783 | return mRunningOnQ35 ?\r | |
| 784 | PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 785 | PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 786 | }\r | |
| 787 | \r | |
| 788 | /**\r | |
| 789 | Reads a 32-bit PCI configuration register.\r | |
| 790 | \r | |
| 791 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
| 792 | This function must guarantee that all PCI read and write operations are\r | |
| 793 | serialized.\r | |
| 794 | \r | |
| 795 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 796 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 797 | \r | |
| 798 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 799 | Register.\r | |
| 800 | \r | |
| 801 | @return The read value from the PCI configuration register.\r | |
| 802 | \r | |
| 803 | **/\r | |
| 804 | UINT32\r | |
| 805 | EFIAPI\r | |
| 806 | PciRead32 (\r | |
| ac0a286f | 807 | IN UINTN Address\r |
| 7523788f LE |
808 | )\r |
| 809 | {\r | |
| 810 | return mRunningOnQ35 ?\r | |
| 811 | PciExpressRead32 (Address) :\r | |
| 812 | PciCf8Read32 (Address);\r | |
| 813 | }\r | |
| 814 | \r | |
| 815 | /**\r | |
| 816 | Writes a 32-bit PCI configuration register.\r | |
| 817 | \r | |
| 818 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
| 819 | value specified by Value. Value is returned. This function must guarantee\r | |
| 820 | that all PCI read and write operations are serialized.\r | |
| 821 | \r | |
| 822 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 823 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 824 | \r | |
| 825 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 826 | Register.\r | |
| 827 | @param Value The value to write.\r | |
| 828 | \r | |
| 829 | @return The value written to the PCI configuration register.\r | |
| 830 | \r | |
| 831 | **/\r | |
| 832 | UINT32\r | |
| 833 | EFIAPI\r | |
| 834 | PciWrite32 (\r | |
| ac0a286f MK |
835 | IN UINTN Address,\r |
| 836 | IN UINT32 Value\r | |
| 7523788f LE |
837 | )\r |
| 838 | {\r | |
| 839 | return mRunningOnQ35 ?\r | |
| 840 | PciExpressWrite32 (Address, Value) :\r | |
| 841 | PciCf8Write32 (Address, Value);\r | |
| 842 | }\r | |
| 843 | \r | |
| 844 | /**\r | |
| 845 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
| 846 | a 32-bit value.\r | |
| 847 | \r | |
| 848 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 849 | bitwise OR between the read result and the value specified by\r | |
| 850 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 851 | specified by Address. The value written to the PCI configuration register is\r | |
| 852 | returned. This function must guarantee that all PCI read and write operations\r | |
| 853 | are serialized.\r | |
| 854 | \r | |
| 855 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 856 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 857 | \r | |
| 858 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 859 | Register.\r | |
| 860 | @param OrData The value to OR with the PCI configuration register.\r | |
| 861 | \r | |
| 862 | @return The value written back to the PCI configuration register.\r | |
| 863 | \r | |
| 864 | **/\r | |
| 865 | UINT32\r | |
| 866 | EFIAPI\r | |
| 867 | PciOr32 (\r | |
| ac0a286f MK |
868 | IN UINTN Address,\r |
| 869 | IN UINT32 OrData\r | |
| 7523788f LE |
870 | )\r |
| 871 | {\r | |
| 872 | return mRunningOnQ35 ?\r | |
| 873 | PciExpressOr32 (Address, OrData) :\r | |
| 874 | PciCf8Or32 (Address, OrData);\r | |
| 875 | }\r | |
| 876 | \r | |
| 877 | /**\r | |
| 878 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 879 | value.\r | |
| 880 | \r | |
| 881 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 882 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 883 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 884 | Address. The value written to the PCI configuration register is returned.\r | |
| 885 | This function must guarantee that all PCI read and write operations are\r | |
| 886 | serialized.\r | |
| 887 | \r | |
| 888 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 889 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 890 | \r | |
| 891 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 892 | Register.\r | |
| 893 | @param AndData The value to AND with the PCI configuration register.\r | |
| 894 | \r | |
| 895 | @return The value written back to the PCI configuration register.\r | |
| 896 | \r | |
| 897 | **/\r | |
| 898 | UINT32\r | |
| 899 | EFIAPI\r | |
| 900 | PciAnd32 (\r | |
| ac0a286f MK |
901 | IN UINTN Address,\r |
| 902 | IN UINT32 AndData\r | |
| 7523788f LE |
903 | )\r |
| 904 | {\r | |
| 905 | return mRunningOnQ35 ?\r | |
| 906 | PciExpressAnd32 (Address, AndData) :\r | |
| 907 | PciCf8And32 (Address, AndData);\r | |
| 908 | }\r | |
| 909 | \r | |
| 910 | /**\r | |
| 911 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 912 | value, followed a bitwise OR with another 32-bit value.\r | |
| 913 | \r | |
| 914 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 915 | bitwise AND between the read result and the value specified by AndData,\r | |
| 916 | performs a bitwise OR between the result of the AND operation and\r | |
| 917 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
| 918 | configuration register specified by Address. The value written to the PCI\r | |
| 919 | configuration register is returned. This function must guarantee that all PCI\r | |
| 920 | read and write operations are serialized.\r | |
| 921 | \r | |
| 922 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 923 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 924 | \r | |
| 925 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 926 | Register.\r | |
| 927 | @param AndData The value to AND with the PCI configuration register.\r | |
| 928 | @param OrData The value to OR with the result of the AND operation.\r | |
| 929 | \r | |
| 930 | @return The value written back to the PCI configuration register.\r | |
| 931 | \r | |
| 932 | **/\r | |
| 933 | UINT32\r | |
| 934 | EFIAPI\r | |
| 935 | PciAndThenOr32 (\r | |
| ac0a286f MK |
936 | IN UINTN Address,\r |
| 937 | IN UINT32 AndData,\r | |
| 938 | IN UINT32 OrData\r | |
| 7523788f LE |
939 | )\r |
| 940 | {\r | |
| 941 | return mRunningOnQ35 ?\r | |
| 942 | PciExpressAndThenOr32 (Address, AndData, OrData) :\r | |
| 943 | PciCf8AndThenOr32 (Address, AndData, OrData);\r | |
| 944 | }\r | |
| 945 | \r | |
| 946 | /**\r | |
| 947 | Reads a bit field of a PCI configuration register.\r | |
| 948 | \r | |
| 949 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
| 950 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 951 | returned.\r | |
| 952 | \r | |
| 953 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 954 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 955 | If StartBit is greater than 31, then ASSERT().\r | |
| 956 | If EndBit is greater than 31, then ASSERT().\r | |
| 957 | If EndBit is less than StartBit, then ASSERT().\r | |
| 958 | \r | |
| 959 | @param Address The PCI configuration register to read.\r | |
| 960 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 961 | Range 0..31.\r | |
| 962 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 963 | Range 0..31.\r | |
| 964 | \r | |
| 965 | @return The value of the bit field read from the PCI configuration register.\r | |
| 966 | \r | |
| 967 | **/\r | |
| 968 | UINT32\r | |
| 969 | EFIAPI\r | |
| 970 | PciBitFieldRead32 (\r | |
| ac0a286f MK |
971 | IN UINTN Address,\r |
| 972 | IN UINTN StartBit,\r | |
| 973 | IN UINTN EndBit\r | |
| 7523788f LE |
974 | )\r |
| 975 | {\r | |
| 976 | return mRunningOnQ35 ?\r | |
| 977 | PciExpressBitFieldRead32 (Address, StartBit, EndBit) :\r | |
| 978 | PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r | |
| 979 | }\r | |
| 980 | \r | |
| 981 | /**\r | |
| 982 | Writes a bit field to a PCI configuration register.\r | |
| 983 | \r | |
| 984 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 985 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 986 | destination PCI configuration register are preserved. The new value of the\r | |
| 987 | 32-bit register is returned.\r | |
| 988 | \r | |
| 989 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 990 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 991 | If StartBit is greater than 31, then ASSERT().\r | |
| 992 | If EndBit is greater than 31, then ASSERT().\r | |
| 993 | If EndBit is less than StartBit, then ASSERT().\r | |
| 994 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 995 | \r | |
| 996 | @param Address The PCI configuration register to write.\r | |
| 997 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 998 | Range 0..31.\r | |
| 999 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1000 | Range 0..31.\r | |
| 1001 | @param Value The new value of the bit field.\r | |
| 1002 | \r | |
| 1003 | @return The value written back to the PCI configuration register.\r | |
| 1004 | \r | |
| 1005 | **/\r | |
| 1006 | UINT32\r | |
| 1007 | EFIAPI\r | |
| 1008 | PciBitFieldWrite32 (\r | |
| ac0a286f MK |
1009 | IN UINTN Address,\r |
| 1010 | IN UINTN StartBit,\r | |
| 1011 | IN UINTN EndBit,\r | |
| 1012 | IN UINT32 Value\r | |
| 7523788f LE |
1013 | )\r |
| 1014 | {\r | |
| 1015 | return mRunningOnQ35 ?\r | |
| 1016 | PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value) :\r | |
| 1017 | PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
| 1018 | }\r | |
| 1019 | \r | |
| 1020 | /**\r | |
| 1021 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
| 1022 | writes the result back to the bit field in the 32-bit port.\r | |
| 1023 | \r | |
| 1024 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1025 | bitwise OR between the read result and the value specified by\r | |
| 1026 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 1027 | specified by Address. The value written to the PCI configuration register is\r | |
| 1028 | returned. This function must guarantee that all PCI read and write operations\r | |
| 1029 | are serialized. Extra left bits in OrData are stripped.\r | |
| 1030 | \r | |
| 1031 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1032 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1033 | If StartBit is greater than 31, then ASSERT().\r | |
| 1034 | If EndBit is greater than 31, then ASSERT().\r | |
| 1035 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1036 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1037 | \r | |
| 1038 | @param Address The PCI configuration register to write.\r | |
| 1039 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1040 | Range 0..31.\r | |
| 1041 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1042 | Range 0..31.\r | |
| 1043 | @param OrData The value to OR with the PCI configuration register.\r | |
| 1044 | \r | |
| 1045 | @return The value written back to the PCI configuration register.\r | |
| 1046 | \r | |
| 1047 | **/\r | |
| 1048 | UINT32\r | |
| 1049 | EFIAPI\r | |
| 1050 | PciBitFieldOr32 (\r | |
| ac0a286f MK |
1051 | IN UINTN Address,\r |
| 1052 | IN UINTN StartBit,\r | |
| 1053 | IN UINTN EndBit,\r | |
| 1054 | IN UINT32 OrData\r | |
| 7523788f LE |
1055 | )\r |
| 1056 | {\r | |
| 1057 | return mRunningOnQ35 ?\r | |
| 1058 | PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData) :\r | |
| 1059 | PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
| 1060 | }\r | |
| 1061 | \r | |
| 1062 | /**\r | |
| 1063 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
| 1064 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
| 1065 | \r | |
| 1066 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1067 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 1068 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 1069 | Address. The value written to the PCI configuration register is returned.\r | |
| 1070 | This function must guarantee that all PCI read and write operations are\r | |
| 1071 | serialized. Extra left bits in AndData are stripped.\r | |
| 1072 | \r | |
| 1073 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1074 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1075 | If StartBit is greater than 31, then ASSERT().\r | |
| 1076 | If EndBit is greater than 31, then ASSERT().\r | |
| 1077 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1078 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1079 | \r | |
| 1080 | @param Address The PCI configuration register to write.\r | |
| 1081 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1082 | Range 0..31.\r | |
| 1083 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1084 | Range 0..31.\r | |
| 1085 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1086 | \r | |
| 1087 | @return The value written back to the PCI configuration register.\r | |
| 1088 | \r | |
| 1089 | **/\r | |
| 1090 | UINT32\r | |
| 1091 | EFIAPI\r | |
| 1092 | PciBitFieldAnd32 (\r | |
| ac0a286f MK |
1093 | IN UINTN Address,\r |
| 1094 | IN UINTN StartBit,\r | |
| 1095 | IN UINTN EndBit,\r | |
| 1096 | IN UINT32 AndData\r | |
| 7523788f LE |
1097 | )\r |
| 1098 | {\r | |
| 1099 | return mRunningOnQ35 ?\r | |
| 1100 | PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData) :\r | |
| 1101 | PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
| 1102 | }\r | |
| 1103 | \r | |
| 1104 | /**\r | |
| 1105 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
| 1106 | bitwise OR, and writes the result back to the bit field in the\r | |
| 1107 | 32-bit port.\r | |
| 1108 | \r | |
| 1109 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1110 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 1111 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
| 1112 | configuration register specified by Address. The value written to the PCI\r | |
| 1113 | configuration register is returned. This function must guarantee that all PCI\r | |
| 1114 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 1115 | OrData are stripped.\r | |
| 1116 | \r | |
| 1117 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1118 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1119 | If StartBit is greater than 31, then ASSERT().\r | |
| 1120 | If EndBit is greater than 31, then ASSERT().\r | |
| 1121 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1122 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1123 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1124 | \r | |
| 1125 | @param Address The PCI configuration register to write.\r | |
| 1126 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1127 | Range 0..31.\r | |
| 1128 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1129 | Range 0..31.\r | |
| 1130 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1131 | @param OrData The value to OR with the result of the AND operation.\r | |
| 1132 | \r | |
| 1133 | @return The value written back to the PCI configuration register.\r | |
| 1134 | \r | |
| 1135 | **/\r | |
| 1136 | UINT32\r | |
| 1137 | EFIAPI\r | |
| 1138 | PciBitFieldAndThenOr32 (\r | |
| ac0a286f MK |
1139 | IN UINTN Address,\r |
| 1140 | IN UINTN StartBit,\r | |
| 1141 | IN UINTN EndBit,\r | |
| 1142 | IN UINT32 AndData,\r | |
| 1143 | IN UINT32 OrData\r | |
| 7523788f LE |
1144 | )\r |
| 1145 | {\r | |
| 1146 | return mRunningOnQ35 ?\r | |
| 1147 | PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 1148 | PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 1149 | }\r | |
| 1150 | \r | |
| 1151 | /**\r | |
| 1152 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
| 1153 | \r | |
| 1154 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
| 1155 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
| 1156 | configuration registers from a single PCI function to be read. Size is\r | |
| 1157 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
| a2e75595 | 1158 | from StartAddress to StartAddress + Size. Due to alignment restrictions, 8-bit\r |
| 7523788f LE |
1159 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r |
| 1160 | end of the range.\r | |
| 1161 | \r | |
| 1162 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1163 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1164 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1165 | \r | |
| 1166 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1167 | Function and Register.\r | |
| 1168 | @param Size The size in bytes of the transfer.\r | |
| 1169 | @param Buffer The pointer to a buffer receiving the data read.\r | |
| 1170 | \r | |
| 1171 | @return Size\r | |
| 1172 | \r | |
| 1173 | **/\r | |
| 1174 | UINTN\r | |
| 1175 | EFIAPI\r | |
| 1176 | PciReadBuffer (\r | |
| ac0a286f MK |
1177 | IN UINTN StartAddress,\r |
| 1178 | IN UINTN Size,\r | |
| 1179 | OUT VOID *Buffer\r | |
| 7523788f LE |
1180 | )\r |
| 1181 | {\r | |
| 1182 | return mRunningOnQ35 ?\r | |
| 1183 | PciExpressReadBuffer (StartAddress, Size, Buffer) :\r | |
| 1184 | PciCf8ReadBuffer (StartAddress, Size, Buffer);\r | |
| 1185 | }\r | |
| 1186 | \r | |
| 1187 | /**\r | |
| 1188 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
| 1189 | configuration space.\r | |
| 1190 | \r | |
| 1191 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
| 1192 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
| 1193 | configuration registers from a single PCI function to be written. Size is\r | |
| 1194 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
| a2e75595 | 1195 | write from StartAddress to StartAddress + Size. Due to alignment restrictions,\r |
| 7523788f LE |
1196 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r |
| 1197 | and the end of the range.\r | |
| 1198 | \r | |
| 1199 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1200 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1201 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1202 | \r | |
| 1203 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1204 | Function and Register.\r | |
| 1205 | @param Size The size in bytes of the transfer.\r | |
| 1206 | @param Buffer The pointer to a buffer containing the data to write.\r | |
| 1207 | \r | |
| 1208 | @return Size written to StartAddress.\r | |
| 1209 | \r | |
| 1210 | **/\r | |
| 1211 | UINTN\r | |
| 1212 | EFIAPI\r | |
| 1213 | PciWriteBuffer (\r | |
| ac0a286f MK |
1214 | IN UINTN StartAddress,\r |
| 1215 | IN UINTN Size,\r | |
| 1216 | IN VOID *Buffer\r | |
| 7523788f LE |
1217 | )\r |
| 1218 | {\r | |
| 1219 | return mRunningOnQ35 ?\r | |
| 1220 | PciExpressWriteBuffer (StartAddress, Size, Buffer) :\r | |
| 1221 | PciCf8WriteBuffer (StartAddress, Size, Buffer);\r | |
| 1222 | }\r |