projects / mirror_edk2.git / blame
| Commit | Line | Data |
|---|---|---|
| 7523788f LE |
1 | /** @file\r |
| 2 | PCI Library functions that use\r | |
| 3 | (a) I/O ports 0xCF8 and 0xCFC to perform PCI Configuration cycles, layering\r | |
| 4 | on top of one PCI CF8 Library instance; or\r | |
| 5 | (b) PCI Library functions that use the 256 MB PCI Express MMIO window to\r | |
| 6 | perform PCI Configuration cycles, layering on PCI Express Library.\r | |
| 7 | \r | |
| 8 | The decision is made in the entry point function, based on the OVMF platform\r | |
| 9 | type, and then adhered to during the lifetime of the client module.\r | |
| 10 | \r | |
| 11 | Copyright (C) 2016, Red Hat, Inc.\r | |
| 12 | \r | |
| 13 | Copyright (c) 2006 - 2012, Intel Corporation. All rights reserved.<BR>\r | |
| b26f0cf9 | 14 | SPDX-License-Identifier: BSD-2-Clause-Patent\r |
| 7523788f LE |
15 | \r |
| 16 | **/\r | |
| 17 | \r | |
| 18 | \r | |
| 19 | #include <Base.h>\r | |
| 20 | \r | |
| 21 | #include <IndustryStandard/Q35MchIch9.h>\r | |
| 22 | \r | |
| 23 | #include <Library/PciLib.h>\r | |
| 24 | #include <Library/PciCf8Lib.h>\r | |
| 25 | #include <Library/PciExpressLib.h>\r | |
| 26 | #include <Library/PcdLib.h>\r | |
| 27 | \r | |
| 28 | STATIC BOOLEAN mRunningOnQ35;\r | |
| 29 | \r | |
| 30 | RETURN_STATUS\r | |
| 31 | EFIAPI\r | |
| 32 | InitializeConfigAccessMethod (\r | |
| 33 | VOID\r | |
| 34 | )\r | |
| 35 | {\r | |
| 36 | mRunningOnQ35 = (PcdGet16 (PcdOvmfHostBridgePciDevId) ==\r | |
| 37 | INTEL_Q35_MCH_DEVICE_ID);\r | |
| 38 | return RETURN_SUCCESS;\r | |
| 39 | }\r | |
| 40 | \r | |
| 41 | /**\r | |
| 42 | Registers a PCI device so PCI configuration registers may be accessed after \r | |
| 43 | SetVirtualAddressMap().\r | |
| 44 | \r | |
| 45 | Registers the PCI device specified by Address so all the PCI configuration registers \r | |
| 46 | associated with that PCI device may be accessed after SetVirtualAddressMap() is called.\r | |
| 47 | \r | |
| 48 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 49 | \r | |
| 50 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 51 | Register.\r | |
| 52 | \r | |
| 53 | @retval RETURN_SUCCESS The PCI device was registered for runtime access.\r | |
| 54 | @retval RETURN_UNSUPPORTED An attempt was made to call this function \r | |
| 55 | after ExitBootServices().\r | |
| 56 | @retval RETURN_UNSUPPORTED The resources required to access the PCI device\r | |
| 57 | at runtime could not be mapped.\r | |
| 58 | @retval RETURN_OUT_OF_RESOURCES There are not enough resources available to\r | |
| 59 | complete the registration.\r | |
| 60 | \r | |
| 61 | **/\r | |
| 62 | RETURN_STATUS\r | |
| 63 | EFIAPI\r | |
| 64 | PciRegisterForRuntimeAccess (\r | |
| 65 | IN UINTN Address\r | |
| 66 | )\r | |
| 67 | {\r | |
| 68 | return mRunningOnQ35 ?\r | |
| 69 | PciExpressRegisterForRuntimeAccess (Address) :\r | |
| 70 | PciCf8RegisterForRuntimeAccess (Address);\r | |
| 71 | }\r | |
| 72 | \r | |
| 73 | /**\r | |
| 74 | Reads an 8-bit PCI configuration register.\r | |
| 75 | \r | |
| 76 | Reads and returns the 8-bit PCI configuration register specified by Address.\r | |
| 77 | This function must guarantee that all PCI read and write operations are\r | |
| 78 | serialized.\r | |
| 79 | \r | |
| 80 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 81 | \r | |
| 82 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 83 | Register.\r | |
| 84 | \r | |
| 85 | @return The read value from the PCI configuration register.\r | |
| 86 | \r | |
| 87 | **/\r | |
| 88 | UINT8\r | |
| 89 | EFIAPI\r | |
| 90 | PciRead8 (\r | |
| 91 | IN UINTN Address\r | |
| 92 | )\r | |
| 93 | {\r | |
| 94 | return mRunningOnQ35 ?\r | |
| 95 | PciExpressRead8 (Address) :\r | |
| 96 | PciCf8Read8 (Address);\r | |
| 97 | }\r | |
| 98 | \r | |
| 99 | /**\r | |
| 100 | Writes an 8-bit PCI configuration register.\r | |
| 101 | \r | |
| 102 | Writes the 8-bit PCI configuration register specified by Address with the\r | |
| 103 | value specified by Value. Value is returned. This function must guarantee\r | |
| 104 | that all PCI read and write operations are serialized.\r | |
| 105 | \r | |
| 106 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 107 | \r | |
| 108 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 109 | Register.\r | |
| 110 | @param Value The value to write.\r | |
| 111 | \r | |
| 112 | @return The value written to the PCI configuration register.\r | |
| 113 | \r | |
| 114 | **/\r | |
| 115 | UINT8\r | |
| 116 | EFIAPI\r | |
| 117 | PciWrite8 (\r | |
| 118 | IN UINTN Address,\r | |
| 119 | IN UINT8 Value\r | |
| 120 | )\r | |
| 121 | {\r | |
| 122 | return mRunningOnQ35 ?\r | |
| 123 | PciExpressWrite8 (Address, Value) :\r | |
| 124 | PciCf8Write8 (Address, Value);\r | |
| 125 | }\r | |
| 126 | \r | |
| 127 | /**\r | |
| 128 | Performs a bitwise OR of an 8-bit PCI configuration register with\r | |
| 129 | an 8-bit value.\r | |
| 130 | \r | |
| 131 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 132 | bitwise OR between the read result and the value specified by\r | |
| 133 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 134 | specified by Address. The value written to the PCI configuration register is\r | |
| 135 | returned. This function must guarantee that all PCI read and write operations\r | |
| 136 | are serialized.\r | |
| 137 | \r | |
| 138 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 139 | \r | |
| 140 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 141 | Register.\r | |
| 142 | @param OrData The value to OR with the PCI configuration register.\r | |
| 143 | \r | |
| 144 | @return The value written back to the PCI configuration register.\r | |
| 145 | \r | |
| 146 | **/\r | |
| 147 | UINT8\r | |
| 148 | EFIAPI\r | |
| 149 | PciOr8 (\r | |
| 150 | IN UINTN Address,\r | |
| 151 | IN UINT8 OrData\r | |
| 152 | )\r | |
| 153 | {\r | |
| 154 | return mRunningOnQ35 ?\r | |
| 155 | PciExpressOr8 (Address, OrData) :\r | |
| 156 | PciCf8Or8 (Address, OrData);\r | |
| 157 | }\r | |
| 158 | \r | |
| 159 | /**\r | |
| 160 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 161 | value.\r | |
| 162 | \r | |
| 163 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 164 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 165 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 166 | Address. The value written to the PCI configuration register is returned.\r | |
| 167 | This function must guarantee that all PCI read and write operations are\r | |
| 168 | serialized.\r | |
| 169 | \r | |
| 170 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 171 | \r | |
| 172 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 173 | Register.\r | |
| 174 | @param AndData The value to AND with the PCI configuration register.\r | |
| 175 | \r | |
| 176 | @return The value written back to the PCI configuration register.\r | |
| 177 | \r | |
| 178 | **/\r | |
| 179 | UINT8\r | |
| 180 | EFIAPI\r | |
| 181 | PciAnd8 (\r | |
| 182 | IN UINTN Address,\r | |
| 183 | IN UINT8 AndData\r | |
| 184 | )\r | |
| 185 | {\r | |
| 186 | return mRunningOnQ35 ?\r | |
| 187 | PciExpressAnd8 (Address, AndData) :\r | |
| 188 | PciCf8And8 (Address, AndData);\r | |
| 189 | }\r | |
| 190 | \r | |
| 191 | /**\r | |
| 192 | Performs a bitwise AND of an 8-bit PCI configuration register with an 8-bit\r | |
| 193 | value, followed a bitwise OR with another 8-bit value.\r | |
| 194 | \r | |
| 195 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 196 | bitwise AND between the read result and the value specified by AndData,\r | |
| 197 | performs a bitwise OR between the result of the AND operation and\r | |
| 198 | the value specified by OrData, and writes the result to the 8-bit PCI\r | |
| 199 | configuration register specified by Address. The value written to the PCI\r | |
| 200 | configuration register is returned. This function must guarantee that all PCI\r | |
| 201 | read and write operations are serialized.\r | |
| 202 | \r | |
| 203 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 204 | \r | |
| 205 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 206 | Register.\r | |
| 207 | @param AndData The value to AND with the PCI configuration register.\r | |
| 208 | @param OrData The value to OR with the result of the AND operation.\r | |
| 209 | \r | |
| 210 | @return The value written back to the PCI configuration register.\r | |
| 211 | \r | |
| 212 | **/\r | |
| 213 | UINT8\r | |
| 214 | EFIAPI\r | |
| 215 | PciAndThenOr8 (\r | |
| 216 | IN UINTN Address,\r | |
| 217 | IN UINT8 AndData,\r | |
| 218 | IN UINT8 OrData\r | |
| 219 | )\r | |
| 220 | {\r | |
| 221 | return mRunningOnQ35 ?\r | |
| 222 | PciExpressAndThenOr8 (Address, AndData, OrData) :\r | |
| 223 | PciCf8AndThenOr8 (Address, AndData, OrData);\r | |
| 224 | }\r | |
| 225 | \r | |
| 226 | /**\r | |
| 227 | Reads a bit field of a PCI configuration register.\r | |
| 228 | \r | |
| 229 | Reads the bit field in an 8-bit PCI configuration register. The bit field is\r | |
| 230 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 231 | returned.\r | |
| 232 | \r | |
| 233 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 234 | If StartBit is greater than 7, then ASSERT().\r | |
| 235 | If EndBit is greater than 7, then ASSERT().\r | |
| 236 | If EndBit is less than StartBit, then ASSERT().\r | |
| 237 | \r | |
| 238 | @param Address The PCI configuration register to read.\r | |
| 239 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 240 | Range 0..7.\r | |
| 241 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 242 | Range 0..7.\r | |
| 243 | \r | |
| 244 | @return The value of the bit field read from the PCI configuration register.\r | |
| 245 | \r | |
| 246 | **/\r | |
| 247 | UINT8\r | |
| 248 | EFIAPI\r | |
| 249 | PciBitFieldRead8 (\r | |
| 250 | IN UINTN Address,\r | |
| 251 | IN UINTN StartBit,\r | |
| 252 | IN UINTN EndBit\r | |
| 253 | )\r | |
| 254 | {\r | |
| 255 | return mRunningOnQ35 ?\r | |
| 256 | PciExpressBitFieldRead8 (Address, StartBit, EndBit) :\r | |
| 257 | PciCf8BitFieldRead8 (Address, StartBit, EndBit);\r | |
| 258 | }\r | |
| 259 | \r | |
| 260 | /**\r | |
| 261 | Writes a bit field to a PCI configuration register.\r | |
| 262 | \r | |
| 263 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 264 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 265 | destination PCI configuration register are preserved. The new value of the\r | |
| 266 | 8-bit register is returned.\r | |
| 267 | \r | |
| 268 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 269 | If StartBit is greater than 7, then ASSERT().\r | |
| 270 | If EndBit is greater than 7, then ASSERT().\r | |
| 271 | If EndBit is less than StartBit, then ASSERT().\r | |
| 272 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 273 | \r | |
| 274 | @param Address The PCI configuration register to write.\r | |
| 275 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 276 | Range 0..7.\r | |
| 277 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 278 | Range 0..7.\r | |
| 279 | @param Value The new value of the bit field.\r | |
| 280 | \r | |
| 281 | @return The value written back to the PCI configuration register.\r | |
| 282 | \r | |
| 283 | **/\r | |
| 284 | UINT8\r | |
| 285 | EFIAPI\r | |
| 286 | PciBitFieldWrite8 (\r | |
| 287 | IN UINTN Address,\r | |
| 288 | IN UINTN StartBit,\r | |
| 289 | IN UINTN EndBit,\r | |
| 290 | IN UINT8 Value\r | |
| 291 | )\r | |
| 292 | {\r | |
| 293 | return mRunningOnQ35 ?\r | |
| 294 | PciExpressBitFieldWrite8 (Address, StartBit, EndBit, Value) :\r | |
| 295 | PciCf8BitFieldWrite8 (Address, StartBit, EndBit, Value);\r | |
| 296 | }\r | |
| 297 | \r | |
| 298 | /**\r | |
| 299 | Reads a bit field in an 8-bit PCI configuration, performs a bitwise OR, and\r | |
| 300 | writes the result back to the bit field in the 8-bit port.\r | |
| 301 | \r | |
| 302 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 303 | bitwise OR between the read result and the value specified by\r | |
| 304 | OrData, and writes the result to the 8-bit PCI configuration register\r | |
| 305 | specified by Address. The value written to the PCI configuration register is\r | |
| 306 | returned. This function must guarantee that all PCI read and write operations\r | |
| 307 | are serialized. Extra left bits in OrData are stripped.\r | |
| 308 | \r | |
| 309 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 310 | If StartBit is greater than 7, then ASSERT().\r | |
| 311 | If EndBit is greater than 7, then ASSERT().\r | |
| 312 | If EndBit is less than StartBit, then ASSERT().\r | |
| 313 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 314 | \r | |
| 315 | @param Address The PCI configuration register to write.\r | |
| 316 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 317 | Range 0..7.\r | |
| 318 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 319 | Range 0..7.\r | |
| 320 | @param OrData The value to OR with the PCI configuration register.\r | |
| 321 | \r | |
| 322 | @return The value written back to the PCI configuration register.\r | |
| 323 | \r | |
| 324 | **/\r | |
| 325 | UINT8\r | |
| 326 | EFIAPI\r | |
| 327 | PciBitFieldOr8 (\r | |
| 328 | IN UINTN Address,\r | |
| 329 | IN UINTN StartBit,\r | |
| 330 | IN UINTN EndBit,\r | |
| 331 | IN UINT8 OrData\r | |
| 332 | )\r | |
| 333 | {\r | |
| 334 | return mRunningOnQ35 ?\r | |
| 335 | PciExpressBitFieldOr8 (Address, StartBit, EndBit, OrData) :\r | |
| 336 | PciCf8BitFieldOr8 (Address, StartBit, EndBit, OrData);\r | |
| 337 | }\r | |
| 338 | \r | |
| 339 | /**\r | |
| 340 | Reads a bit field in an 8-bit PCI configuration register, performs a bitwise\r | |
| 341 | AND, and writes the result back to the bit field in the 8-bit register.\r | |
| 342 | \r | |
| 343 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 344 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 345 | writes the result to the 8-bit PCI configuration register specified by\r | |
| 346 | Address. The value written to the PCI configuration register is returned.\r | |
| 347 | This function must guarantee that all PCI read and write operations are\r | |
| 348 | serialized. Extra left bits in AndData are stripped.\r | |
| 349 | \r | |
| 350 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 351 | If StartBit is greater than 7, then ASSERT().\r | |
| 352 | If EndBit is greater than 7, then ASSERT().\r | |
| 353 | If EndBit is less than StartBit, then ASSERT().\r | |
| 354 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 355 | \r | |
| 356 | @param Address The PCI configuration register to write.\r | |
| 357 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 358 | Range 0..7.\r | |
| 359 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 360 | Range 0..7.\r | |
| 361 | @param AndData The value to AND with the PCI configuration register.\r | |
| 362 | \r | |
| 363 | @return The value written back to the PCI configuration register.\r | |
| 364 | \r | |
| 365 | **/\r | |
| 366 | UINT8\r | |
| 367 | EFIAPI\r | |
| 368 | PciBitFieldAnd8 (\r | |
| 369 | IN UINTN Address,\r | |
| 370 | IN UINTN StartBit,\r | |
| 371 | IN UINTN EndBit,\r | |
| 372 | IN UINT8 AndData\r | |
| 373 | )\r | |
| 374 | {\r | |
| 375 | return mRunningOnQ35 ?\r | |
| 376 | PciExpressBitFieldAnd8 (Address, StartBit, EndBit, AndData) :\r | |
| 377 | PciCf8BitFieldAnd8 (Address, StartBit, EndBit, AndData);\r | |
| 378 | }\r | |
| 379 | \r | |
| 380 | /**\r | |
| 381 | Reads a bit field in an 8-bit port, performs a bitwise AND followed by a\r | |
| 382 | bitwise OR, and writes the result back to the bit field in the\r | |
| 383 | 8-bit port.\r | |
| 384 | \r | |
| 385 | Reads the 8-bit PCI configuration register specified by Address, performs a\r | |
| 386 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 387 | the value specified by AndData, and writes the result to the 8-bit PCI\r | |
| 388 | configuration register specified by Address. The value written to the PCI\r | |
| 389 | configuration register is returned. This function must guarantee that all PCI\r | |
| 390 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 391 | OrData are stripped.\r | |
| 392 | \r | |
| 393 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 394 | If StartBit is greater than 7, then ASSERT().\r | |
| 395 | If EndBit is greater than 7, then ASSERT().\r | |
| 396 | If EndBit is less than StartBit, then ASSERT().\r | |
| 397 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 398 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 399 | \r | |
| 400 | @param Address The PCI configuration register to write.\r | |
| 401 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 402 | Range 0..7.\r | |
| 403 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 404 | Range 0..7.\r | |
| 405 | @param AndData The value to AND with the PCI configuration register.\r | |
| 406 | @param OrData The value to OR with the result of the AND operation.\r | |
| 407 | \r | |
| 408 | @return The value written back to the PCI configuration register.\r | |
| 409 | \r | |
| 410 | **/\r | |
| 411 | UINT8\r | |
| 412 | EFIAPI\r | |
| 413 | PciBitFieldAndThenOr8 (\r | |
| 414 | IN UINTN Address,\r | |
| 415 | IN UINTN StartBit,\r | |
| 416 | IN UINTN EndBit,\r | |
| 417 | IN UINT8 AndData,\r | |
| 418 | IN UINT8 OrData\r | |
| 419 | )\r | |
| 420 | {\r | |
| 421 | return mRunningOnQ35 ?\r | |
| 422 | PciExpressBitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 423 | PciCf8BitFieldAndThenOr8 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 424 | }\r | |
| 425 | \r | |
| 426 | /**\r | |
| 427 | Reads a 16-bit PCI configuration register.\r | |
| 428 | \r | |
| 429 | Reads and returns the 16-bit PCI configuration register specified by Address.\r | |
| 430 | This function must guarantee that all PCI read and write operations are\r | |
| 431 | serialized.\r | |
| 432 | \r | |
| 433 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 434 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 435 | \r | |
| 436 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 437 | Register.\r | |
| 438 | \r | |
| 439 | @return The read value from the PCI configuration register.\r | |
| 440 | \r | |
| 441 | **/\r | |
| 442 | UINT16\r | |
| 443 | EFIAPI\r | |
| 444 | PciRead16 (\r | |
| 445 | IN UINTN Address\r | |
| 446 | )\r | |
| 447 | {\r | |
| 448 | return mRunningOnQ35 ?\r | |
| 449 | PciExpressRead16 (Address) :\r | |
| 450 | PciCf8Read16 (Address);\r | |
| 451 | }\r | |
| 452 | \r | |
| 453 | /**\r | |
| 454 | Writes a 16-bit PCI configuration register.\r | |
| 455 | \r | |
| 456 | Writes the 16-bit PCI configuration register specified by Address with the\r | |
| 457 | value specified by Value. Value is returned. This function must guarantee\r | |
| 458 | that all PCI read and write operations are serialized.\r | |
| 459 | \r | |
| 460 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 461 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 462 | \r | |
| 463 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 464 | Register.\r | |
| 465 | @param Value The value to write.\r | |
| 466 | \r | |
| 467 | @return The value written to the PCI configuration register.\r | |
| 468 | \r | |
| 469 | **/\r | |
| 470 | UINT16\r | |
| 471 | EFIAPI\r | |
| 472 | PciWrite16 (\r | |
| 473 | IN UINTN Address,\r | |
| 474 | IN UINT16 Value\r | |
| 475 | )\r | |
| 476 | {\r | |
| 477 | return mRunningOnQ35 ?\r | |
| 478 | PciExpressWrite16 (Address, Value) :\r | |
| 479 | PciCf8Write16 (Address, Value);\r | |
| 480 | }\r | |
| 481 | \r | |
| 482 | /**\r | |
| 483 | Performs a bitwise OR of a 16-bit PCI configuration register with\r | |
| 484 | a 16-bit value.\r | |
| 485 | \r | |
| 486 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 487 | bitwise OR between the read result and the value specified by\r | |
| 488 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 489 | specified by Address. The value written to the PCI configuration register is\r | |
| 490 | returned. This function must guarantee that all PCI read and write operations\r | |
| 491 | are serialized.\r | |
| 492 | \r | |
| 493 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 494 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 495 | \r | |
| 496 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 497 | Register.\r | |
| 498 | @param OrData The value to OR with the PCI configuration register.\r | |
| 499 | \r | |
| 500 | @return The value written back to the PCI configuration register.\r | |
| 501 | \r | |
| 502 | **/\r | |
| 503 | UINT16\r | |
| 504 | EFIAPI\r | |
| 505 | PciOr16 (\r | |
| 506 | IN UINTN Address,\r | |
| 507 | IN UINT16 OrData\r | |
| 508 | )\r | |
| 509 | {\r | |
| 510 | return mRunningOnQ35 ?\r | |
| 511 | PciExpressOr16 (Address, OrData) :\r | |
| 512 | PciCf8Or16 (Address, OrData);\r | |
| 513 | }\r | |
| 514 | \r | |
| 515 | /**\r | |
| 516 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 517 | value.\r | |
| 518 | \r | |
| 519 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 520 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 521 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 522 | Address. The value written to the PCI configuration register is returned.\r | |
| 523 | This function must guarantee that all PCI read and write operations are\r | |
| 524 | serialized.\r | |
| 525 | \r | |
| 526 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 527 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 528 | \r | |
| 529 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 530 | Register.\r | |
| 531 | @param AndData The value to AND with the PCI configuration register.\r | |
| 532 | \r | |
| 533 | @return The value written back to the PCI configuration register.\r | |
| 534 | \r | |
| 535 | **/\r | |
| 536 | UINT16\r | |
| 537 | EFIAPI\r | |
| 538 | PciAnd16 (\r | |
| 539 | IN UINTN Address,\r | |
| 540 | IN UINT16 AndData\r | |
| 541 | )\r | |
| 542 | {\r | |
| 543 | return mRunningOnQ35 ?\r | |
| 544 | PciExpressAnd16 (Address, AndData) :\r | |
| 545 | PciCf8And16 (Address, AndData);\r | |
| 546 | }\r | |
| 547 | \r | |
| 548 | /**\r | |
| 549 | Performs a bitwise AND of a 16-bit PCI configuration register with a 16-bit\r | |
| 550 | value, followed a bitwise OR with another 16-bit value.\r | |
| 551 | \r | |
| 552 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 553 | bitwise AND between the read result and the value specified by AndData,\r | |
| 554 | performs a bitwise OR between the result of the AND operation and\r | |
| 555 | the value specified by OrData, and writes the result to the 16-bit PCI\r | |
| 556 | configuration register specified by Address. The value written to the PCI\r | |
| 557 | configuration register is returned. This function must guarantee that all PCI\r | |
| 558 | read and write operations are serialized.\r | |
| 559 | \r | |
| 560 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 561 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 562 | \r | |
| 563 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 564 | Register.\r | |
| 565 | @param AndData The value to AND with the PCI configuration register.\r | |
| 566 | @param OrData The value to OR with the result of the AND operation.\r | |
| 567 | \r | |
| 568 | @return The value written back to the PCI configuration register.\r | |
| 569 | \r | |
| 570 | **/\r | |
| 571 | UINT16\r | |
| 572 | EFIAPI\r | |
| 573 | PciAndThenOr16 (\r | |
| 574 | IN UINTN Address,\r | |
| 575 | IN UINT16 AndData,\r | |
| 576 | IN UINT16 OrData\r | |
| 577 | )\r | |
| 578 | {\r | |
| 579 | return mRunningOnQ35 ?\r | |
| 580 | PciExpressAndThenOr16 (Address, AndData, OrData) :\r | |
| 581 | PciCf8AndThenOr16 (Address, AndData, OrData);\r | |
| 582 | }\r | |
| 583 | \r | |
| 584 | /**\r | |
| 585 | Reads a bit field of a PCI configuration register.\r | |
| 586 | \r | |
| 587 | Reads the bit field in a 16-bit PCI configuration register. The bit field is\r | |
| 588 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 589 | returned.\r | |
| 590 | \r | |
| 591 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 592 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 593 | If StartBit is greater than 15, then ASSERT().\r | |
| 594 | If EndBit is greater than 15, then ASSERT().\r | |
| 595 | If EndBit is less than StartBit, then ASSERT().\r | |
| 596 | \r | |
| 597 | @param Address The PCI configuration register to read.\r | |
| 598 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 599 | Range 0..15.\r | |
| 600 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 601 | Range 0..15.\r | |
| 602 | \r | |
| 603 | @return The value of the bit field read from the PCI configuration register.\r | |
| 604 | \r | |
| 605 | **/\r | |
| 606 | UINT16\r | |
| 607 | EFIAPI\r | |
| 608 | PciBitFieldRead16 (\r | |
| 609 | IN UINTN Address,\r | |
| 610 | IN UINTN StartBit,\r | |
| 611 | IN UINTN EndBit\r | |
| 612 | )\r | |
| 613 | {\r | |
| 614 | return mRunningOnQ35 ?\r | |
| 615 | PciExpressBitFieldRead16 (Address, StartBit, EndBit) :\r | |
| 616 | PciCf8BitFieldRead16 (Address, StartBit, EndBit);\r | |
| 617 | }\r | |
| 618 | \r | |
| 619 | /**\r | |
| 620 | Writes a bit field to a PCI configuration register.\r | |
| 621 | \r | |
| 622 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 623 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 624 | destination PCI configuration register are preserved. The new value of the\r | |
| 625 | 16-bit register is returned.\r | |
| 626 | \r | |
| 627 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 628 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 629 | If StartBit is greater than 15, then ASSERT().\r | |
| 630 | If EndBit is greater than 15, then ASSERT().\r | |
| 631 | If EndBit is less than StartBit, then ASSERT().\r | |
| 632 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 633 | \r | |
| 634 | @param Address The PCI configuration register to write.\r | |
| 635 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 636 | Range 0..15.\r | |
| 637 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 638 | Range 0..15.\r | |
| 639 | @param Value The new value of the bit field.\r | |
| 640 | \r | |
| 641 | @return The value written back to the PCI configuration register.\r | |
| 642 | \r | |
| 643 | **/\r | |
| 644 | UINT16\r | |
| 645 | EFIAPI\r | |
| 646 | PciBitFieldWrite16 (\r | |
| 647 | IN UINTN Address,\r | |
| 648 | IN UINTN StartBit,\r | |
| 649 | IN UINTN EndBit,\r | |
| 650 | IN UINT16 Value\r | |
| 651 | )\r | |
| 652 | {\r | |
| 653 | return mRunningOnQ35 ?\r | |
| 654 | PciExpressBitFieldWrite16 (Address, StartBit, EndBit, Value) :\r | |
| 655 | PciCf8BitFieldWrite16 (Address, StartBit, EndBit, Value);\r | |
| 656 | }\r | |
| 657 | \r | |
| 658 | /**\r | |
| 659 | Reads a bit field in a 16-bit PCI configuration, performs a bitwise OR, and\r | |
| 660 | writes the result back to the bit field in the 16-bit port.\r | |
| 661 | \r | |
| 662 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 663 | bitwise OR between the read result and the value specified by\r | |
| 664 | OrData, and writes the result to the 16-bit PCI configuration register\r | |
| 665 | specified by Address. The value written to the PCI configuration register is\r | |
| 666 | returned. This function must guarantee that all PCI read and write operations\r | |
| 667 | are serialized. Extra left bits in OrData are stripped.\r | |
| 668 | \r | |
| 669 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 670 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 671 | If StartBit is greater than 15, then ASSERT().\r | |
| 672 | If EndBit is greater than 15, then ASSERT().\r | |
| 673 | If EndBit is less than StartBit, then ASSERT().\r | |
| 674 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 675 | \r | |
| 676 | @param Address The PCI configuration register to write.\r | |
| 677 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 678 | Range 0..15.\r | |
| 679 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 680 | Range 0..15.\r | |
| 681 | @param OrData The value to OR with the PCI configuration register.\r | |
| 682 | \r | |
| 683 | @return The value written back to the PCI configuration register.\r | |
| 684 | \r | |
| 685 | **/\r | |
| 686 | UINT16\r | |
| 687 | EFIAPI\r | |
| 688 | PciBitFieldOr16 (\r | |
| 689 | IN UINTN Address,\r | |
| 690 | IN UINTN StartBit,\r | |
| 691 | IN UINTN EndBit,\r | |
| 692 | IN UINT16 OrData\r | |
| 693 | )\r | |
| 694 | {\r | |
| 695 | return mRunningOnQ35 ?\r | |
| 696 | PciExpressBitFieldOr16 (Address, StartBit, EndBit, OrData) :\r | |
| 697 | PciCf8BitFieldOr16 (Address, StartBit, EndBit, OrData);\r | |
| 698 | }\r | |
| 699 | \r | |
| 700 | /**\r | |
| 701 | Reads a bit field in a 16-bit PCI configuration register, performs a bitwise\r | |
| 702 | AND, and writes the result back to the bit field in the 16-bit register.\r | |
| 703 | \r | |
| 704 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 705 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 706 | writes the result to the 16-bit PCI configuration register specified by\r | |
| 707 | Address. The value written to the PCI configuration register is returned.\r | |
| 708 | This function must guarantee that all PCI read and write operations are\r | |
| 709 | serialized. Extra left bits in AndData are stripped.\r | |
| 710 | \r | |
| 711 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 712 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 713 | If StartBit is greater than 15, then ASSERT().\r | |
| 714 | If EndBit is greater than 15, then ASSERT().\r | |
| 715 | If EndBit is less than StartBit, then ASSERT().\r | |
| 716 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 717 | \r | |
| 718 | @param Address The PCI configuration register to write.\r | |
| 719 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 720 | Range 0..15.\r | |
| 721 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 722 | Range 0..15.\r | |
| 723 | @param AndData The value to AND with the PCI configuration register.\r | |
| 724 | \r | |
| 725 | @return The value written back to the PCI configuration register.\r | |
| 726 | \r | |
| 727 | **/\r | |
| 728 | UINT16\r | |
| 729 | EFIAPI\r | |
| 730 | PciBitFieldAnd16 (\r | |
| 731 | IN UINTN Address,\r | |
| 732 | IN UINTN StartBit,\r | |
| 733 | IN UINTN EndBit,\r | |
| 734 | IN UINT16 AndData\r | |
| 735 | )\r | |
| 736 | {\r | |
| 737 | return mRunningOnQ35 ?\r | |
| 738 | PciExpressBitFieldAnd16 (Address, StartBit, EndBit, AndData) :\r | |
| 739 | PciCf8BitFieldAnd16 (Address, StartBit, EndBit, AndData);\r | |
| 740 | }\r | |
| 741 | \r | |
| 742 | /**\r | |
| 743 | Reads a bit field in a 16-bit port, performs a bitwise AND followed by a\r | |
| 744 | bitwise OR, and writes the result back to the bit field in the\r | |
| 745 | 16-bit port.\r | |
| 746 | \r | |
| 747 | Reads the 16-bit PCI configuration register specified by Address, performs a\r | |
| 748 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 749 | the value specified by AndData, and writes the result to the 16-bit PCI\r | |
| 750 | configuration register specified by Address. The value written to the PCI\r | |
| 751 | configuration register is returned. This function must guarantee that all PCI\r | |
| 752 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 753 | OrData are stripped.\r | |
| 754 | \r | |
| 755 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 756 | If Address is not aligned on a 16-bit boundary, then ASSERT().\r | |
| 757 | If StartBit is greater than 15, then ASSERT().\r | |
| 758 | If EndBit is greater than 15, then ASSERT().\r | |
| 759 | If EndBit is less than StartBit, then ASSERT().\r | |
| 760 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 761 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 762 | \r | |
| 763 | @param Address The PCI configuration register to write.\r | |
| 764 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 765 | Range 0..15.\r | |
| 766 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 767 | Range 0..15.\r | |
| 768 | @param AndData The value to AND with the PCI configuration register.\r | |
| 769 | @param OrData The value to OR with the result of the AND operation.\r | |
| 770 | \r | |
| 771 | @return The value written back to the PCI configuration register.\r | |
| 772 | \r | |
| 773 | **/\r | |
| 774 | UINT16\r | |
| 775 | EFIAPI\r | |
| 776 | PciBitFieldAndThenOr16 (\r | |
| 777 | IN UINTN Address,\r | |
| 778 | IN UINTN StartBit,\r | |
| 779 | IN UINTN EndBit,\r | |
| 780 | IN UINT16 AndData,\r | |
| 781 | IN UINT16 OrData\r | |
| 782 | )\r | |
| 783 | {\r | |
| 784 | return mRunningOnQ35 ?\r | |
| 785 | PciExpressBitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 786 | PciCf8BitFieldAndThenOr16 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 787 | }\r | |
| 788 | \r | |
| 789 | /**\r | |
| 790 | Reads a 32-bit PCI configuration register.\r | |
| 791 | \r | |
| 792 | Reads and returns the 32-bit PCI configuration register specified by Address.\r | |
| 793 | This function must guarantee that all PCI read and write operations are\r | |
| 794 | serialized.\r | |
| 795 | \r | |
| 796 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 797 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 798 | \r | |
| 799 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 800 | Register.\r | |
| 801 | \r | |
| 802 | @return The read value from the PCI configuration register.\r | |
| 803 | \r | |
| 804 | **/\r | |
| 805 | UINT32\r | |
| 806 | EFIAPI\r | |
| 807 | PciRead32 (\r | |
| 808 | IN UINTN Address\r | |
| 809 | )\r | |
| 810 | {\r | |
| 811 | return mRunningOnQ35 ?\r | |
| 812 | PciExpressRead32 (Address) :\r | |
| 813 | PciCf8Read32 (Address);\r | |
| 814 | }\r | |
| 815 | \r | |
| 816 | /**\r | |
| 817 | Writes a 32-bit PCI configuration register.\r | |
| 818 | \r | |
| 819 | Writes the 32-bit PCI configuration register specified by Address with the\r | |
| 820 | value specified by Value. Value is returned. This function must guarantee\r | |
| 821 | that all PCI read and write operations are serialized.\r | |
| 822 | \r | |
| 823 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 824 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 825 | \r | |
| 826 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 827 | Register.\r | |
| 828 | @param Value The value to write.\r | |
| 829 | \r | |
| 830 | @return The value written to the PCI configuration register.\r | |
| 831 | \r | |
| 832 | **/\r | |
| 833 | UINT32\r | |
| 834 | EFIAPI\r | |
| 835 | PciWrite32 (\r | |
| 836 | IN UINTN Address,\r | |
| 837 | IN UINT32 Value\r | |
| 838 | )\r | |
| 839 | {\r | |
| 840 | return mRunningOnQ35 ?\r | |
| 841 | PciExpressWrite32 (Address, Value) :\r | |
| 842 | PciCf8Write32 (Address, Value);\r | |
| 843 | }\r | |
| 844 | \r | |
| 845 | /**\r | |
| 846 | Performs a bitwise OR of a 32-bit PCI configuration register with\r | |
| 847 | a 32-bit value.\r | |
| 848 | \r | |
| 849 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 850 | bitwise OR between the read result and the value specified by\r | |
| 851 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 852 | specified by Address. The value written to the PCI configuration register is\r | |
| 853 | returned. This function must guarantee that all PCI read and write operations\r | |
| 854 | are serialized.\r | |
| 855 | \r | |
| 856 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 857 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 858 | \r | |
| 859 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 860 | Register.\r | |
| 861 | @param OrData The value to OR with the PCI configuration register.\r | |
| 862 | \r | |
| 863 | @return The value written back to the PCI configuration register.\r | |
| 864 | \r | |
| 865 | **/\r | |
| 866 | UINT32\r | |
| 867 | EFIAPI\r | |
| 868 | PciOr32 (\r | |
| 869 | IN UINTN Address,\r | |
| 870 | IN UINT32 OrData\r | |
| 871 | )\r | |
| 872 | {\r | |
| 873 | return mRunningOnQ35 ?\r | |
| 874 | PciExpressOr32 (Address, OrData) :\r | |
| 875 | PciCf8Or32 (Address, OrData);\r | |
| 876 | }\r | |
| 877 | \r | |
| 878 | /**\r | |
| 879 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 880 | value.\r | |
| 881 | \r | |
| 882 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 883 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 884 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 885 | Address. The value written to the PCI configuration register is returned.\r | |
| 886 | This function must guarantee that all PCI read and write operations are\r | |
| 887 | serialized.\r | |
| 888 | \r | |
| 889 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 890 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 891 | \r | |
| 892 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 893 | Register.\r | |
| 894 | @param AndData The value to AND with the PCI configuration register.\r | |
| 895 | \r | |
| 896 | @return The value written back to the PCI configuration register.\r | |
| 897 | \r | |
| 898 | **/\r | |
| 899 | UINT32\r | |
| 900 | EFIAPI\r | |
| 901 | PciAnd32 (\r | |
| 902 | IN UINTN Address,\r | |
| 903 | IN UINT32 AndData\r | |
| 904 | )\r | |
| 905 | {\r | |
| 906 | return mRunningOnQ35 ?\r | |
| 907 | PciExpressAnd32 (Address, AndData) :\r | |
| 908 | PciCf8And32 (Address, AndData);\r | |
| 909 | }\r | |
| 910 | \r | |
| 911 | /**\r | |
| 912 | Performs a bitwise AND of a 32-bit PCI configuration register with a 32-bit\r | |
| 913 | value, followed a bitwise OR with another 32-bit value.\r | |
| 914 | \r | |
| 915 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 916 | bitwise AND between the read result and the value specified by AndData,\r | |
| 917 | performs a bitwise OR between the result of the AND operation and\r | |
| 918 | the value specified by OrData, and writes the result to the 32-bit PCI\r | |
| 919 | configuration register specified by Address. The value written to the PCI\r | |
| 920 | configuration register is returned. This function must guarantee that all PCI\r | |
| 921 | read and write operations are serialized.\r | |
| 922 | \r | |
| 923 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 924 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 925 | \r | |
| 926 | @param Address The address that encodes the PCI Bus, Device, Function and\r | |
| 927 | Register.\r | |
| 928 | @param AndData The value to AND with the PCI configuration register.\r | |
| 929 | @param OrData The value to OR with the result of the AND operation.\r | |
| 930 | \r | |
| 931 | @return The value written back to the PCI configuration register.\r | |
| 932 | \r | |
| 933 | **/\r | |
| 934 | UINT32\r | |
| 935 | EFIAPI\r | |
| 936 | PciAndThenOr32 (\r | |
| 937 | IN UINTN Address,\r | |
| 938 | IN UINT32 AndData,\r | |
| 939 | IN UINT32 OrData\r | |
| 940 | )\r | |
| 941 | {\r | |
| 942 | return mRunningOnQ35 ?\r | |
| 943 | PciExpressAndThenOr32 (Address, AndData, OrData) :\r | |
| 944 | PciCf8AndThenOr32 (Address, AndData, OrData);\r | |
| 945 | }\r | |
| 946 | \r | |
| 947 | /**\r | |
| 948 | Reads a bit field of a PCI configuration register.\r | |
| 949 | \r | |
| 950 | Reads the bit field in a 32-bit PCI configuration register. The bit field is\r | |
| 951 | specified by the StartBit and the EndBit. The value of the bit field is\r | |
| 952 | returned.\r | |
| 953 | \r | |
| 954 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 955 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 956 | If StartBit is greater than 31, then ASSERT().\r | |
| 957 | If EndBit is greater than 31, then ASSERT().\r | |
| 958 | If EndBit is less than StartBit, then ASSERT().\r | |
| 959 | \r | |
| 960 | @param Address The PCI configuration register to read.\r | |
| 961 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 962 | Range 0..31.\r | |
| 963 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 964 | Range 0..31.\r | |
| 965 | \r | |
| 966 | @return The value of the bit field read from the PCI configuration register.\r | |
| 967 | \r | |
| 968 | **/\r | |
| 969 | UINT32\r | |
| 970 | EFIAPI\r | |
| 971 | PciBitFieldRead32 (\r | |
| 972 | IN UINTN Address,\r | |
| 973 | IN UINTN StartBit,\r | |
| 974 | IN UINTN EndBit\r | |
| 975 | )\r | |
| 976 | {\r | |
| 977 | return mRunningOnQ35 ?\r | |
| 978 | PciExpressBitFieldRead32 (Address, StartBit, EndBit) :\r | |
| 979 | PciCf8BitFieldRead32 (Address, StartBit, EndBit);\r | |
| 980 | }\r | |
| 981 | \r | |
| 982 | /**\r | |
| 983 | Writes a bit field to a PCI configuration register.\r | |
| 984 | \r | |
| 985 | Writes Value to the bit field of the PCI configuration register. The bit\r | |
| 986 | field is specified by the StartBit and the EndBit. All other bits in the\r | |
| 987 | destination PCI configuration register are preserved. The new value of the\r | |
| 988 | 32-bit register is returned.\r | |
| 989 | \r | |
| 990 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 991 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 992 | If StartBit is greater than 31, then ASSERT().\r | |
| 993 | If EndBit is greater than 31, then ASSERT().\r | |
| 994 | If EndBit is less than StartBit, then ASSERT().\r | |
| 995 | If Value is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 996 | \r | |
| 997 | @param Address The PCI configuration register to write.\r | |
| 998 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 999 | Range 0..31.\r | |
| 1000 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1001 | Range 0..31.\r | |
| 1002 | @param Value The new value of the bit field.\r | |
| 1003 | \r | |
| 1004 | @return The value written back to the PCI configuration register.\r | |
| 1005 | \r | |
| 1006 | **/\r | |
| 1007 | UINT32\r | |
| 1008 | EFIAPI\r | |
| 1009 | PciBitFieldWrite32 (\r | |
| 1010 | IN UINTN Address,\r | |
| 1011 | IN UINTN StartBit,\r | |
| 1012 | IN UINTN EndBit,\r | |
| 1013 | IN UINT32 Value\r | |
| 1014 | )\r | |
| 1015 | {\r | |
| 1016 | return mRunningOnQ35 ?\r | |
| 1017 | PciExpressBitFieldWrite32 (Address, StartBit, EndBit, Value) :\r | |
| 1018 | PciCf8BitFieldWrite32 (Address, StartBit, EndBit, Value);\r | |
| 1019 | }\r | |
| 1020 | \r | |
| 1021 | /**\r | |
| 1022 | Reads a bit field in a 32-bit PCI configuration, performs a bitwise OR, and\r | |
| 1023 | writes the result back to the bit field in the 32-bit port.\r | |
| 1024 | \r | |
| 1025 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1026 | bitwise OR between the read result and the value specified by\r | |
| 1027 | OrData, and writes the result to the 32-bit PCI configuration register\r | |
| 1028 | specified by Address. The value written to the PCI configuration register is\r | |
| 1029 | returned. This function must guarantee that all PCI read and write operations\r | |
| 1030 | are serialized. Extra left bits in OrData are stripped.\r | |
| 1031 | \r | |
| 1032 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1033 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1034 | If StartBit is greater than 31, then ASSERT().\r | |
| 1035 | If EndBit is greater than 31, then ASSERT().\r | |
| 1036 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1037 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1038 | \r | |
| 1039 | @param Address The PCI configuration register to write.\r | |
| 1040 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1041 | Range 0..31.\r | |
| 1042 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1043 | Range 0..31.\r | |
| 1044 | @param OrData The value to OR with the PCI configuration register.\r | |
| 1045 | \r | |
| 1046 | @return The value written back to the PCI configuration register.\r | |
| 1047 | \r | |
| 1048 | **/\r | |
| 1049 | UINT32\r | |
| 1050 | EFIAPI\r | |
| 1051 | PciBitFieldOr32 (\r | |
| 1052 | IN UINTN Address,\r | |
| 1053 | IN UINTN StartBit,\r | |
| 1054 | IN UINTN EndBit,\r | |
| 1055 | IN UINT32 OrData\r | |
| 1056 | )\r | |
| 1057 | {\r | |
| 1058 | return mRunningOnQ35 ?\r | |
| 1059 | PciExpressBitFieldOr32 (Address, StartBit, EndBit, OrData) :\r | |
| 1060 | PciCf8BitFieldOr32 (Address, StartBit, EndBit, OrData);\r | |
| 1061 | }\r | |
| 1062 | \r | |
| 1063 | /**\r | |
| 1064 | Reads a bit field in a 32-bit PCI configuration register, performs a bitwise\r | |
| 1065 | AND, and writes the result back to the bit field in the 32-bit register.\r | |
| 1066 | \r | |
| 1067 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1068 | bitwise AND between the read result and the value specified by AndData, and\r | |
| 1069 | writes the result to the 32-bit PCI configuration register specified by\r | |
| 1070 | Address. The value written to the PCI configuration register is returned.\r | |
| 1071 | This function must guarantee that all PCI read and write operations are\r | |
| 1072 | serialized. Extra left bits in AndData are stripped.\r | |
| 1073 | \r | |
| 1074 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1075 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1076 | If StartBit is greater than 31, then ASSERT().\r | |
| 1077 | If EndBit is greater than 31, then ASSERT().\r | |
| 1078 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1079 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1080 | \r | |
| 1081 | @param Address The PCI configuration register to write.\r | |
| 1082 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1083 | Range 0..31.\r | |
| 1084 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1085 | Range 0..31.\r | |
| 1086 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1087 | \r | |
| 1088 | @return The value written back to the PCI configuration register.\r | |
| 1089 | \r | |
| 1090 | **/\r | |
| 1091 | UINT32\r | |
| 1092 | EFIAPI\r | |
| 1093 | PciBitFieldAnd32 (\r | |
| 1094 | IN UINTN Address,\r | |
| 1095 | IN UINTN StartBit,\r | |
| 1096 | IN UINTN EndBit,\r | |
| 1097 | IN UINT32 AndData\r | |
| 1098 | )\r | |
| 1099 | {\r | |
| 1100 | return mRunningOnQ35 ?\r | |
| 1101 | PciExpressBitFieldAnd32 (Address, StartBit, EndBit, AndData) :\r | |
| 1102 | PciCf8BitFieldAnd32 (Address, StartBit, EndBit, AndData);\r | |
| 1103 | }\r | |
| 1104 | \r | |
| 1105 | /**\r | |
| 1106 | Reads a bit field in a 32-bit port, performs a bitwise AND followed by a\r | |
| 1107 | bitwise OR, and writes the result back to the bit field in the\r | |
| 1108 | 32-bit port.\r | |
| 1109 | \r | |
| 1110 | Reads the 32-bit PCI configuration register specified by Address, performs a\r | |
| 1111 | bitwise AND followed by a bitwise OR between the read result and\r | |
| 1112 | the value specified by AndData, and writes the result to the 32-bit PCI\r | |
| 1113 | configuration register specified by Address. The value written to the PCI\r | |
| 1114 | configuration register is returned. This function must guarantee that all PCI\r | |
| 1115 | read and write operations are serialized. Extra left bits in both AndData and\r | |
| 1116 | OrData are stripped.\r | |
| 1117 | \r | |
| 1118 | If Address > 0x0FFFFFFF, then ASSERT().\r | |
| 1119 | If Address is not aligned on a 32-bit boundary, then ASSERT().\r | |
| 1120 | If StartBit is greater than 31, then ASSERT().\r | |
| 1121 | If EndBit is greater than 31, then ASSERT().\r | |
| 1122 | If EndBit is less than StartBit, then ASSERT().\r | |
| 1123 | If AndData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1124 | If OrData is larger than the bitmask value range specified by StartBit and EndBit, then ASSERT().\r | |
| 1125 | \r | |
| 1126 | @param Address The PCI configuration register to write.\r | |
| 1127 | @param StartBit The ordinal of the least significant bit in the bit field.\r | |
| 1128 | Range 0..31.\r | |
| 1129 | @param EndBit The ordinal of the most significant bit in the bit field.\r | |
| 1130 | Range 0..31.\r | |
| 1131 | @param AndData The value to AND with the PCI configuration register.\r | |
| 1132 | @param OrData The value to OR with the result of the AND operation.\r | |
| 1133 | \r | |
| 1134 | @return The value written back to the PCI configuration register.\r | |
| 1135 | \r | |
| 1136 | **/\r | |
| 1137 | UINT32\r | |
| 1138 | EFIAPI\r | |
| 1139 | PciBitFieldAndThenOr32 (\r | |
| 1140 | IN UINTN Address,\r | |
| 1141 | IN UINTN StartBit,\r | |
| 1142 | IN UINTN EndBit,\r | |
| 1143 | IN UINT32 AndData,\r | |
| 1144 | IN UINT32 OrData\r | |
| 1145 | )\r | |
| 1146 | {\r | |
| 1147 | return mRunningOnQ35 ?\r | |
| 1148 | PciExpressBitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData) :\r | |
| 1149 | PciCf8BitFieldAndThenOr32 (Address, StartBit, EndBit, AndData, OrData);\r | |
| 1150 | }\r | |
| 1151 | \r | |
| 1152 | /**\r | |
| 1153 | Reads a range of PCI configuration registers into a caller supplied buffer.\r | |
| 1154 | \r | |
| 1155 | Reads the range of PCI configuration registers specified by StartAddress and\r | |
| 1156 | Size into the buffer specified by Buffer. This function only allows the PCI\r | |
| 1157 | configuration registers from a single PCI function to be read. Size is\r | |
| 1158 | returned. When possible 32-bit PCI configuration read cycles are used to read\r | |
| 1159 | from StartAdress to StartAddress + Size. Due to alignment restrictions, 8-bit\r | |
| 1160 | and 16-bit PCI configuration read cycles may be used at the beginning and the\r | |
| 1161 | end of the range.\r | |
| 1162 | \r | |
| 1163 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1164 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1165 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1166 | \r | |
| 1167 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1168 | Function and Register.\r | |
| 1169 | @param Size The size in bytes of the transfer.\r | |
| 1170 | @param Buffer The pointer to a buffer receiving the data read.\r | |
| 1171 | \r | |
| 1172 | @return Size\r | |
| 1173 | \r | |
| 1174 | **/\r | |
| 1175 | UINTN\r | |
| 1176 | EFIAPI\r | |
| 1177 | PciReadBuffer (\r | |
| 1178 | IN UINTN StartAddress,\r | |
| 1179 | IN UINTN Size,\r | |
| 1180 | OUT VOID *Buffer\r | |
| 1181 | )\r | |
| 1182 | {\r | |
| 1183 | return mRunningOnQ35 ?\r | |
| 1184 | PciExpressReadBuffer (StartAddress, Size, Buffer) :\r | |
| 1185 | PciCf8ReadBuffer (StartAddress, Size, Buffer);\r | |
| 1186 | }\r | |
| 1187 | \r | |
| 1188 | /**\r | |
| 1189 | Copies the data in a caller supplied buffer to a specified range of PCI\r | |
| 1190 | configuration space.\r | |
| 1191 | \r | |
| 1192 | Writes the range of PCI configuration registers specified by StartAddress and\r | |
| 1193 | Size from the buffer specified by Buffer. This function only allows the PCI\r | |
| 1194 | configuration registers from a single PCI function to be written. Size is\r | |
| 1195 | returned. When possible 32-bit PCI configuration write cycles are used to\r | |
| 1196 | write from StartAdress to StartAddress + Size. Due to alignment restrictions,\r | |
| 1197 | 8-bit and 16-bit PCI configuration write cycles may be used at the beginning\r | |
| 1198 | and the end of the range.\r | |
| 1199 | \r | |
| 1200 | If StartAddress > 0x0FFFFFFF, then ASSERT().\r | |
| 1201 | If ((StartAddress & 0xFFF) + Size) > 0x1000, then ASSERT().\r | |
| 1202 | If Size > 0 and Buffer is NULL, then ASSERT().\r | |
| 1203 | \r | |
| 1204 | @param StartAddress The starting address that encodes the PCI Bus, Device,\r | |
| 1205 | Function and Register.\r | |
| 1206 | @param Size The size in bytes of the transfer.\r | |
| 1207 | @param Buffer The pointer to a buffer containing the data to write.\r | |
| 1208 | \r | |
| 1209 | @return Size written to StartAddress.\r | |
| 1210 | \r | |
| 1211 | **/\r | |
| 1212 | UINTN\r | |
| 1213 | EFIAPI\r | |
| 1214 | PciWriteBuffer (\r | |
| 1215 | IN UINTN StartAddress,\r | |
| 1216 | IN UINTN Size,\r | |
| 1217 | IN VOID *Buffer\r | |
| 1218 | )\r | |
| 1219 | {\r | |
| 1220 | return mRunningOnQ35 ?\r | |
| 1221 | PciExpressWriteBuffer (StartAddress, Size, Buffer) :\r | |
| 1222 | PciCf8WriteBuffer (StartAddress, Size, Buffer);\r | |
| 1223 | }\r |