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4fe26784 MX |
1 | /** @file\r |
2 | \r | |
3 | Copyright (c) 2021, Intel Corporation. All rights reserved.<BR>\r | |
4 | \r | |
5 | SPDX-License-Identifier: BSD-2-Clause-Patent\r | |
6 | \r | |
7 | **/\r | |
8 | \r | |
9 | #include <PiPei.h>\r | |
10 | #include <Library/BaseLib.h>\r | |
11 | #include <Library/BaseMemoryLib.h>\r | |
12 | #include <Library/MemoryAllocationLib.h>\r | |
13 | #include <Library/DebugLib.h>\r | |
14 | #include <Protocol/DebugSupport.h>\r | |
15 | #include <Library/TdxLib.h>\r | |
16 | #include <IndustryStandard/Tdx.h>\r | |
17 | #include <Library/PrePiLib.h>\r | |
18 | #include <Library/PeilessStartupLib.h>\r | |
19 | #include <Library/PlatformInitLib.h>\r | |
f41acc65 | 20 | #include <Library/TdxHelperLib.h>\r |
4fe26784 MX |
21 | #include <ConfidentialComputingGuestAttr.h>\r |
22 | #include <Guid/MemoryTypeInformation.h>\r | |
23 | #include <OvmfPlatforms.h>\r | |
24 | #include "PeilessStartupInternal.h"\r | |
25 | \r | |
26 | #define GET_GPAW_INIT_STATE(INFO) ((UINT8) ((INFO) & 0x3f))\r | |
27 | \r | |
28 | EFI_MEMORY_TYPE_INFORMATION mDefaultMemoryTypeInformation[] = {\r | |
29 | { EfiACPIMemoryNVS, 0x004 },\r | |
30 | { EfiACPIReclaimMemory, 0x008 },\r | |
31 | { EfiReservedMemoryType, 0x004 },\r | |
32 | { EfiRuntimeServicesData, 0x024 },\r | |
33 | { EfiRuntimeServicesCode, 0x030 },\r | |
34 | { EfiBootServicesCode, 0x180 },\r | |
35 | { EfiBootServicesData, 0xF00 },\r | |
36 | { EfiMaxMemoryType, 0x000 }\r | |
37 | };\r | |
38 | \r | |
39 | EFI_STATUS\r | |
40 | EFIAPI\r | |
41 | InitializePlatform (\r | |
42 | EFI_HOB_PLATFORM_INFO *PlatformInfoHob\r | |
43 | )\r | |
44 | {\r | |
124b7650 | 45 | VOID *VariableStore;\r |
4fe26784 MX |
46 | \r |
47 | DEBUG ((DEBUG_INFO, "InitializePlatform in Pei-less boot\n"));\r | |
48 | PlatformDebugDumpCmos ();\r | |
49 | \r | |
50 | PlatformInfoHob->DefaultMaxCpuNumber = 64;\r | |
51 | PlatformInfoHob->PcdPciMmio64Size = 0x800000000;\r | |
52 | \r | |
53 | PlatformInfoHob->HostBridgeDevId = PciRead16 (OVMF_HOSTBRIDGE_DID);\r | |
54 | DEBUG ((DEBUG_INFO, "HostBridgeDeviceId = 0x%x\n", PlatformInfoHob->HostBridgeDevId));\r | |
55 | \r | |
56 | PlatformAddressWidthInitialization (PlatformInfoHob);\r | |
57 | DEBUG ((\r | |
58 | DEBUG_INFO,\r | |
59 | "PhysMemAddressWidth=0x%x, Pci64Base=0x%llx, Pci64Size=0x%llx\n",\r | |
60 | PlatformInfoHob->PhysMemAddressWidth,\r | |
61 | PlatformInfoHob->PcdPciMmio64Base,\r | |
62 | PlatformInfoHob->PcdPciMmio64Size\r | |
63 | ));\r | |
64 | \r | |
65 | PlatformMaxCpuCountInitialization (PlatformInfoHob);\r | |
66 | DEBUG ((\r | |
67 | DEBUG_INFO,\r | |
68 | "MaxCpuCount=%d, BootCpuCount=%d\n",\r | |
69 | PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber,\r | |
70 | PlatformInfoHob->PcdCpuBootLogicalProcessorNumber\r | |
71 | ));\r | |
72 | \r | |
124b7650 | 73 | PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r |
4fe26784 MX |
74 | PlatformQemuUc32BaseInitialization (PlatformInfoHob);\r |
75 | DEBUG ((\r | |
76 | DEBUG_INFO,\r | |
77 | "Uc32Base = 0x%x, Uc32Size = 0x%x, LowerMemorySize = 0x%x\n",\r | |
78 | PlatformInfoHob->Uc32Base,\r | |
79 | PlatformInfoHob->Uc32Size,\r | |
124b7650 | 80 | PlatformInfoHob->LowMemory\r |
4fe26784 MX |
81 | ));\r |
82 | \r | |
ee91d9ef MX |
83 | VariableStore = PlatformReserveEmuVariableNvStore ();\r |
84 | PlatformInfoHob->PcdEmuVariableNvStoreReserved = (UINT64)(UINTN)VariableStore;\r | |
85 | #ifdef SECURE_BOOT_FEATURE_ENABLED\r | |
86 | PlatformInitEmuVariableNvStore (VariableStore);\r | |
87 | #endif\r | |
88 | \r | |
4fe26784 MX |
89 | if (TdIsEnabled ()) {\r |
90 | PlatformTdxPublishRamRegions ();\r | |
91 | } else {\r | |
92 | PlatformQemuInitializeRam (PlatformInfoHob);\r | |
93 | PlatformQemuInitializeRamForS3 (PlatformInfoHob);\r | |
94 | }\r | |
95 | \r | |
96 | //\r | |
97 | // Create Memory Type Information HOB\r | |
98 | //\r | |
99 | BuildGuidDataHob (\r | |
100 | &gEfiMemoryTypeInformationGuid,\r | |
101 | mDefaultMemoryTypeInformation,\r | |
102 | sizeof (mDefaultMemoryTypeInformation)\r | |
103 | );\r | |
104 | \r | |
105 | PlatformMemMapInitialization (PlatformInfoHob);\r | |
106 | \r | |
107 | PlatformNoexecDxeInitialization (PlatformInfoHob);\r | |
108 | \r | |
109 | if (TdIsEnabled ()) {\r | |
110 | PlatformInfoHob->PcdConfidentialComputingGuestAttr = CCAttrIntelTdx;\r | |
111 | PlatformInfoHob->PcdTdxSharedBitMask = TdSharedPageMask ();\r | |
112 | PlatformInfoHob->PcdSetNxForStack = TRUE;\r | |
113 | }\r | |
114 | \r | |
115 | PlatformMiscInitialization (PlatformInfoHob);\r | |
116 | \r | |
117 | return EFI_SUCCESS;\r | |
118 | }\r | |
119 | \r | |
120 | /**\r | |
121 | * This function brings up the Tdx guest from SEC phase to DXE phase.\r | |
122 | * PEI phase is skipped because most of the components in PEI phase\r | |
123 | * is not needed for Tdx guest, for example, MP Services, TPM etc.\r | |
124 | * In this way, the attack surfaces are reduced as much as possible.\r | |
125 | *\r | |
126 | * @param Context The pointer to the SecCoreData\r | |
127 | * @return VOID This function never returns\r | |
128 | */\r | |
129 | VOID\r | |
130 | EFIAPI\r | |
131 | PeilessStartup (\r | |
132 | IN VOID *Context\r | |
133 | )\r | |
134 | {\r | |
135 | EFI_SEC_PEI_HAND_OFF *SecCoreData;\r | |
136 | EFI_FIRMWARE_VOLUME_HEADER *BootFv;\r | |
137 | EFI_STATUS Status;\r | |
138 | EFI_HOB_PLATFORM_INFO PlatformInfoHob;\r | |
139 | UINT32 DxeCodeBase;\r | |
140 | UINT32 DxeCodeSize;\r | |
141 | TD_RETURN_DATA TdReturnData;\r | |
142 | VOID *VmmHobList;\r | |
143 | \r | |
144 | Status = EFI_SUCCESS;\r | |
145 | BootFv = NULL;\r | |
146 | VmmHobList = NULL;\r | |
147 | SecCoreData = (EFI_SEC_PEI_HAND_OFF *)Context;\r | |
148 | \r | |
149 | ZeroMem (&PlatformInfoHob, sizeof (PlatformInfoHob));\r | |
150 | \r | |
151 | if (TdIsEnabled ()) {\r | |
152 | VmmHobList = (VOID *)(UINTN)FixedPcdGet32 (PcdOvmfSecGhcbBase);\r | |
153 | Status = TdCall (TDCALL_TDINFO, 0, 0, 0, &TdReturnData);\r | |
154 | ASSERT (Status == EFI_SUCCESS);\r | |
155 | \r | |
156 | DEBUG ((\r | |
157 | DEBUG_INFO,\r | |
158 | "Tdx started with(Hob: 0x%x, Gpaw: 0x%x, Cpus: %d)\n",\r | |
159 | (UINT32)(UINTN)VmmHobList,\r | |
160 | GET_GPAW_INIT_STATE (TdReturnData.TdInfo.Gpaw),\r | |
161 | TdReturnData.TdInfo.NumVcpus\r | |
162 | ));\r | |
163 | \r | |
164 | Status = ConstructFwHobList (VmmHobList);\r | |
165 | } else {\r | |
166 | DEBUG ((DEBUG_INFO, "Ovmf started\n"));\r | |
167 | Status = ConstructSecHobList ();\r | |
168 | }\r | |
169 | \r | |
170 | if (EFI_ERROR (Status)) {\r | |
171 | ASSERT (FALSE);\r | |
172 | CpuDeadLoop ();\r | |
173 | }\r | |
174 | \r | |
175 | DEBUG ((DEBUG_INFO, "HobList: %p\n", GetHobList ()));\r | |
176 | \r | |
4b0a6226 MX |
177 | if (TdIsEnabled ()) {\r |
178 | //\r | |
019621d0 | 179 | // Build GuidHob for the tdx measurements which were done in SEC phase.\r |
4b0a6226 | 180 | //\r |
852ae4cd | 181 | Status = TdxHelperBuildGuidHobForTdxMeasurement ();\r |
4b0a6226 MX |
182 | if (EFI_ERROR (Status)) {\r |
183 | ASSERT (FALSE);\r | |
184 | CpuDeadLoop ();\r | |
185 | }\r | |
186 | }\r | |
187 | \r | |
4fe26784 MX |
188 | //\r |
189 | // Initialize the Platform\r | |
190 | //\r | |
191 | Status = InitializePlatform (&PlatformInfoHob);\r | |
192 | if (EFI_ERROR (Status)) {\r | |
193 | ASSERT (FALSE);\r | |
194 | CpuDeadLoop ();\r | |
195 | }\r | |
196 | \r | |
197 | BuildGuidDataHob (&gUefiOvmfPkgPlatformInfoGuid, &PlatformInfoHob, sizeof (EFI_HOB_PLATFORM_INFO));\r | |
198 | \r | |
199 | //\r | |
200 | // SecFV\r | |
201 | //\r | |
202 | BootFv = (EFI_FIRMWARE_VOLUME_HEADER *)SecCoreData->BootFirmwareVolumeBase;\r | |
203 | BuildFvHob ((UINTN)BootFv, BootFv->FvLength);\r | |
204 | \r | |
205 | //\r | |
206 | // DxeFV\r | |
207 | //\r | |
208 | DxeCodeBase = PcdGet32 (PcdBfvBase);\r | |
209 | DxeCodeSize = PcdGet32 (PcdBfvRawDataSize) - (UINT32)BootFv->FvLength;\r | |
210 | BuildFvHob (DxeCodeBase, DxeCodeSize);\r | |
211 | \r | |
212 | DEBUG ((DEBUG_INFO, "SecFv : %p, 0x%x\n", BootFv, BootFv->FvLength));\r | |
213 | DEBUG ((DEBUG_INFO, "DxeFv : %x, 0x%x\n", DxeCodeBase, DxeCodeSize));\r | |
214 | \r | |
215 | BuildStackHob ((UINTN)SecCoreData->StackBase, SecCoreData->StackSize <<= 1);\r | |
216 | \r | |
217 | BuildResourceDescriptorHob (\r | |
218 | EFI_RESOURCE_SYSTEM_MEMORY,\r | |
219 | EFI_RESOURCE_ATTRIBUTE_PRESENT |\r | |
220 | EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r | |
221 | EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r | |
222 | EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r | |
223 | EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r | |
224 | EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r | |
225 | EFI_RESOURCE_ATTRIBUTE_TESTED,\r | |
226 | (UINT64)SecCoreData->TemporaryRamBase,\r | |
227 | (UINT64)SecCoreData->TemporaryRamSize\r | |
228 | );\r | |
229 | \r | |
230 | //\r | |
231 | // Load the DXE Core and transfer control to it.\r | |
232 | // Only DxeFV is in the compressed section.\r | |
233 | //\r | |
234 | Status = DxeLoadCore (1);\r | |
235 | \r | |
236 | //\r | |
237 | // Never arrive here.\r | |
238 | //\r | |
239 | ASSERT (FALSE);\r | |
240 | CpuDeadLoop ();\r | |
241 | }\r |