[mirror_edk2.git] / OvmfPkg / Library / PlatformInitLib / MemDetect.c

/**@file\r
  Memory Detection for Virtual Machines.\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
Module Name:\r
\r
  MemDetect.c\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <IndustryStandard/E820.h>\r
#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/CloudHv.h>\r
#include <IndustryStandard/Xen/arch-x86/hvm/start_info.h>\r
#include <PiPei.h>\r
#include <Register/Intel/SmramSaveStateMap.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseLib.h>\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/CcProbeLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HardwareInfoLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <Library/MemEncryptSevLib.h>\r
#include <Library/PcdLib.h>\r
#include <Library/PciLib.h>\r
#include <Library/PeimEntryPoint.h>\r
#include <Library/ResourcePublicationLib.h>\r
#include <Library/MtrrLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include <Library/TdxLib.h>\r
\r
#include <Library/PlatformInitLib.h>\r
\r
#define MEGABYTE_SHIFT  20\r
\r
VOID\r
EFIAPI\r
PlatformQemuUc32BaseInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT32  LowerMemorySize;\r
\r
  if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
    return;\r
  }\r
\r
  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
    ASSERT (PcdGet64 (PcdPciExpressBaseAddress) <= MAX_UINT32);\r
    ASSERT (PcdGet64 (PcdPciExpressBaseAddress) >= LowerMemorySize);\r
\r
    if (LowerMemorySize <= BASE_2GB) {\r
      // Newer qemu with gigabyte aligned memory,\r
      // 32-bit pci mmio window is 2G -> 4G then.\r
      PlatformInfoHob->Uc32Base = BASE_2GB;\r
    } else {\r
      //\r
      // On q35, the 32-bit area that we'll mark as UC, through variable MTRRs,\r
      // starts at PcdPciExpressBaseAddress. The platform DSC is responsible for\r
      // setting PcdPciExpressBaseAddress such that describing the\r
      // [PcdPciExpressBaseAddress, 4GB) range require a very small number of\r
      // variable MTRRs (preferably 1 or 2).\r
      //\r
      PlatformInfoHob->Uc32Base = (UINT32)PcdGet64 (PcdPciExpressBaseAddress);\r
    }\r
\r
    return;\r
  }\r
\r
  if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {\r
    PlatformInfoHob->Uc32Size = CLOUDHV_MMIO_HOLE_SIZE;\r
    PlatformInfoHob->Uc32Base = CLOUDHV_MMIO_HOLE_ADDRESS;\r
    return;\r
  }\r
\r
  ASSERT (PlatformInfoHob->HostBridgeDevId == INTEL_82441_DEVICE_ID);\r
  //\r
  // On i440fx, start with the [LowerMemorySize, 4GB) range. Make sure one\r
  // variable MTRR suffices by truncating the size to a whole power of two,\r
  // while keeping the end affixed to 4GB. This will round the base up.\r
  //\r
  LowerMemorySize           = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
  PlatformInfoHob->Uc32Size = GetPowerOfTwo32 ((UINT32)(SIZE_4GB - LowerMemorySize));\r
  PlatformInfoHob->Uc32Base = (UINT32)(SIZE_4GB - PlatformInfoHob->Uc32Size);\r
  //\r
  // Assuming that LowerMemorySize is at least 1 byte, Uc32Size is at most 2GB.\r
  // Therefore Uc32Base is at least 2GB.\r
  //\r
  ASSERT (PlatformInfoHob->Uc32Base >= BASE_2GB);\r
\r
  if (PlatformInfoHob->Uc32Base != LowerMemorySize) {\r
    DEBUG ((\r
      DEBUG_VERBOSE,\r
      "%a: rounded UC32 base from 0x%x up to 0x%x, for "\r
      "an UC32 size of 0x%x\n",\r
      __FUNCTION__,\r
      LowerMemorySize,\r
      PlatformInfoHob->Uc32Base,\r
      PlatformInfoHob->Uc32Size\r
      ));\r
  }\r
}\r
\r
/**\r
  Iterate over the RAM entries in QEMU's fw_cfg E820 RAM map that start outside\r
  of the 32-bit address range.\r
\r
  Find the highest exclusive >=4GB RAM address, or produce memory resource\r
  descriptor HOBs for RAM entries that start at or above 4GB.\r
\r
  @param[out] MaxAddress  If MaxAddress is NULL, then PlatformScanOrAdd64BitE820Ram()\r
                          produces memory resource descriptor HOBs for RAM\r
                          entries that start at or above 4GB.\r
\r
                          Otherwise, MaxAddress holds the highest exclusive\r
                          >=4GB RAM address on output. If QEMU's fw_cfg E820\r
                          RAM map contains no RAM entry that starts outside of\r
                          the 32-bit address range, then MaxAddress is exactly\r
                          4GB on output.\r
\r
  @retval EFI_SUCCESS         The fw_cfg E820 RAM map was found and processed.\r
\r
  @retval EFI_PROTOCOL_ERROR  The RAM map was found, but its size wasn't a\r
                              whole multiple of sizeof(EFI_E820_ENTRY64). No\r
                              RAM entry was processed.\r
\r
  @return                     Error codes from QemuFwCfgFindFile(). No RAM\r
                              entry was processed.\r
**/\r
STATIC\r
EFI_STATUS\r
PlatformScanOrAdd64BitE820Ram (\r
  IN BOOLEAN  AddHighHob,\r
  OUT UINT64  *LowMemory OPTIONAL,\r
  OUT UINT64  *MaxAddress OPTIONAL\r
  )\r
{\r
  EFI_STATUS            Status;\r
  FIRMWARE_CONFIG_ITEM  FwCfgItem;\r
  UINTN                 FwCfgSize;\r
  EFI_E820_ENTRY64      E820Entry;\r
  UINTN                 Processed;\r
\r
  Status = QemuFwCfgFindFile ("etc/e820", &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  if (FwCfgSize % sizeof E820Entry != 0) {\r
    return EFI_PROTOCOL_ERROR;\r
  }\r
\r
  if (LowMemory != NULL) {\r
    *LowMemory = 0;\r
  }\r
\r
  if (MaxAddress != NULL) {\r
    *MaxAddress = BASE_4GB;\r
  }\r
\r
  QemuFwCfgSelectItem (FwCfgItem);\r
  for (Processed = 0; Processed < FwCfgSize; Processed += sizeof E820Entry) {\r
    QemuFwCfgReadBytes (sizeof E820Entry, &E820Entry);\r
    DEBUG ((\r
      DEBUG_VERBOSE,\r
      "%a: Base=0x%Lx Length=0x%Lx Type=%u\n",\r
      __FUNCTION__,\r
      E820Entry.BaseAddr,\r
      E820Entry.Length,\r
      E820Entry.Type\r
      ));\r
    if (E820Entry.Type == EfiAcpiAddressRangeMemory) {\r
      if (AddHighHob && (E820Entry.BaseAddr >= BASE_4GB)) {\r
        UINT64  Base;\r
        UINT64  End;\r
\r
        //\r
        // Round up the start address, and round down the end address.\r
        //\r
        Base = ALIGN_VALUE (E820Entry.BaseAddr, (UINT64)EFI_PAGE_SIZE);\r
        End  = (E820Entry.BaseAddr + E820Entry.Length) &\r
               ~(UINT64)EFI_PAGE_MASK;\r
        if (Base < End) {\r
          PlatformAddMemoryRangeHob (Base, End);\r
          DEBUG ((\r
            DEBUG_VERBOSE,\r
            "%a: PlatformAddMemoryRangeHob [0x%Lx, 0x%Lx)\n",\r
            __FUNCTION__,\r
            Base,\r
            End\r
            ));\r
        }\r
      }\r
\r
      if (MaxAddress || LowMemory) {\r
        UINT64  Candidate;\r
\r
        Candidate = E820Entry.BaseAddr + E820Entry.Length;\r
        if (MaxAddress && (Candidate > *MaxAddress)) {\r
          *MaxAddress = Candidate;\r
          DEBUG ((\r
            DEBUG_VERBOSE,\r
            "%a: MaxAddress=0x%Lx\n",\r
            __FUNCTION__,\r
            *MaxAddress\r
            ));\r
        }\r
\r
        if (LowMemory && (Candidate > *LowMemory) && (Candidate < BASE_4GB)) {\r
          *LowMemory = Candidate;\r
          DEBUG ((\r
            DEBUG_VERBOSE,\r
            "%a: LowMemory=0x%Lx\n",\r
            __FUNCTION__,\r
            *LowMemory\r
            ));\r
        }\r
      }\r
    } else if (E820Entry.Type == EfiAcpiAddressRangeReserved) {\r
      if (AddHighHob) {\r
        DEBUG ((\r
          DEBUG_INFO,\r
          "%a: Reserved: Base=0x%Lx Length=0x%Lx\n",\r
          __FUNCTION__,\r
          E820Entry.BaseAddr,\r
          E820Entry.Length\r
          ));\r
        BuildResourceDescriptorHob (\r
          EFI_RESOURCE_MEMORY_RESERVED,\r
          0,\r
          E820Entry.BaseAddr,\r
          E820Entry.Length\r
          );\r
      }\r
    }\r
  }\r
\r
  return EFI_SUCCESS;\r
}\r
\r
/**\r
  Returns PVH memmap\r
\r
  @param Entries      Pointer to PVH memmap\r
  @param Count        Number of entries\r
\r
  @return EFI_STATUS\r
**/\r
EFI_STATUS\r
GetPvhMemmapEntries (\r
  struct hvm_memmap_table_entry  **Entries,\r
  UINT32                         *Count\r
  )\r
{\r
  UINT32                 *PVHResetVectorData;\r
  struct hvm_start_info  *pvh_start_info;\r
\r
  PVHResetVectorData = (VOID *)(UINTN)PcdGet32 (PcdXenPvhStartOfDayStructPtr);\r
  if (PVHResetVectorData == 0) {\r
    return EFI_NOT_FOUND;\r
  }\r
\r
  pvh_start_info = (struct hvm_start_info *)(UINTN)PVHResetVectorData[0];\r
\r
  *Entries = (struct hvm_memmap_table_entry *)(UINTN)pvh_start_info->memmap_paddr;\r
  *Count   = pvh_start_info->memmap_entries;\r
\r
  return EFI_SUCCESS;\r
}\r
\r
STATIC\r
UINT64\r
GetHighestSystemMemoryAddressFromPvhMemmap (\r
  BOOLEAN  Below4gb\r
  )\r
{\r
  struct hvm_memmap_table_entry  *Memmap;\r
  UINT32                         MemmapEntriesCount;\r
  struct hvm_memmap_table_entry  *Entry;\r
  EFI_STATUS                     Status;\r
  UINT32                         Loop;\r
  UINT64                         HighestAddress;\r
  UINT64                         EntryEnd;\r
\r
  HighestAddress = 0;\r
\r
  Status = GetPvhMemmapEntries (&Memmap, &MemmapEntriesCount);\r
  ASSERT_EFI_ERROR (Status);\r
\r
  for (Loop = 0; Loop < MemmapEntriesCount; Loop++) {\r
    Entry    = Memmap + Loop;\r
    EntryEnd = Entry->addr + Entry->size;\r
\r
    if ((Entry->type == XEN_HVM_MEMMAP_TYPE_RAM) &&\r
        (EntryEnd > HighestAddress))\r
    {\r
      if (Below4gb && (EntryEnd <= BASE_4GB)) {\r
        HighestAddress = EntryEnd;\r
      } else if (!Below4gb && (EntryEnd >= BASE_4GB)) {\r
        HighestAddress = EntryEnd;\r
      }\r
    }\r
  }\r
\r
  return HighestAddress;\r
}\r
\r
UINT32\r
EFIAPI\r
PlatformGetSystemMemorySizeBelow4gb (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  EFI_STATUS  Status;\r
  UINT64      LowerMemorySize = 0;\r
  UINT8       Cmos0x34;\r
  UINT8       Cmos0x35;\r
\r
  if ((PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) &&\r
      (CcProbe () != CcGuestTypeIntelTdx))\r
  {\r
    // Get the information from PVH memmap\r
    return (UINT32)GetHighestSystemMemoryAddressFromPvhMemmap (TRUE);\r
  }\r
\r
  Status = PlatformScanOrAdd64BitE820Ram (FALSE, &LowerMemorySize, NULL);\r
  if ((Status == EFI_SUCCESS) && (LowerMemorySize > 0)) {\r
    return (UINT32)LowerMemorySize;\r
  }\r
\r
  //\r
  // CMOS 0x34/0x35 specifies the system memory above 16 MB.\r
  // * CMOS(0x35) is the high byte\r
  // * CMOS(0x34) is the low byte\r
  // * The size is specified in 64kb chunks\r
  // * Since this is memory above 16MB, the 16MB must be added\r
  //   into the calculation to get the total memory size.\r
  //\r
\r
  Cmos0x34 = (UINT8)PlatformCmosRead8 (0x34);\r
  Cmos0x35 = (UINT8)PlatformCmosRead8 (0x35);\r
\r
  return (UINT32)(((UINTN)((Cmos0x35 << 8) + Cmos0x34) << 16) + SIZE_16MB);\r
}\r
\r
STATIC\r
UINT64\r
PlatformGetSystemMemorySizeAbove4gb (\r
  )\r
{\r
  UINT32  Size;\r
  UINTN   CmosIndex;\r
\r
  //\r
  // CMOS 0x5b-0x5d specifies the system memory above 4GB MB.\r
  // * CMOS(0x5d) is the most significant size byte\r
  // * CMOS(0x5c) is the middle size byte\r
  // * CMOS(0x5b) is the least significant size byte\r
  // * The size is specified in 64kb chunks\r
  //\r
\r
  Size = 0;\r
  for (CmosIndex = 0x5d; CmosIndex >= 0x5b; CmosIndex--) {\r
    Size = (UINT32)(Size << 8) + (UINT32)PlatformCmosRead8 (CmosIndex);\r
  }\r
\r
  return LShiftU64 (Size, 16);\r
}\r
\r
/**\r
  Return the highest address that DXE could possibly use, plus one.\r
**/\r
STATIC\r
UINT64\r
PlatformGetFirstNonAddress (\r
  IN OUT  EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT64                FirstNonAddress;\r
  UINT32                FwCfgPciMmio64Mb;\r
  EFI_STATUS            Status;\r
  FIRMWARE_CONFIG_ITEM  FwCfgItem;\r
  UINTN                 FwCfgSize;\r
  UINT64                HotPlugMemoryEnd;\r
\r
  //\r
  // set FirstNonAddress to suppress incorrect compiler/analyzer warnings\r
  //\r
  FirstNonAddress = 0;\r
\r
  //\r
  // If QEMU presents an E820 map, then get the highest exclusive >=4GB RAM\r
  // address from it. This can express an address >= 4GB+1TB.\r
  //\r
  // Otherwise, get the flat size of the memory above 4GB from the CMOS (which\r
  // can only express a size smaller than 1TB), and add it to 4GB.\r
  //\r
  Status = PlatformScanOrAdd64BitE820Ram (FALSE, NULL, &FirstNonAddress);\r
  if (EFI_ERROR (Status)) {\r
    FirstNonAddress = BASE_4GB + PlatformGetSystemMemorySizeAbove4gb ();\r
  }\r
\r
  //\r
  // If DXE is 32-bit, then we're done; PciBusDxe will degrade 64-bit MMIO\r
  // resources to 32-bit anyway. See DegradeResource() in\r
  // "PciResourceSupport.c".\r
  //\r
 #ifdef MDE_CPU_IA32\r
  if (!FeaturePcdGet (PcdDxeIplSwitchToLongMode)) {\r
    return FirstNonAddress;\r
  }\r
\r
 #endif\r
\r
  //\r
  // See if the user specified the number of megabytes for the 64-bit PCI host\r
  // aperture. Accept an aperture size up to 16TB.\r
  //\r
  // As signaled by the "X-" prefix, this knob is experimental, and might go\r
  // away at any time.\r
  //\r
  Status = QemuFwCfgParseUint32 (\r
             "opt/ovmf/X-PciMmio64Mb",\r
             FALSE,\r
             &FwCfgPciMmio64Mb\r
             );\r
  switch (Status) {\r
    case EFI_UNSUPPORTED:\r
    case EFI_NOT_FOUND:\r
      break;\r
    case EFI_SUCCESS:\r
      if (FwCfgPciMmio64Mb <= 0x1000000) {\r
        PlatformInfoHob->PcdPciMmio64Size = LShiftU64 (FwCfgPciMmio64Mb, 20);\r
        break;\r
      }\r
\r
    //\r
    // fall through\r
    //\r
    default:\r
      DEBUG ((\r
        DEBUG_WARN,\r
        "%a: ignoring malformed 64-bit PCI host aperture size from fw_cfg\n",\r
        __FUNCTION__\r
        ));\r
      break;\r
  }\r
\r
  if (PlatformInfoHob->PcdPciMmio64Size == 0) {\r
    if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
      DEBUG ((\r
        DEBUG_INFO,\r
        "%a: disabling 64-bit PCI host aperture\n",\r
        __FUNCTION__\r
        ));\r
    }\r
\r
    //\r
    // There's nothing more to do; the amount of memory above 4GB fully\r
    // determines the highest address plus one. The memory hotplug area (see\r
    // below) plays no role for the firmware in this case.\r
    //\r
    return FirstNonAddress;\r
  }\r
\r
  //\r
  // The "etc/reserved-memory-end" fw_cfg file, when present, contains an\r
  // absolute, exclusive end address for the memory hotplug area. This area\r
  // starts right at the end of the memory above 4GB. The 64-bit PCI host\r
  // aperture must be placed above it.\r
  //\r
  Status = QemuFwCfgFindFile (\r
             "etc/reserved-memory-end",\r
             &FwCfgItem,\r
             &FwCfgSize\r
             );\r
  if (!EFI_ERROR (Status) && (FwCfgSize == sizeof HotPlugMemoryEnd)) {\r
    QemuFwCfgSelectItem (FwCfgItem);\r
    QemuFwCfgReadBytes (FwCfgSize, &HotPlugMemoryEnd);\r
    DEBUG ((\r
      DEBUG_VERBOSE,\r
      "%a: HotPlugMemoryEnd=0x%Lx\n",\r
      __FUNCTION__,\r
      HotPlugMemoryEnd\r
      ));\r
\r
    ASSERT (HotPlugMemoryEnd >= FirstNonAddress);\r
    FirstNonAddress = HotPlugMemoryEnd;\r
  }\r
\r
  //\r
  // SeaBIOS aligns both boundaries of the 64-bit PCI host aperture to 1GB, so\r
  // that the host can map it with 1GB hugepages. Follow suit.\r
  //\r
  PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (FirstNonAddress, (UINT64)SIZE_1GB);\r
  PlatformInfoHob->PcdPciMmio64Size = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Size, (UINT64)SIZE_1GB);\r
\r
  //\r
  // The 64-bit PCI host aperture should also be "naturally" aligned. The\r
  // alignment is determined by rounding the size of the aperture down to the\r
  // next smaller or equal power of two. That is, align the aperture by the\r
  // largest BAR size that can fit into it.\r
  //\r
  PlatformInfoHob->PcdPciMmio64Base = ALIGN_VALUE (PlatformInfoHob->PcdPciMmio64Base, GetPowerOfTwo64 (PlatformInfoHob->PcdPciMmio64Size));\r
\r
  //\r
  // The useful address space ends with the 64-bit PCI host aperture.\r
  //\r
  FirstNonAddress = PlatformInfoHob->PcdPciMmio64Base + PlatformInfoHob->PcdPciMmio64Size;\r
  return FirstNonAddress;\r
}\r
\r
/*\r
 * Use CPUID to figure physical address width.\r
 *\r
 * Does *not* work reliable on qemu.  For historical reasons qemu\r
 * returns phys-bits=40 by default even in case the host machine\r
 * supports less than that.\r
 *\r
 * So we apply the following rules (which can be enabled/disabled\r
 * using the QemuQuirk parameter) to figure whenever we can work with\r
 * the returned physical address width or not:\r
 *\r
 *   (1) If it is 41 or higher consider it valid.\r
 *   (2) If it is 40 or lower consider it valid in case it matches a\r
 *       known-good value for the CPU vendor, which is:\r
 *         ->  36 or 39 for Intel\r
 *         ->  40 for AMD\r
 *   (3) Otherwise consider it invalid.\r
 *\r
 * Recommendation: Run qemu with host-phys-bits=on.  That will make\r
 * sure guest phys-bits is not larger than host phys-bits.  Some\r
 * distro builds do that by default.\r
 */\r
VOID\r
EFIAPI\r
PlatformAddressWidthFromCpuid (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob,\r
  IN     BOOLEAN                QemuQuirk\r
  )\r
{\r
  UINT32   RegEax, RegEbx, RegEcx, RegEdx, Max;\r
  UINT8    PhysBits;\r
  CHAR8    Signature[13] = { 0 };\r
  BOOLEAN  Valid         = FALSE;\r
  BOOLEAN  Page1GSupport = FALSE;\r
\r
  AsmCpuid (0x80000000, &RegEax, &RegEbx, &RegEcx, &RegEdx);\r
  *(UINT32 *)(Signature + 0) = RegEbx;\r
  *(UINT32 *)(Signature + 4) = RegEdx;\r
  *(UINT32 *)(Signature + 8) = RegEcx;\r
  Max                        = RegEax;\r
\r
  if (Max >= 0x80000001) {\r
    AsmCpuid (0x80000001, NULL, NULL, NULL, &RegEdx);\r
    if ((RegEdx & BIT26) != 0) {\r
      Page1GSupport = TRUE;\r
    }\r
  }\r
\r
  if (Max >= 0x80000008) {\r
    AsmCpuid (0x80000008, &RegEax, NULL, NULL, NULL);\r
    PhysBits = (UINT8)RegEax;\r
  } else {\r
    PhysBits = 36;\r
  }\r
\r
  if (!QemuQuirk) {\r
    Valid = TRUE;\r
  } else if (PhysBits >= 41) {\r
    Valid = TRUE;\r
  } else if (AsciiStrCmp (Signature, "GenuineIntel") == 0) {\r
    if ((PhysBits == 36) || (PhysBits == 39)) {\r
      Valid = TRUE;\r
    }\r
  } else if (AsciiStrCmp (Signature, "AuthenticAMD") == 0) {\r
    if (PhysBits == 40) {\r
      Valid = TRUE;\r
    }\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: Signature: '%a', PhysBits: %d, QemuQuirk: %a, Valid: %a\n",\r
    __FUNCTION__,\r
    Signature,\r
    PhysBits,\r
    QemuQuirk ? "On" : "Off",\r
    Valid ? "Yes" : "No"\r
    ));\r
\r
  if (Valid) {\r
    if (PhysBits > 47) {\r
      /*\r
       * Avoid 5-level paging altogether for now, which limits\r
       * PhysBits to 48.  Also avoid using address bit 48, due to sign\r
       * extension we can't identity-map these addresses (and lots of\r
       * places in edk2 assume we have everything identity-mapped).\r
       * So the actual limit is 47.\r
       */\r
      DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 47 (avoid 5-level paging)\n", __func__));\r
      PhysBits = 47;\r
    }\r
\r
    if (!Page1GSupport && (PhysBits > 40)) {\r
      DEBUG ((DEBUG_INFO, "%a: limit PhysBits to 40 (no 1G pages available)\n", __func__));\r
      PhysBits = 40;\r
    }\r
\r
    PlatformInfoHob->PhysMemAddressWidth = PhysBits;\r
    PlatformInfoHob->FirstNonAddress     = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
PlatformDynamicMmioWindow (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT64  AddrSpace, MmioSpace;\r
\r
  AddrSpace = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth);\r
  MmioSpace = LShiftU64 (1, PlatformInfoHob->PhysMemAddressWidth - 3);\r
\r
  if ((PlatformInfoHob->PcdPciMmio64Size < MmioSpace) &&\r
      (PlatformInfoHob->PcdPciMmio64Base + MmioSpace < AddrSpace))\r
  {\r
    DEBUG ((DEBUG_INFO, "%a: using dynamic mmio window\n", __func__));\r
    DEBUG ((DEBUG_INFO, "%a:   Addr Space 0x%Lx (%Ld GB)\n", __func__, AddrSpace, RShiftU64 (AddrSpace, 30)));\r
    DEBUG ((DEBUG_INFO, "%a:   MMIO Space 0x%Lx (%Ld GB)\n", __func__, MmioSpace, RShiftU64 (MmioSpace, 30)));\r
    PlatformInfoHob->PcdPciMmio64Size = MmioSpace;\r
    PlatformInfoHob->PcdPciMmio64Base = AddrSpace - MmioSpace;\r
  } else {\r
    DEBUG ((DEBUG_INFO, "%a: using classic mmio window\n", __func__));\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "%a:   Pci64 Base 0x%Lx\n", __func__, PlatformInfoHob->PcdPciMmio64Base));\r
  DEBUG ((DEBUG_INFO, "%a:   Pci64 Size 0x%Lx\n", __func__, PlatformInfoHob->PcdPciMmio64Size));\r
}\r
\r
/**\r
  Iterate over the PCI host bridges resources information optionally provided\r
  in fw-cfg and find the highest address contained in the PCI MMIO windows. If\r
  the information is found, return the exclusive end; one past the last usable\r
  address.\r
\r
  @param[out] PciMmioAddressEnd Pointer to one-after End Address updated with\r
                                information extracted from host-provided data\r
                                or zero if no information available or an\r
                                error happened\r
\r
  @retval EFI_SUCCESS               PCI information was read and the output\r
                                    parameter updated with the last valid\r
                                    address in the 64-bit MMIO range.\r
  @retval EFI_INVALID_PARAMETER     Pointer parameter is invalid\r
  @retval EFI_INCOMPATIBLE_VERSION  Hardware information found in fw-cfg\r
                                    has an incompatible format\r
  @retval EFI_UNSUPPORTED           Fw-cfg is not supported, thus host\r
                                    provided information, if any, cannot be\r
                                    read\r
  @retval EFI_NOT_FOUND             No PCI host bridge information provided\r
                                    by the host.\r
**/\r
STATIC\r
EFI_STATUS\r
PlatformScanHostProvided64BitPciMmioEnd (\r
  OUT UINT64  *PciMmioAddressEnd\r
  )\r
{\r
  EFI_STATUS            Status;\r
  HOST_BRIDGE_INFO      HostBridge;\r
  FIRMWARE_CONFIG_ITEM  FwCfgItem;\r
  UINTN                 FwCfgSize;\r
  UINTN                 FwCfgReadIndex;\r
  UINTN                 ReadDataSize;\r
  UINT64                Above4GMmioEnd;\r
\r
  if (PciMmioAddressEnd == NULL) {\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  *PciMmioAddressEnd = 0;\r
  Above4GMmioEnd     = 0;\r
\r
  Status = QemuFwCfgFindFile ("etc/hardware-info", &FwCfgItem, &FwCfgSize);\r
  if (EFI_ERROR (Status)) {\r
    return Status;\r
  }\r
\r
  QemuFwCfgSelectItem (FwCfgItem);\r
\r
  FwCfgReadIndex = 0;\r
  while (FwCfgReadIndex < FwCfgSize) {\r
    Status = QemuFwCfgReadNextHardwareInfoByType (\r
               HardwareInfoTypeHostBridge,\r
               sizeof (HostBridge),\r
               FwCfgSize,\r
               &HostBridge,\r
               &ReadDataSize,\r
               &FwCfgReadIndex\r
               );\r
\r
    if (Status != EFI_SUCCESS) {\r
      //\r
      // No more data available to read in the file, break\r
      // loop and finish process\r
      //\r
      break;\r
    }\r
\r
    Status = HardwareInfoPciHostBridgeLastMmioAddress (\r
               &HostBridge,\r
               ReadDataSize,\r
               TRUE,\r
               &Above4GMmioEnd\r
               );\r
\r
    if (Status != EFI_SUCCESS) {\r
      //\r
      // Error parsing MMIO apertures and extracting last MMIO\r
      // address, reset PciMmioAddressEnd as if no information was\r
      // found, to avoid moving forward with incomplete data, and\r
      // bail out\r
      //\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: ignoring malformed hardware information from fw_cfg\n",\r
        __FUNCTION__\r
        ));\r
      *PciMmioAddressEnd = 0;\r
      return Status;\r
    }\r
\r
    if (Above4GMmioEnd > *PciMmioAddressEnd) {\r
      *PciMmioAddressEnd = Above4GMmioEnd;\r
    }\r
  }\r
\r
  if (*PciMmioAddressEnd > 0) {\r
    //\r
    // Host-provided PCI information was found and a MMIO window end\r
    // derived from it.\r
    // Increase the End address by one to have the output pointing to\r
    // one after the address in use (exclusive end).\r
    //\r
    *PciMmioAddressEnd += 1;\r
\r
    DEBUG ((\r
      DEBUG_INFO,\r
      "%a: Pci64End=0x%Lx\n",\r
      __FUNCTION__,\r
      *PciMmioAddressEnd\r
      ));\r
\r
    return EFI_SUCCESS;\r
  }\r
\r
  return EFI_NOT_FOUND;\r
}\r
\r
/**\r
  Initialize the PhysMemAddressWidth field in PlatformInfoHob based on guest RAM size.\r
**/\r
VOID\r
EFIAPI\r
PlatformAddressWidthInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT64      FirstNonAddress;\r
  UINT8       PhysMemAddressWidth;\r
  EFI_STATUS  Status;\r
\r
  if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
    PlatformAddressWidthFromCpuid (PlatformInfoHob, FALSE);\r
    return;\r
  }\r
\r
  //\r
  // First scan host-provided hardware information to assess if the address\r
  // space is already known. If so, guest must use those values.\r
  //\r
  Status = PlatformScanHostProvided64BitPciMmioEnd (&FirstNonAddress);\r
\r
  if (EFI_ERROR (Status)) {\r
    //\r
    // If the host did not provide valid hardware information leading to a\r
    // hard-defined 64-bit MMIO end, fold back to calculating the minimum range\r
    // needed.\r
    // As guest-physical memory size grows, the permanent PEI RAM requirements\r
    // are dominated by the identity-mapping page tables built by the DXE IPL.\r
    // The DXL IPL keys off of the physical address bits advertized in the CPU\r
    // HOB. To conserve memory, we calculate the minimum address width here.\r
    //\r
    FirstNonAddress = PlatformGetFirstNonAddress (PlatformInfoHob);\r
  }\r
\r
  PlatformAddressWidthFromCpuid (PlatformInfoHob, TRUE);\r
  if (PlatformInfoHob->PhysMemAddressWidth != 0) {\r
    // physical address width is known\r
    PlatformInfoHob->FirstNonAddress = FirstNonAddress;\r
    PlatformDynamicMmioWindow (PlatformInfoHob);\r
    return;\r
  }\r
\r
  //\r
  // physical address width is NOT known\r
  //   -> do some guess work, mostly based on installed memory\r
  //   -> try be conservstibe to stay below the guaranteed minimum of\r
  //      36 phys bits (aka 64 GB).\r
  //\r
  PhysMemAddressWidth = (UINT8)HighBitSet64 (FirstNonAddress);\r
\r
  //\r
  // If FirstNonAddress is not an integral power of two, then we need an\r
  // additional bit.\r
  //\r
  if ((FirstNonAddress & (FirstNonAddress - 1)) != 0) {\r
    ++PhysMemAddressWidth;\r
  }\r
\r
  //\r
  // The minimum address width is 36 (covers up to and excluding 64 GB, which\r
  // is the maximum for Ia32 + PAE). The theoretical architecture maximum for\r
  // X64 long mode is 52 bits, but the DXE IPL clamps that down to 48 bits. We\r
  // can simply assert that here, since 48 bits are good enough for 256 TB.\r
  //\r
  if (PhysMemAddressWidth <= 36) {\r
    PhysMemAddressWidth = 36;\r
  }\r
\r
 #if defined (MDE_CPU_X64)\r
  if (TdIsEnabled ()) {\r
    if (TdSharedPageMask () == (1ULL << 47)) {\r
      PhysMemAddressWidth = 48;\r
    } else {\r
      PhysMemAddressWidth = 52;\r
    }\r
  }\r
\r
  ASSERT (PhysMemAddressWidth <= 52);\r
 #else\r
  ASSERT (PhysMemAddressWidth <= 48);\r
 #endif\r
\r
  PlatformInfoHob->FirstNonAddress     = FirstNonAddress;\r
  PlatformInfoHob->PhysMemAddressWidth = PhysMemAddressWidth;\r
}\r
\r
STATIC\r
VOID\r
QemuInitializeRamBelow1gb (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  if (PlatformInfoHob->SmmSmramRequire && PlatformInfoHob->Q35SmramAtDefaultSmbase) {\r
    PlatformAddMemoryRangeHob (0, SMM_DEFAULT_SMBASE);\r
    PlatformAddReservedMemoryBaseSizeHob (\r
      SMM_DEFAULT_SMBASE,\r
      MCH_DEFAULT_SMBASE_SIZE,\r
      TRUE /* Cacheable */\r
      );\r
    STATIC_ASSERT (\r
      SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE < BASE_512KB + BASE_128KB,\r
      "end of SMRAM at default SMBASE ends at, or exceeds, 640KB"\r
      );\r
    PlatformAddMemoryRangeHob (\r
      SMM_DEFAULT_SMBASE + MCH_DEFAULT_SMBASE_SIZE,\r
      BASE_512KB + BASE_128KB\r
      );\r
  } else {\r
    PlatformAddMemoryRangeHob (0, BASE_512KB + BASE_128KB);\r
  }\r
}\r
\r
/**\r
  Peform Memory Detection for QEMU / KVM\r
\r
**/\r
VOID\r
EFIAPI\r
PlatformQemuInitializeRam (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT64         LowerMemorySize;\r
  UINT64         UpperMemorySize;\r
  MTRR_SETTINGS  MtrrSettings;\r
  EFI_STATUS     Status;\r
\r
  DEBUG ((DEBUG_INFO, "%a called\n", __FUNCTION__));\r
\r
  //\r
  // Determine total memory size available\r
  //\r
  LowerMemorySize = PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
\r
  if (PlatformInfoHob->BootMode == BOOT_ON_S3_RESUME) {\r
    //\r
    // Create the following memory HOB as an exception on the S3 boot path.\r
    //\r
    // Normally we'd create memory HOBs only on the normal boot path. However,\r
    // CpuMpPei specifically needs such a low-memory HOB on the S3 path as\r
    // well, for "borrowing" a subset of it temporarily, for the AP startup\r
    // vector.\r
    //\r
    // CpuMpPei saves the original contents of the borrowed area in permanent\r
    // PEI RAM, in a backup buffer allocated with the normal PEI services.\r
    // CpuMpPei restores the original contents ("returns" the borrowed area) at\r
    // End-of-PEI. End-of-PEI in turn is emitted by S3Resume2Pei before\r
    // transferring control to the OS's wakeup vector in the FACS.\r
    //\r
    // We expect any other PEIMs that "borrow" memory similarly to CpuMpPei to\r
    // restore the original contents. Furthermore, we expect all such PEIMs\r
    // (CpuMpPei included) to claim the borrowed areas by producing memory\r
    // allocation HOBs, and to honor preexistent memory allocation HOBs when\r
    // looking for an area to borrow.\r
    //\r
    QemuInitializeRamBelow1gb (PlatformInfoHob);\r
  } else {\r
    //\r
    // Create memory HOBs\r
    //\r
    QemuInitializeRamBelow1gb (PlatformInfoHob);\r
\r
    if (PlatformInfoHob->SmmSmramRequire) {\r
      UINT32  TsegSize;\r
\r
      TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;\r
      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize - TsegSize);\r
      PlatformAddReservedMemoryBaseSizeHob (\r
        LowerMemorySize - TsegSize,\r
        TsegSize,\r
        TRUE\r
        );\r
    } else {\r
      PlatformAddMemoryRangeHob (BASE_1MB, LowerMemorySize);\r
    }\r
\r
    //\r
    // If QEMU presents an E820 map, then create memory HOBs for the >=4GB RAM\r
    // entries. Otherwise, create a single memory HOB with the flat >=4GB\r
    // memory size read from the CMOS.\r
    //\r
    Status = PlatformScanOrAdd64BitE820Ram (TRUE, NULL, NULL);\r
    if (EFI_ERROR (Status)) {\r
      UpperMemorySize = PlatformGetSystemMemorySizeAbove4gb ();\r
      if (UpperMemorySize != 0) {\r
        PlatformAddMemoryBaseSizeHob (BASE_4GB, UpperMemorySize);\r
      }\r
    }\r
  }\r
\r
  //\r
  // We'd like to keep the following ranges uncached:\r
  // - [640 KB, 1 MB)\r
  // - [LowerMemorySize, 4 GB)\r
  //\r
  // Everything else should be WB. Unfortunately, programming the inverse (ie.\r
  // keeping the default UC, and configuring the complement set of the above as\r
  // WB) is not reliable in general, because the end of the upper RAM can have\r
  // practically any alignment, and we may not have enough variable MTRRs to\r
  // cover it exactly.\r
  //\r
  if (IsMtrrSupported () && (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID)) {\r
    MtrrGetAllMtrrs (&MtrrSettings);\r
\r
    //\r
    // MTRRs disabled, fixed MTRRs disabled, default type is uncached\r
    //\r
    ASSERT ((MtrrSettings.MtrrDefType & BIT11) == 0);\r
    ASSERT ((MtrrSettings.MtrrDefType & BIT10) == 0);\r
    ASSERT ((MtrrSettings.MtrrDefType & 0xFF) == 0);\r
\r
    //\r
    // flip default type to writeback\r
    //\r
    SetMem (&MtrrSettings.Fixed, sizeof MtrrSettings.Fixed, 0x06);\r
    ZeroMem (&MtrrSettings.Variables, sizeof MtrrSettings.Variables);\r
    MtrrSettings.MtrrDefType |= BIT11 | BIT10 | 6;\r
    MtrrSetAllMtrrs (&MtrrSettings);\r
\r
    //\r
    // Set memory range from 640KB to 1MB to uncacheable\r
    //\r
    Status = MtrrSetMemoryAttribute (\r
               BASE_512KB + BASE_128KB,\r
               BASE_1MB - (BASE_512KB + BASE_128KB),\r
               CacheUncacheable\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
\r
    //\r
    // Set the memory range from the start of the 32-bit MMIO area (32-bit PCI\r
    // MMIO aperture on i440fx, PCIEXBAR on q35) to 4GB as uncacheable.\r
    //\r
    Status = MtrrSetMemoryAttribute (\r
               PlatformInfoHob->Uc32Base,\r
               SIZE_4GB - PlatformInfoHob->Uc32Base,\r
               CacheUncacheable\r
               );\r
    ASSERT_EFI_ERROR (Status);\r
  }\r
}\r
\r
VOID\r
EFIAPI\r
PlatformQemuInitializeRamForS3 (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  if (PlatformInfoHob->S3Supported && (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME)) {\r
    //\r
    // This is the memory range that will be used for PEI on S3 resume\r
    //\r
    BuildMemoryAllocationHob (\r
      PlatformInfoHob->S3AcpiReservedMemoryBase,\r
      PlatformInfoHob->S3AcpiReservedMemorySize,\r
      EfiACPIMemoryNVS\r
      );\r
\r
    //\r
    // Cover the initial RAM area used as stack and temporary PEI heap.\r
    //\r
    // This is reserved as ACPI NVS so it can be used on S3 resume.\r
    //\r
    BuildMemoryAllocationHob (\r
      PcdGet32 (PcdOvmfSecPeiTempRamBase),\r
      PcdGet32 (PcdOvmfSecPeiTempRamSize),\r
      EfiACPIMemoryNVS\r
      );\r
\r
    //\r
    // SEC stores its table of GUIDed section handlers here.\r
    //\r
    BuildMemoryAllocationHob (\r
      PcdGet64 (PcdGuidedExtractHandlerTableAddress),\r
      PcdGet32 (PcdGuidedExtractHandlerTableSize),\r
      EfiACPIMemoryNVS\r
      );\r
\r
 #ifdef MDE_CPU_X64\r
    //\r
    // Reserve the initial page tables built by the reset vector code.\r
    //\r
    // Since this memory range will be used by the Reset Vector on S3\r
    // resume, it must be reserved as ACPI NVS.\r
    //\r
    BuildMemoryAllocationHob (\r
      (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecPageTablesBase),\r
      (UINT64)(UINTN)PcdGet32 (PcdOvmfSecPageTablesSize),\r
      EfiACPIMemoryNVS\r
      );\r
\r
    if (PlatformInfoHob->SevEsIsEnabled) {\r
      //\r
      // If SEV-ES is enabled, reserve the GHCB-related memory area. This\r
      // includes the extra page table used to break down the 2MB page\r
      // mapping into 4KB page entries where the GHCB resides and the\r
      // GHCB area itself.\r
      //\r
      // Since this memory range will be used by the Reset Vector on S3\r
      // resume, it must be reserved as ACPI NVS.\r
      //\r
      BuildMemoryAllocationHob (\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableBase),\r
        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbPageTableSize),\r
        EfiACPIMemoryNVS\r
        );\r
      BuildMemoryAllocationHob (\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBase),\r
        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbSize),\r
        EfiACPIMemoryNVS\r
        );\r
      BuildMemoryAllocationHob (\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupBase),\r
        (UINT64)(UINTN)PcdGet32 (PcdOvmfSecGhcbBackupSize),\r
        EfiACPIMemoryNVS\r
        );\r
    }\r
\r
 #endif\r
  }\r
\r
  if (PlatformInfoHob->BootMode != BOOT_ON_S3_RESUME) {\r
    if (!PlatformInfoHob->SmmSmramRequire) {\r
      //\r
      // Reserve the lock box storage area\r
      //\r
      // Since this memory range will be used on S3 resume, it must be\r
      // reserved as ACPI NVS.\r
      //\r
      // If S3 is unsupported, then various drivers might still write to the\r
      // LockBox area. We ought to prevent DXE from serving allocation requests\r
      // such that they would overlap the LockBox storage.\r
      //\r
      ZeroMem (\r
        (VOID *)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
        (UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize)\r
        );\r
      BuildMemoryAllocationHob (\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageBase),\r
        (UINT64)(UINTN)PcdGet32 (PcdOvmfLockBoxStorageSize),\r
        PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
        );\r
    }\r
\r
    if (PlatformInfoHob->SmmSmramRequire) {\r
      UINT32  TsegSize;\r
\r
      //\r
      // Make sure the TSEG area that we reported as a reserved memory resource\r
      // cannot be used for reserved memory allocations.\r
      //\r
      TsegSize = PlatformInfoHob->Q35TsegMbytes * SIZE_1MB;\r
      BuildMemoryAllocationHob (\r
        PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob) - TsegSize,\r
        TsegSize,\r
        EfiReservedMemoryType\r
        );\r
      //\r
      // Similarly, allocate away the (already reserved) SMRAM at the default\r
      // SMBASE, if it exists.\r
      //\r
      if (PlatformInfoHob->Q35SmramAtDefaultSmbase) {\r
        BuildMemoryAllocationHob (\r
          SMM_DEFAULT_SMBASE,\r
          MCH_DEFAULT_SMBASE_SIZE,\r
          EfiReservedMemoryType\r
          );\r
      }\r
    }\r
\r
 #ifdef MDE_CPU_X64\r
    if (FixedPcdGet32 (PcdOvmfWorkAreaSize) != 0) {\r
      //\r
      // Reserve the work area.\r
      //\r
      // Since this memory range will be used by the Reset Vector on S3\r
      // resume, it must be reserved as ACPI NVS.\r
      //\r
      // If S3 is unsupported, then various drivers might still write to the\r
      // work area. We ought to prevent DXE from serving allocation requests\r
      // such that they would overlap the work area.\r
      //\r
      BuildMemoryAllocationHob (\r
        (EFI_PHYSICAL_ADDRESS)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaBase),\r
        (UINT64)(UINTN)FixedPcdGet32 (PcdOvmfWorkAreaSize),\r
        PlatformInfoHob->S3Supported ? EfiACPIMemoryNVS : EfiBootServicesData\r
        );\r
    }\r
\r
 #endif\r
  }\r
}\r