[mirror_edk2.git] / OvmfPkg / Library / PlatformInitLib / Platform.c

/**@file\r
\r
  Copyright (c) 2006 - 2016, Intel Corporation. All rights reserved.<BR>\r
  Copyright (c) 2011, Andrei Warkentin <andreiw@motorola.com>\r
\r
  SPDX-License-Identifier: BSD-2-Clause-Patent\r
\r
**/\r
\r
//\r
// The package level header files this module uses\r
//\r
#include <PiPei.h>\r
\r
//\r
// The Library classes this module consumes\r
//\r
#include <Library/BaseMemoryLib.h>\r
#include <Library/BaseLib.h>\r
#include <Library/DebugLib.h>\r
#include <Library/HobLib.h>\r
#include <Library/IoLib.h>\r
#include <IndustryStandard/I440FxPiix4.h>\r
#include <IndustryStandard/Microvm.h>\r
#include <IndustryStandard/Pci22.h>\r
#include <IndustryStandard/Q35MchIch9.h>\r
#include <IndustryStandard/QemuCpuHotplug.h>\r
#include <Library/MemoryAllocationLib.h>\r
#include <Library/QemuFwCfgLib.h>\r
#include <Library/QemuFwCfgS3Lib.h>\r
#include <Library/QemuFwCfgSimpleParserLib.h>\r
#include <Library/PciLib.h>\r
#include <Guid/SystemNvDataGuid.h>\r
#include <Guid/VariableFormat.h>\r
#include <OvmfPlatforms.h>\r
\r
#include <Library/PlatformInitLib.h>\r
\r
VOID\r
EFIAPI\r
PlatformAddIoMemoryBaseSizeHob (\r
  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
  IN UINT64                MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_MAPPED_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
EFIAPI\r
PlatformAddReservedMemoryBaseSizeHob (\r
  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
  IN UINT64                MemorySize,\r
  IN BOOLEAN               Cacheable\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_MEMORY_RESERVED,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
    (Cacheable ?\r
     EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
     EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
     EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE :\r
     0\r
    ) |\r
    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
EFIAPI\r
PlatformAddIoMemoryRangeHob (\r
  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
  )\r
{\r
  PlatformAddIoMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
EFIAPI\r
PlatformAddMemoryBaseSizeHob (\r
  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
  IN UINT64                MemorySize\r
  )\r
{\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_SYSTEM_MEMORY,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED |\r
    EFI_RESOURCE_ATTRIBUTE_UNCACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_COMBINEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_THROUGH_CACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_WRITE_BACK_CACHEABLE |\r
    EFI_RESOURCE_ATTRIBUTE_TESTED,\r
    MemoryBase,\r
    MemorySize\r
    );\r
}\r
\r
VOID\r
EFIAPI\r
PlatformAddMemoryRangeHob (\r
  IN EFI_PHYSICAL_ADDRESS  MemoryBase,\r
  IN EFI_PHYSICAL_ADDRESS  MemoryLimit\r
  )\r
{\r
  PlatformAddMemoryBaseSizeHob (MemoryBase, (UINT64)(MemoryLimit - MemoryBase));\r
}\r
\r
VOID\r
EFIAPI\r
PlatformMemMapInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT64  PciIoBase;\r
  UINT64  PciIoSize;\r
  UINT64  PciExBarBase;\r
  UINT32  PciBase;\r
  UINT32  PciSize;\r
\r
  PciIoBase = 0xC000;\r
  PciIoSize = 0x4000;\r
\r
  //\r
  // Video memory + Legacy BIOS region\r
  //\r
  if (!TdIsEnabled ()) {\r
    PlatformAddIoMemoryRangeHob (0x0A0000, BASE_1MB);\r
  }\r
\r
  if (PlatformInfoHob->HostBridgeDevId == 0xffff /* microvm */) {\r
    PlatformAddIoMemoryBaseSizeHob (MICROVM_GED_MMIO_BASE, SIZE_4KB);\r
    PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB); /* ioapic #1 */\r
    PlatformAddIoMemoryBaseSizeHob (0xFEC10000, SIZE_4KB); /* ioapic #2 */\r
    return;\r
  }\r
\r
  PlatformGetSystemMemorySizeBelow4gb (PlatformInfoHob);\r
  PciExBarBase = 0;\r
  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // The MMCONFIG area is expected to fall between the top of low RAM and\r
    // the base of the 32-bit PCI host aperture.\r
    //\r
    PciExBarBase = PcdGet64 (PcdPciExpressBaseAddress);\r
    ASSERT (PlatformInfoHob->LowMemory <= PciExBarBase);\r
    ASSERT (PciExBarBase <= MAX_UINT32 - SIZE_256MB);\r
    PciBase = (UINT32)(PciExBarBase + SIZE_256MB);\r
  } else {\r
    ASSERT (PlatformInfoHob->LowMemory <= PlatformInfoHob->Uc32Base);\r
    PciBase = PlatformInfoHob->Uc32Base;\r
  }\r
\r
  //\r
  // address       purpose   size\r
  // ------------  --------  -------------------------\r
  // max(top, 2g)  PCI MMIO  0xFC000000 - max(top, 2g)\r
  // 0xFC000000    gap                           44 MB\r
  // 0xFEC00000    IO-APIC                        4 KB\r
  // 0xFEC01000    gap                         1020 KB\r
  // 0xFED00000    HPET                           1 KB\r
  // 0xFED00400    gap                          111 KB\r
  // 0xFED1C000    gap (PIIX4) / RCRB (ICH9)     16 KB\r
  // 0xFED20000    gap                          896 KB\r
  // 0xFEE00000    LAPIC                          1 MB\r
  //\r
  PciSize = 0xFC000000 - PciBase;\r
  PlatformAddIoMemoryBaseSizeHob (PciBase, PciSize);\r
\r
  PlatformInfoHob->PcdPciMmio32Base = PciBase;\r
  PlatformInfoHob->PcdPciMmio32Size = PciSize;\r
\r
  PlatformAddIoMemoryBaseSizeHob (0xFEC00000, SIZE_4KB);\r
  PlatformAddIoMemoryBaseSizeHob (0xFED00000, SIZE_1KB);\r
  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    PlatformAddIoMemoryBaseSizeHob (ICH9_ROOT_COMPLEX_BASE, SIZE_16KB);\r
    //\r
    // Note: there should be an\r
    //\r
    //   PlatformAddIoMemoryBaseSizeHob (PciExBarBase, SIZE_256MB);\r
    //\r
    // call below, just like the one above for RCBA. However, Linux insists\r
    // that the MMCONFIG area be marked in the E820 or UEFI memory map as\r
    // "reserved memory" -- Linux does not content itself with a simple gap\r
    // in the memory map wherever the MCFG ACPI table points to.\r
    //\r
    // This appears to be a safety measure. The PCI Firmware Specification\r
    // (rev 3.1) says in 4.1.2. "MCFG Table Description": "The resources can\r
    // *optionally* be returned in [...] EFIGetMemoryMap as reserved memory\r
    // [...]". (Emphasis added here.)\r
    //\r
    // Normally we add memory resource descriptor HOBs in\r
    // QemuInitializeRam(), and pre-allocate from those with memory\r
    // allocation HOBs in InitializeRamRegions(). However, the MMCONFIG area\r
    // is most definitely not RAM; so, as an exception, cover it with\r
    // uncacheable reserved memory right here.\r
    //\r
    PlatformAddReservedMemoryBaseSizeHob (PciExBarBase, SIZE_256MB, FALSE);\r
    BuildMemoryAllocationHob (\r
      PciExBarBase,\r
      SIZE_256MB,\r
      EfiReservedMemoryType\r
      );\r
  }\r
\r
  PlatformAddIoMemoryBaseSizeHob (PcdGet32 (PcdCpuLocalApicBaseAddress), SIZE_1MB);\r
\r
  //\r
  // On Q35, the IO Port space is available for PCI resource allocations from\r
  // 0x6000 up.\r
  //\r
  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    PciIoBase = 0x6000;\r
    PciIoSize = 0xA000;\r
    ASSERT ((ICH9_PMBASE_VALUE & 0xF000) < PciIoBase);\r
  }\r
\r
  //\r
  // Add PCI IO Port space available for PCI resource allocations.\r
  //\r
  BuildResourceDescriptorHob (\r
    EFI_RESOURCE_IO,\r
    EFI_RESOURCE_ATTRIBUTE_PRESENT     |\r
    EFI_RESOURCE_ATTRIBUTE_INITIALIZED,\r
    PciIoBase,\r
    PciIoSize\r
    );\r
\r
  PlatformInfoHob->PcdPciIoBase = PciIoBase;\r
  PlatformInfoHob->PcdPciIoSize = PciIoSize;\r
}\r
\r
/**\r
 * Fetch "opt/ovmf/PcdSetNxForStack" from QEMU\r
 *\r
 * @param Setting     The pointer to the setting of "/opt/ovmf/PcdSetNxForStack".\r
 * @return EFI_SUCCESS  Successfully fetch the settings.\r
 */\r
EFI_STATUS\r
EFIAPI\r
PlatformNoexecDxeInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  return QemuFwCfgParseBool ("opt/ovmf/PcdSetNxForStack", &PlatformInfoHob->PcdSetNxForStack);\r
}\r
\r
VOID\r
PciExBarInitialization (\r
  VOID\r
  )\r
{\r
  union {\r
    UINT64    Uint64;\r
    UINT32    Uint32[2];\r
  } PciExBarBase;\r
\r
  //\r
  // We only support the 256MB size for the MMCONFIG area:\r
  // 256 buses * 32 devices * 8 functions * 4096 bytes config space.\r
  //\r
  // The masks used below enforce the Q35 requirements that the MMCONFIG area\r
  // be (a) correctly aligned -- here at 256 MB --, (b) located under 64 GB.\r
  //\r
  // Note that (b) also ensures that the minimum address width we have\r
  // determined in AddressWidthInitialization(), i.e., 36 bits, will suffice\r
  // for DXE's page tables to cover the MMCONFIG area.\r
  //\r
  PciExBarBase.Uint64 = PcdGet64 (PcdPciExpressBaseAddress);\r
  ASSERT ((PciExBarBase.Uint32[1] & MCH_PCIEXBAR_HIGHMASK) == 0);\r
  ASSERT ((PciExBarBase.Uint32[0] & MCH_PCIEXBAR_LOWMASK) == 0);\r
\r
  //\r
  // Clear the PCIEXBAREN bit first, before programming the high register.\r
  //\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW), 0);\r
\r
  //\r
  // Program the high register. Then program the low register, setting the\r
  // MMCONFIG area size and enabling decoding at once.\r
  //\r
  PciWrite32 (DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_HIGH), PciExBarBase.Uint32[1]);\r
  PciWrite32 (\r
    DRAMC_REGISTER_Q35 (MCH_PCIEXBAR_LOW),\r
    PciExBarBase.Uint32[0] | MCH_PCIEXBAR_BUS_FF | MCH_PCIEXBAR_EN\r
    );\r
}\r
\r
VOID\r
EFIAPI\r
PlatformMiscInitialization (\r
  IN EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINTN   PmCmd;\r
  UINTN   Pmba;\r
  UINT32  PmbaAndVal;\r
  UINT32  PmbaOrVal;\r
  UINTN   AcpiCtlReg;\r
  UINT8   AcpiEnBit;\r
\r
  //\r
  // Disable A20 Mask\r
  //\r
  if (PlatformInfoHob->HostBridgeDevId != CLOUDHV_DEVICE_ID) {\r
    IoOr8 (0x92, BIT1);\r
  }\r
\r
  //\r
  // Build the CPU HOB with guest RAM size dependent address width and 16-bits\r
  // of IO space. (Side note: unlike other HOBs, the CPU HOB is needed during\r
  // S3 resume as well, so we build it unconditionally.)\r
  //\r
  BuildCpuHob (PlatformInfoHob->PhysMemAddressWidth, 16);\r
\r
  //\r
  // Determine platform type and save Host Bridge DID to PCD\r
  //\r
  switch (PlatformInfoHob->HostBridgeDevId) {\r
    case INTEL_82441_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_PIIX4 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMBA);\r
      PmbaAndVal = ~(UINT32)PIIX4_PMBA_MASK;\r
      PmbaOrVal  = PIIX4_PMBA_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_PIIX4 (PIIX4_PMREGMISC);\r
      AcpiEnBit  = PIIX4_PMREGMISC_PMIOSE;\r
      break;\r
    case INTEL_Q35_MCH_DEVICE_ID:\r
      PmCmd      = POWER_MGMT_REGISTER_Q35 (PCI_COMMAND_OFFSET);\r
      Pmba       = POWER_MGMT_REGISTER_Q35 (ICH9_PMBASE);\r
      PmbaAndVal = ~(UINT32)ICH9_PMBASE_MASK;\r
      PmbaOrVal  = ICH9_PMBASE_VALUE;\r
      AcpiCtlReg = POWER_MGMT_REGISTER_Q35 (ICH9_ACPI_CNTL);\r
      AcpiEnBit  = ICH9_ACPI_CNTL_ACPI_EN;\r
      break;\r
    case CLOUDHV_DEVICE_ID:\r
      break;\r
    default:\r
      DEBUG ((\r
        DEBUG_ERROR,\r
        "%a: Unknown Host Bridge Device ID: 0x%04x\n",\r
        __FUNCTION__,\r
        PlatformInfoHob->HostBridgeDevId\r
        ));\r
      ASSERT (FALSE);\r
      return;\r
  }\r
\r
  if (PlatformInfoHob->HostBridgeDevId == CLOUDHV_DEVICE_ID) {\r
    DEBUG ((DEBUG_INFO, "%a: Cloud Hypervisor is done.\n", __FUNCTION__));\r
    return;\r
  }\r
\r
  //\r
  // If the appropriate IOspace enable bit is set, assume the ACPI PMBA has\r
  // been configured and skip the setup here. This matches the logic in\r
  // AcpiTimerLibConstructor ().\r
  //\r
  if ((PciRead8 (AcpiCtlReg) & AcpiEnBit) == 0) {\r
    //\r
    // The PEI phase should be exited with fully accessibe ACPI PM IO space:\r
    // 1. set PMBA\r
    //\r
    PciAndThenOr32 (Pmba, PmbaAndVal, PmbaOrVal);\r
\r
    //\r
    // 2. set PCICMD/IOSE\r
    //\r
    PciOr8 (PmCmd, EFI_PCI_COMMAND_IO_SPACE);\r
\r
    //\r
    // 3. set ACPI PM IO enable bit (PMREGMISC:PMIOSE or ACPI_CNTL:ACPI_EN)\r
    //\r
    PciOr8 (AcpiCtlReg, AcpiEnBit);\r
  }\r
\r
  if (PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) {\r
    //\r
    // Set Root Complex Register Block BAR\r
    //\r
    PciWrite32 (\r
      POWER_MGMT_REGISTER_Q35 (ICH9_RCBA),\r
      ICH9_ROOT_COMPLEX_BASE | ICH9_RCBA_EN\r
      );\r
\r
    //\r
    // Set PCI Express Register Range Base Address\r
    //\r
    PciExBarInitialization ();\r
  }\r
}\r
\r
/**\r
  Check for various QEMU bugs concerning CPU numbers.\r
\r
  Compensate for those bugs if various conditions are satisfied, by updating a\r
  suitable subset of the input-output parameters. The function may not return\r
  (it may hang deliberately), even in RELEASE builds, if the QEMU bug is\r
  impossible to cover up.\r
\r
  @param[in,out] BootCpuCount  On input, the boot CPU count reported by QEMU via\r
                               fw_cfg (QemuFwCfgItemSmpCpuCount). The caller is\r
                               responsible for ensuring (BootCpuCount > 0); that\r
                               is, if QEMU does not provide the boot CPU count\r
                               via fw_cfg *at all*, then this function must not\r
                               be called.\r
\r
  @param[in,out] Present       On input, the number of present-at-boot CPUs, as\r
                               reported by QEMU through the modern CPU hotplug\r
                               register block.\r
\r
  @param[in,out] Possible      On input, the number of possible CPUs, as\r
                               reported by QEMU through the modern CPU hotplug\r
                               register block.\r
**/\r
STATIC\r
VOID\r
PlatformCpuCountBugCheck (\r
  IN OUT UINT16  *BootCpuCount,\r
  IN OUT UINT32  *Present,\r
  IN OUT UINT32  *Possible\r
  )\r
{\r
  ASSERT (*BootCpuCount > 0);\r
\r
  //\r
  // Sanity check: fw_cfg and the modern CPU hotplug interface should expose the\r
  // same boot CPU count.\r
  //\r
  if (*BootCpuCount != *Present) {\r
    DEBUG ((\r
      DEBUG_WARN,\r
      "%a: QEMU v2.7 reset bug: BootCpuCount=%d Present=%u\n",\r
      __FUNCTION__,\r
      *BootCpuCount,\r
      *Present\r
      ));\r
    //\r
    // The handling of QemuFwCfgItemSmpCpuCount, across CPU hotplug plus\r
    // platform reset (including S3), was corrected in QEMU commit e3cadac073a9\r
    // ("pc: fix FW_CFG_NB_CPUS to account for -device added CPUs", 2016-11-16),\r
    // part of release v2.8.0.\r
    //\r
    *BootCpuCount = (UINT16)*Present;\r
  }\r
}\r
\r
/**\r
  Fetch the boot CPU count and the possible CPU count from QEMU, and expose\r
  them to UefiCpuPkg modules.\r
**/\r
VOID\r
EFIAPI\r
PlatformMaxCpuCountInitialization (\r
  IN OUT EFI_HOB_PLATFORM_INFO  *PlatformInfoHob\r
  )\r
{\r
  UINT16  BootCpuCount = 0;\r
  UINT32  MaxCpuCount;\r
\r
  //\r
  // Try to fetch the boot CPU count.\r
  //\r
  if (QemuFwCfgIsAvailable ()) {\r
    QemuFwCfgSelectItem (QemuFwCfgItemSmpCpuCount);\r
    BootCpuCount = QemuFwCfgRead16 ();\r
  }\r
\r
  if (BootCpuCount == 0) {\r
    //\r
    // QEMU doesn't report the boot CPU count. (BootCpuCount == 0) will let\r
    // MpInitLib count APs up to (PcdCpuMaxLogicalProcessorNumber - 1), or\r
    // until PcdCpuApInitTimeOutInMicroSeconds elapses (whichever is reached\r
    // first).\r
    //\r
    DEBUG ((DEBUG_WARN, "%a: boot CPU count unavailable\n", __FUNCTION__));\r
    MaxCpuCount = PlatformInfoHob->DefaultMaxCpuNumber;\r
  } else {\r
    //\r
    // We will expose BootCpuCount to MpInitLib. MpInitLib will count APs up to\r
    // (BootCpuCount - 1) precisely, regardless of timeout.\r
    //\r
    // Now try to fetch the possible CPU count.\r
    //\r
    UINTN   CpuHpBase;\r
    UINT32  CmdData2;\r
\r
    CpuHpBase = ((PlatformInfoHob->HostBridgeDevId == INTEL_Q35_MCH_DEVICE_ID) ?\r
                 ICH9_CPU_HOTPLUG_BASE : PIIX4_CPU_HOTPLUG_BASE);\r
\r
    //\r
    // If only legacy mode is available in the CPU hotplug register block, or\r
    // the register block is completely missing, then the writes below are\r
    // no-ops.\r
    //\r
    // 1. Switch the hotplug register block to modern mode.\r
    //\r
    IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
    //\r
    // 2. Select a valid CPU for deterministic reading of\r
    //    QEMU_CPUHP_R_CMD_DATA2.\r
    //\r
    //    CPU#0 is always valid; it is the always present and non-removable\r
    //    BSP.\r
    //\r
    IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, 0);\r
    //\r
    // 3. Send a command after which QEMU_CPUHP_R_CMD_DATA2 is specified to\r
    //    read as zero, and which does not invalidate the selector. (The\r
    //    selector may change, but it must not become invalid.)\r
    //\r
    //    Send QEMU_CPUHP_CMD_GET_PENDING, as it will prove useful later.\r
    //\r
    IoWrite8 (CpuHpBase + QEMU_CPUHP_W_CMD, QEMU_CPUHP_CMD_GET_PENDING);\r
    //\r
    // 4. Read QEMU_CPUHP_R_CMD_DATA2.\r
    //\r
    //    If the register block is entirely missing, then this is an unassigned\r
    //    IO read, returning all-bits-one.\r
    //\r
    //    If only legacy mode is available, then bit#0 stands for CPU#0 in the\r
    //    "CPU present bitmap". CPU#0 is always present.\r
    //\r
    //    Otherwise, QEMU_CPUHP_R_CMD_DATA2 is either still reserved (returning\r
    //    all-bits-zero), or it is specified to read as zero after the above\r
    //    steps. Both cases confirm modern mode.\r
    //\r
    CmdData2 = IoRead32 (CpuHpBase + QEMU_CPUHP_R_CMD_DATA2);\r
    DEBUG ((DEBUG_VERBOSE, "%a: CmdData2=0x%x\n", __FUNCTION__, CmdData2));\r
    if (CmdData2 != 0) {\r
      //\r
      // QEMU doesn't support the modern CPU hotplug interface. Assume that the\r
      // possible CPU count equals the boot CPU count (precluding hotplug).\r
      //\r
      DEBUG ((\r
        DEBUG_WARN,\r
        "%a: modern CPU hotplug interface unavailable\n",\r
        __FUNCTION__\r
        ));\r
      MaxCpuCount = BootCpuCount;\r
    } else {\r
      //\r
      // Grab the possible CPU count from the modern CPU hotplug interface.\r
      //\r
      UINT32  Present, Possible, Selected;\r
\r
      Present  = 0;\r
      Possible = 0;\r
\r
      //\r
      // We've sent QEMU_CPUHP_CMD_GET_PENDING last; this ensures\r
      // QEMU_CPUHP_RW_CMD_DATA can now be read usefully. However,\r
      // QEMU_CPUHP_CMD_GET_PENDING may have selected a CPU with actual pending\r
      // hotplug events; therefore, select CPU#0 forcibly.\r
      //\r
      IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
\r
      do {\r
        UINT8  CpuStatus;\r
\r
        //\r
        // Read the status of the currently selected CPU. This will help with\r
        // various CPU count sanity checks.\r
        //\r
        CpuStatus = IoRead8 (CpuHpBase + QEMU_CPUHP_R_CPU_STAT);\r
        if ((CpuStatus & QEMU_CPUHP_STAT_ENABLED) != 0) {\r
          ++Present;\r
        }\r
\r
        //\r
        // Attempt to select the next CPU.\r
        //\r
        ++Possible;\r
        IoWrite32 (CpuHpBase + QEMU_CPUHP_W_CPU_SEL, Possible);\r
        //\r
        // If the selection is successful, then the following read will return\r
        // the selector (which we know is positive at this point). Otherwise,\r
        // the read will return 0.\r
        //\r
        Selected = IoRead32 (CpuHpBase + QEMU_CPUHP_RW_CMD_DATA);\r
        ASSERT (Selected == Possible || Selected == 0);\r
      } while (Selected > 0);\r
\r
      PlatformCpuCountBugCheck (&BootCpuCount, &Present, &Possible);\r
\r
      MaxCpuCount = Possible;\r
    }\r
  }\r
\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "%a: BootCpuCount=%d MaxCpuCount=%u\n",\r
    __FUNCTION__,\r
    BootCpuCount,\r
    MaxCpuCount\r
    ));\r
  ASSERT (BootCpuCount <= MaxCpuCount);\r
\r
  PlatformInfoHob->PcdCpuMaxLogicalProcessorNumber  = MaxCpuCount;\r
  PlatformInfoHob->PcdCpuBootLogicalProcessorNumber = BootCpuCount;\r
}\r
\r
/**\r
  Check padding data all bit should be 1.\r
\r
  @param[in] Buffer     - A pointer to buffer header\r
  @param[in] BufferSize - Buffer size\r
\r
  @retval  TRUE   - The padding data is valid.\r
  @retval  TRUE  - The padding data is invalid.\r
\r
**/\r
BOOLEAN\r
CheckPaddingData (\r
  IN UINT8   *Buffer,\r
  IN UINT32  BufferSize\r
  )\r
{\r
  UINT32  index;\r
\r
  for (index = 0; index < BufferSize; index++) {\r
    if (Buffer[index] != 0xFF) {\r
      return FALSE;\r
    }\r
  }\r
\r
  return TRUE;\r
}\r
\r
/**\r
  Check the integrity of NvVarStore.\r
\r
  @param[in] NvVarStoreBase - A pointer to NvVarStore header\r
  @param[in] NvVarStoreSize - NvVarStore size\r
\r
  @retval  TRUE   - The NvVarStore is valid.\r
  @retval  FALSE  - The NvVarStore is invalid.\r
\r
**/\r
BOOLEAN\r
EFIAPI\r
PlatformValidateNvVarStore (\r
  IN UINT8   *NvVarStoreBase,\r
  IN UINT32  NvVarStoreSize\r
  )\r
{\r
  UINT16                         Checksum;\r
  UINTN                          VariableBase;\r
  UINT32                         VariableOffset;\r
  UINT32                         VariableOffsetBeforeAlign;\r
  EFI_FIRMWARE_VOLUME_HEADER     *NvVarStoreFvHeader;\r
  VARIABLE_STORE_HEADER          *NvVarStoreHeader;\r
  AUTHENTICATED_VARIABLE_HEADER  *VariableHeader;\r
\r
  static EFI_GUID  FvHdrGUID       = EFI_SYSTEM_NV_DATA_FV_GUID;\r
  static EFI_GUID  VarStoreHdrGUID = EFI_AUTHENTICATED_VARIABLE_GUID;\r
\r
  VariableOffset = 0;\r
\r
  if (NvVarStoreBase == NULL) {\r
    DEBUG ((DEBUG_ERROR, "NvVarStore pointer is NULL.\n"));\r
    return FALSE;\r
  }\r
\r
  //\r
  // Verify the header zerovetor, filesystemguid,\r
  // revision, signature, attributes, fvlength, checksum\r
  // HeaderLength cannot be an odd number\r
  //\r
  NvVarStoreFvHeader = (EFI_FIRMWARE_VOLUME_HEADER *)NvVarStoreBase;\r
\r
  if ((!IsZeroBuffer (NvVarStoreFvHeader->ZeroVector, 16)) ||\r
      (!CompareGuid (&FvHdrGUID, &NvVarStoreFvHeader->FileSystemGuid)) ||\r
      (NvVarStoreFvHeader->Signature != EFI_FVH_SIGNATURE) ||\r
      (NvVarStoreFvHeader->Attributes != 0x4feff) ||\r
      ((NvVarStoreFvHeader->HeaderLength & 0x01) != 0) ||\r
      (NvVarStoreFvHeader->Revision != EFI_FVH_REVISION) ||\r
      (NvVarStoreFvHeader->FvLength != NvVarStoreSize)\r
      )\r
  {\r
    DEBUG ((DEBUG_ERROR, "NvVarStore FV headers were invalid.\n"));\r
    return FALSE;\r
  }\r
\r
  //\r
  // Verify the header checksum\r
  //\r
  Checksum = CalculateSum16 ((VOID *)NvVarStoreFvHeader, NvVarStoreFvHeader->HeaderLength);\r
\r
  if (Checksum != 0) {\r
    DEBUG ((DEBUG_ERROR, "NvVarStore FV checksum was invalid.\n"));\r
    return FALSE;\r
  }\r
\r
  //\r
  // Verify the header signature, size, format, state\r
  //\r
  NvVarStoreHeader = (VARIABLE_STORE_HEADER *)(NvVarStoreBase + NvVarStoreFvHeader->HeaderLength);\r
  if ((!CompareGuid (&VarStoreHdrGUID, &NvVarStoreHeader->Signature)) ||\r
      (NvVarStoreHeader->Format != VARIABLE_STORE_FORMATTED) ||\r
      (NvVarStoreHeader->State != VARIABLE_STORE_HEALTHY) ||\r
      (NvVarStoreHeader->Size > (NvVarStoreFvHeader->FvLength - NvVarStoreFvHeader->HeaderLength)) ||\r
      (NvVarStoreHeader->Size < sizeof (VARIABLE_STORE_HEADER))\r
      )\r
  {\r
    DEBUG ((DEBUG_ERROR, "NvVarStore header signature/size/format/state were invalid.\n"));\r
    return FALSE;\r
  }\r
\r
  //\r
  // Verify the header startId, state\r
  // Verify data to the end\r
  //\r
  VariableBase = (UINTN)NvVarStoreBase + NvVarStoreFvHeader->HeaderLength + sizeof (VARIABLE_STORE_HEADER);\r
  while (VariableOffset  < (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {\r
    VariableHeader = (AUTHENTICATED_VARIABLE_HEADER *)(VariableBase + VariableOffset);\r
    if (VariableHeader->StartId != VARIABLE_DATA) {\r
      if (!CheckPaddingData ((UINT8 *)VariableHeader, NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER) - VariableOffset)) {\r
        DEBUG ((DEBUG_ERROR, "NvVarStore variable header StartId was invalid.\n"));\r
        return FALSE;\r
      }\r
\r
      VariableOffset = NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER);\r
    } else {\r
      if (!((VariableHeader->State == VAR_HEADER_VALID_ONLY) ||\r
            (VariableHeader->State == VAR_ADDED) ||\r
            (VariableHeader->State == (VAR_ADDED & VAR_DELETED)) ||\r
            (VariableHeader->State == (VAR_ADDED & VAR_IN_DELETED_TRANSITION)) ||\r
            (VariableHeader->State == (VAR_ADDED & VAR_IN_DELETED_TRANSITION & VAR_DELETED))))\r
      {\r
        DEBUG ((DEBUG_ERROR, "NvVarStore Variable header State was invalid.\n"));\r
        return FALSE;\r
      }\r
\r
      VariableOffset += sizeof (AUTHENTICATED_VARIABLE_HEADER) + VariableHeader->NameSize + VariableHeader->DataSize;\r
      // Verify VariableOffset should be less than or equal NvVarStoreHeader->Size - sizeof(VARIABLE_STORE_HEADER)\r
      if (VariableOffset > (NvVarStoreHeader->Size - sizeof (VARIABLE_STORE_HEADER))) {\r
        DEBUG ((DEBUG_ERROR, "NvVarStore Variable header VariableOffset was invalid.\n"));\r
        return FALSE;\r
      }\r
\r
      VariableOffsetBeforeAlign = VariableOffset;\r
      // 4 byte align\r
      VariableOffset = (VariableOffset  + 3) & (UINTN)(~3);\r
\r
      if (!CheckPaddingData ((UINT8 *)(VariableBase + VariableOffsetBeforeAlign), VariableOffset - VariableOffsetBeforeAlign)) {\r
        DEBUG ((DEBUG_ERROR, "NvVarStore Variable header PaddingData was invalid.\n"));\r
        return FALSE;\r
      }\r
    }\r
  }\r
\r
  return TRUE;\r
}\r
\r
/**\r
 Allocate storage for NV variables early on so it will be\r
 at a consistent address.  Since VM memory is preserved\r
 across reboots, this allows the NV variable storage to survive\r
 a VM reboot.\r
\r
 *\r
 * @retval VOID* The pointer to the storage for NV Variables\r
 */\r
VOID *\r
EFIAPI\r
PlatformReserveEmuVariableNvStore (\r
  VOID\r
  )\r
{\r
  VOID    *VariableStore;\r
  UINT32  VarStoreSize;\r
\r
  VarStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);\r
  //\r
  // Allocate storage for NV variables early on so it will be\r
  // at a consistent address.  Since VM memory is preserved\r
  // across reboots, this allows the NV variable storage to survive\r
  // a VM reboot.\r
  //\r
  VariableStore =\r
    AllocateRuntimePages (\r
      EFI_SIZE_TO_PAGES (VarStoreSize)\r
      );\r
  DEBUG ((\r
    DEBUG_INFO,\r
    "Reserved variable store memory: 0x%p; size: %dkb\n",\r
    VariableStore,\r
    VarStoreSize / 1024\r
    ));\r
\r
  return VariableStore;\r
}\r
\r
/**\r
 When OVMF is lauched with -bios parameter, UEFI variables will be\r
 partially emulated, and non-volatile variables may lose their contents\r
 after a reboot. This makes the secure boot feature not working.\r
\r
 This function is used to initialize the EmuVariableNvStore\r
 with the conent in PcdOvmfFlashNvStorageVariableBase.\r
\r
 @param[in] EmuVariableNvStore      - A pointer to EmuVariableNvStore\r
\r
 @retval  EFI_SUCCESS   - Successfully init the EmuVariableNvStore\r
 @retval  Others        - As the error code indicates\r
 */\r
EFI_STATUS\r
EFIAPI\r
PlatformInitEmuVariableNvStore (\r
  IN VOID  *EmuVariableNvStore\r
  )\r
{\r
  UINT8   *Base;\r
  UINT32  Size;\r
  UINT32  EmuVariableNvStoreSize;\r
\r
  EmuVariableNvStoreSize = 2 * PcdGet32 (PcdFlashNvStorageFtwSpareSize);\r
  if ((EmuVariableNvStore == NULL) || (EmuVariableNvStoreSize == 0)) {\r
    DEBUG ((DEBUG_ERROR, "Invalid EmuVariableNvStore parameter.\n"));\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  Base = (UINT8 *)(UINTN)PcdGet32 (PcdOvmfFlashNvStorageVariableBase);\r
  Size = (UINT32)PcdGet32 (PcdFlashNvStorageVariableSize);\r
  ASSERT (Size < EmuVariableNvStoreSize);\r
\r
  if (!PlatformValidateNvVarStore (Base, PcdGet32 (PcdCfvRawDataSize))) {\r
    ASSERT (FALSE);\r
    return EFI_INVALID_PARAMETER;\r
  }\r
\r
  DEBUG ((DEBUG_INFO, "Init EmuVariableNvStore with the content in FlashNvStorage\n"));\r
\r
  CopyMem (EmuVariableNvStore, Base, Size);\r
\r
  return EFI_SUCCESS;\r
}\r