[mirror_edk2.git] / OvmfPkg / OvmfPkg.dec

## @file\r
#  EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
#\r
#  Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
#\r
#  SPDX-License-Identifier: BSD-2-Clause-Patent\r
#\r
##\r
\r
[Defines]\r
  DEC_SPECIFICATION              = 0x00010005\r
  PACKAGE_NAME                   = OvmfPkg\r
  PACKAGE_GUID                   = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
  PACKAGE_VERSION                = 0.1\r
\r
[Includes]\r
  Include\r
\r
[LibraryClasses]\r
  ##  @libraryclass  Loads and boots a Linux kernel image\r
  #\r
  LoadLinuxLib|Include/Library/LoadLinuxLib.h\r
\r
  ##  @libraryclass  Save and restore variables using a file\r
  #\r
  NvVarsFileLib|Include/Library/NvVarsFileLib.h\r
\r
  ##  @libraryclass  Provides services to work with PCI capabilities in PCI\r
  #                  config space.\r
  PciCapLib|Include/Library/PciCapLib.h\r
\r
  ##  @libraryclass  Layered on top of PciCapLib, allows clients to plug an\r
  #                  EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r
  #                  space access.\r
  PciCapPciIoLib|Include/Library/PciCapPciIoLib.h\r
\r
  ##  @libraryclass  Layered on top of PciCapLib, allows clients to plug a\r
  #                  PciSegmentLib backend into PciCapLib, for config space\r
  #                  access.\r
  PciCapPciSegmentLib|Include/Library/PciCapPciSegmentLib.h\r
\r
  ##  @libraryclass  Register a status code handler for printing the Boot\r
  #                  Manager's LoadImage() and StartImage() preparations, and\r
  #                  return codes, to the UEFI console.\r
  PlatformBmPrintScLib|Include/Library/PlatformBmPrintScLib.h\r
\r
  ##  @libraryclass  Access QEMU's firmware configuration interface\r
  #\r
  QemuFwCfgLib|Include/Library/QemuFwCfgLib.h\r
\r
  ##  @libraryclass  S3 support for QEMU fw_cfg\r
  #\r
  QemuFwCfgS3Lib|Include/Library/QemuFwCfgS3Lib.h\r
\r
  ##  @libraryclass  Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
  #                  fw_cfg file.\r
  #\r
  QemuBootOrderLib|Include/Library/QemuBootOrderLib.h\r
\r
  ##  @libraryclass  Serialize (and deserialize) variables\r
  #\r
  SerializeVariablesLib|Include/Library/SerializeVariablesLib.h\r
\r
  ##  @libraryclass  Invoke Xen hypercalls\r
  #\r
  XenHypercallLib|Include/Library/XenHypercallLib.h\r
\r
  ##  @libraryclass  Manage XenBus device path and I/O handles\r
  #\r
  XenIoMmioLib|Include/Library/XenIoMmioLib.h\r
\r
[Guids]\r
  gUefiOvmfPkgTokenSpaceGuid          = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
  gEfiXenInfoGuid                     = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
  gOvmfPlatformConfigGuid             = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
  gVirtioMmioTransportGuid            = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
  gQemuRamfbGuid                      = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r
  gXenBusRootDeviceGuid               = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
  gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
  gMicrosoftVendorGuid                = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}\r
\r
[Protocols]\r
  gVirtioDeviceProtocolGuid           = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
  gXenBusProtocolGuid                 = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
  gXenIoProtocolGuid                  = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
  gIoMmuAbsentProtocolGuid            = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r
  gEfiLegacy8259ProtocolGuid          = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r
\r
[PcdsFixedAtBuild]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase|0x0|UINT32|0\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize|0x0|UINT32|1\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase|0x0|UINT32|0x15\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize|0x0|UINT32|0x16\r
\r
  ## This flag is used to control the destination port for PlatformDebugLibIoPort\r
  gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort|0x402|UINT16|4\r
\r
  ## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
  #  LUNs are retrieved from the host during virtio-scsi setup.\r
  #  MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
  #  possible devices. This can take extremely long, for example with\r
  #  MaxTarget=255 and MaxLun=16383. The *inclusive* constants below limit\r
  #  MaxTarget and MaxLun, independently, should the host report higher values,\r
  #  so that scanning the number of devices given by their product is still\r
  #  acceptably fast.\r
  gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit|31|UINT16|6\r
  gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit|7|UINT32|7\r
\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase|0x0|UINT32|0x8\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize|0x0|UINT32|0x9\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize|0x0|UINT32|0xa\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize|0|UINT32|0xb\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase|0x0|UINT32|0xc\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase|0x0|UINT32|0xd\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase|0x0|UINT32|0xe\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress|0x0|UINT32|0xf\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase|0x0|UINT32|0x11\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize|0x0|UINT32|0x12\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase|0x0|UINT32|0x13\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize|0x0|UINT32|0x14\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase|0x0|UINT32|0x18\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize|0x0|UINT32|0x19\r
  gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize|0x0|UINT32|0x1a\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd|0x0|UINT32|0x1f\r
\r
  ## Pcd8259LegacyModeMask defines the default mask value for platform. This\r
  #  value is determined.\r
  #  1) If platform only support pure UEFI, value should be set to 0xFFFF or\r
  #     0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r
  #     UEFI platform.\r
  #  2) If platform install CSM and use thunk module:\r
  #     a) If thunk call provided by CSM binary requires some legacy interrupt\r
  #        support, the corresponding bit should be opened as 0.\r
  #        For example, if keyboard interfaces provided CSM binary use legacy\r
  #        keyboard interrupt in 8259 bit 1, then the value should be set to\r
  #        0xFFFC.\r
  #     b) If all thunk call provied by CSM binary do not require legacy\r
  #        interrupt support, value should be set to 0xFFFF or 0xFFFE.\r
  #\r
  #  The default value of legacy mode mask could be changed by\r
  #  EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r
  #  except some special cases such as when initializing the CSM binary, it\r
  #  should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r
  #  original legacy mask value if changing is made for these special case.\r
  gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask|0xFFFF|UINT16|0x3\r
\r
  ## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r
  #  mode's interrrupt controller.\r
  #  For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
  gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel|0x0000|UINT16|0x5\r
\r
[PcdsDynamic, PcdsDynamicEx]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent|0|UINT64|2\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable|FALSE|BOOLEAN|0x10\r
  gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId|0|UINT16|0x1b\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated|FALSE|BOOLEAN|0x21\r
\r
  ## The IO port aperture shared by all PCI root bridges.\r
  #\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase|0x0|UINT64|0x22\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize|0x0|UINT64|0x23\r
\r
  ## The 32-bit MMIO aperture shared by all PCI root bridges.\r
  #\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base|0x0|UINT64|0x24\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size|0x0|UINT64|0x25\r
\r
  ## The 64-bit MMIO aperture shared by all PCI root bridges.\r
  #\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base|0x0|UINT64|0x26\r
  gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size|0x0|UINT64|0x27\r
\r
  ## The following setting controls how many megabytes we configure as TSEG on\r
  #  Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r
  #  cause undefined behavior. During boot, the PCD is updated by PlatformPei\r
  #  to reflect the extended TSEG size, if one is advertized by QEMU.\r
  #\r
  #  This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes|8|UINT16|0x20\r
\r
[PcdsFeatureFlag]\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation|TRUE|BOOLEAN|0x1c\r
  gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation|FALSE|BOOLEAN|0x1d\r
\r
  ## This feature flag enables SMM/SMRAM support. Note that it also requires\r
  #  such support from the underlying QEMU instance; if that support is not\r
  #  present, the firmware will reject continuing after a certain point.\r
  #\r
  #  The flag also acts as a general "security switch"; when TRUE, many\r
  #  components will change behavior, with the goal of preventing a malicious\r
  #  runtime OS from tampering with firmware structures (special memory ranges\r
  #  used by OVMF, the varstore pflash chip, LockBox etc).\r
  gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire|FALSE|BOOLEAN|0x1e\r
Commit	Line	Data
7b202cb0	1	## @file\r
49ba9447	2	# EFI/Framework Open Virtual Machine Firmware (OVMF) platform\r
49ba9447	3	#\r
10fa47e5	4	# Copyright (c) 2006 - 2019, Intel Corporation. All rights reserved.<BR>\r
49ba9447	5	#\r
b26f0cf9	6	# SPDX-License-Identifier: BSD-2-Clause-Patent\r
49ba9447	7	#\r
7b202cb0	8	##\r
49ba9447	9	\r
49ba9447	10	[Defines]\r
46293a42	11	DEC_SPECIFICATION = 0x00010005\r
49ba9447	12	PACKAGE_NAME = OvmfPkg\r
	13	PACKAGE_GUID = 2daf5f34-50e5-4b9d-b8e3-5562334d87e5\r
	14	PACKAGE_VERSION = 0.1\r
	15	\r
50944545	16	[Includes]\r
	17	Include\r
	18	\r
28b29a70	19	[LibraryClasses]\r
f6c6c020	20	## @libraryclass Loads and boots a Linux kernel image\r
	21	#\r
	22	LoadLinuxLib\|Include/Library/LoadLinuxLib.h\r
	23	\r
28b29a70	24	## @libraryclass Save and restore variables using a file\r
	25	#\r
	26	NvVarsFileLib\|Include/Library/NvVarsFileLib.h\r
	27	\r
392a3146 LE	28	## @libraryclass Provides services to work with PCI capabilities in PCI\r
	29	# config space.\r
	30	PciCapLib\|Include/Library/PciCapLib.h\r
	31	\r
02b9a834 LE	32	## @libraryclass Layered on top of PciCapLib, allows clients to plug an\r
	33	# EFI_PCI_IO_PROTOCOL backend into PciCapLib, for config\r
	34	# space access.\r
	35	PciCapPciIoLib\|Include/Library/PciCapPciIoLib.h\r
	36	\r
6a744d40 LE	37	## @libraryclass Layered on top of PciCapLib, allows clients to plug a\r
	38	# PciSegmentLib backend into PciCapLib, for config space\r
	39	# access.\r
	40	PciCapPciSegmentLib\|Include/Library/PciCapPciSegmentLib.h\r
	41	\r
77874cee LE	42	## @libraryclass Register a status code handler for printing the Boot\r
	43	# Manager's LoadImage() and StartImage() preparations, and\r
	44	# return codes, to the UEFI console.\r
	45	PlatformBmPrintScLib\|Include/Library/PlatformBmPrintScLib.h\r
	46	\r
f1ec65ba	47	## @libraryclass Access QEMU's firmware configuration interface\r
	48	#\r
	49	QemuFwCfgLib\|Include/Library/QemuFwCfgLib.h\r
	50	\r
f70b071e LE	51	## @libraryclass S3 support for QEMU fw_cfg\r
	52	#\r
	53	QemuFwCfgS3Lib\|Include/Library/QemuFwCfgS3Lib.h\r
	54	\r
cca7475b LE	55	## @libraryclass Rewrite the BootOrder NvVar based on QEMU's "bootorder"\r
	56	# fw_cfg file.\r
	57	#\r
	58	QemuBootOrderLib\|Include/Library/QemuBootOrderLib.h\r
	59	\r
28b29a70	60	## @libraryclass Serialize (and deserialize) variables\r
	61	#\r
	62	SerializeVariablesLib\|Include/Library/SerializeVariablesLib.h\r
	63	\r
cd8ff8fd AB	64	## @libraryclass Invoke Xen hypercalls\r
	65	#\r
	66	XenHypercallLib\|Include/Library/XenHypercallLib.h\r
	67	\r
0169352e AB	68	## @libraryclass Manage XenBus device path and I/O handles\r
	69	#\r
	70	XenIoMmioLib\|Include/Library/XenIoMmioLib.h\r
	71	\r
7b202cb0	72	[Guids]\r
29ebe47c LE	73	gUefiOvmfPkgTokenSpaceGuid = {0x93bb96af, 0xb9f2, 0x4eb8, {0x94, 0x62, 0xe0, 0xba, 0x74, 0x56, 0x42, 0x36}}\r
	74	gEfiXenInfoGuid = {0xd3b46f3b, 0xd441, 0x1244, {0x9a, 0x12, 0x0, 0x12, 0x27, 0x3f, 0xc1, 0x4d}}\r
	75	gOvmfPlatformConfigGuid = {0x7235c51c, 0x0c80, 0x4cab, {0x87, 0xac, 0x3b, 0x08, 0x4a, 0x63, 0x04, 0xb1}}\r
	76	gVirtioMmioTransportGuid = {0x837dca9e, 0xe874, 0x4d82, {0xb2, 0x9a, 0x23, 0xfe, 0x0e, 0x23, 0xd1, 0xe2}}\r
2c123c14	77	gQemuRamfbGuid = {0x557423a1, 0x63ab, 0x406c, {0xbe, 0x7e, 0x91, 0xcd, 0xbc, 0x08, 0xc4, 0x57}}\r
29ebe47c	78	gXenBusRootDeviceGuid = {0xa732241f, 0x383d, 0x4d9c, {0x8a, 0xe1, 0x8e, 0x09, 0x83, 0x75, 0x89, 0xd7}}\r
9116c9c5	79	gRootBridgesConnectedEventGroupGuid = {0x24a2d66f, 0xeedd, 0x4086, {0x90, 0x42, 0xf2, 0x6e, 0x47, 0x97, 0xee, 0x69}}\r
7eeaa758	80	gMicrosoftVendorGuid = {0x77fa9abd, 0x0359, 0x4d32, {0xbd, 0x60, 0x28, 0xf4, 0xe7, 0x8f, 0x78, 0x4b}}\r
49ba9447	81	\r
b0f51446	82	[Protocols]\r
29ebe47c	83	gVirtioDeviceProtocolGuid = {0xfa920010, 0x6785, 0x4941, {0xb6, 0xec, 0x49, 0x8c, 0x57, 0x9f, 0x16, 0x0a}}\r
29ebe47c LE	84	gXenBusProtocolGuid = {0x3d3ca290, 0xb9a5, 0x11e3, {0xb7, 0x5d, 0xb8, 0xac, 0x6f, 0x7d, 0x65, 0xe6}}\r
29ebe47c LE	85	gXenIoProtocolGuid = {0x6efac84f, 0x0ab0, 0x4747, {0x81, 0xbe, 0x85, 0x55, 0x62, 0x59, 0x04, 0x49}}\r
c5d736eb	86	gIoMmuAbsentProtocolGuid = {0xf8775d50, 0x8abd, 0x4adf, {0x92, 0xac, 0x85, 0x3e, 0x51, 0xf6, 0xc8, 0xdc}}\r
10fa47e5	87	gEfiLegacy8259ProtocolGuid = {0x38321dba, 0x4fe0, 0x4e17, {0x8a, 0xec, 0x41, 0x30, 0x55, 0xea, 0xed, 0xc1}}\r
b0f51446	88	\r
61069836	89	[PcdsFixedAtBuild]\r
b36f701d JJ	90	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvBase\|0x0\|UINT32\|0\r
	91	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfPeiMemFvSize\|0x0\|UINT32\|1\r
	92	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvBase\|0x0\|UINT32\|0x15\r
	93	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDxeMemFvSize\|0x0\|UINT32\|0x16\r
61069836	94	\r
b90aefa9	95	## This flag is used to control the destination port for PlatformDebugLibIoPort\r
	96	gUefiOvmfPkgTokenSpaceGuid.PcdDebugIoPort\|0x402\|UINT16\|4\r
	97	\r
37078a63	98	## When VirtioScsiDxe is instantiated for a HBA, the numbers of targets and\r
	99	# LUNs are retrieved from the host during virtio-scsi setup.\r
	100	# MdeModulePkg/Bus/Scsi/ScsiBusDxe then scans all MaxTarget * MaxLun\r
	101	# possible devices. This can take extremely long, for example with\r
	102	# MaxTarget=255 and MaxLun=16383. The inclusive constants below limit\r
	103	# MaxTarget and MaxLun, independently, should the host report higher values,\r
	104	# so that scanning the number of devices given by their product is still\r
	105	# acceptably fast.\r
	106	gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxTargetLimit\|31\|UINT16\|6\r
	107	gUefiOvmfPkgTokenSpaceGuid.PcdVirtioScsiMaxLunLimit\|7\|UINT32\|7\r
	108	\r
501e08fc JJ	109	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogBase\|0x0\|UINT32\|0x8\r
	110	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageEventLogSize\|0x0\|UINT32\|0x9\r
	111	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareFdSize\|0x0\|UINT32\|0xa\r
	112	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFirmwareBlockSize\|0\|UINT32\|0xb\r
	113	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageVariableBase\|0x0\|UINT32\|0xc\r
	114	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwSpareBase\|0x0\|UINT32\|0xd\r
	115	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashNvStorageFtwWorkingBase\|0x0\|UINT32\|0xe\r
	116	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFdBaseAddress\|0x0\|UINT32\|0xf\r
b382ede3 JJ	117	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesBase\|0x0\|UINT32\|0x11\r
b382ede3 JJ	118	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPageTablesSize\|0x0\|UINT32\|0x12\r
7cb6b0e0 JJ	119	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamBase\|0x0\|UINT32\|0x13\r
7cb6b0e0 JJ	120	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfSecPeiTempRamSize\|0x0\|UINT32\|0x14\r
6a7cba79 LE	121	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageBase\|0x0\|UINT32\|0x18\r
6a7cba79 LE	122	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfLockBoxStorageSize\|0x0\|UINT32\|0x19\r
ad43bc6b	123	gUefiOvmfPkgTokenSpaceGuid.PcdGuidedExtractHandlerTableSize\|0x0\|UINT32\|0x1a\r
9beac0d8	124	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfDecompressionScratchEnd\|0x0\|UINT32\|0x1f\r
501e08fc	125	\r
460ffed2 HW	126	## Pcd8259LegacyModeMask defines the default mask value for platform. This\r
	127	# value is determined.\r
	128	# 1) If platform only support pure UEFI, value should be set to 0xFFFF or\r
	129	# 0xFFFE; Because only clock interrupt is allowed in legacy mode in pure\r
	130	# UEFI platform.\r
	131	# 2) If platform install CSM and use thunk module:\r
	132	# a) If thunk call provided by CSM binary requires some legacy interrupt\r
	133	# support, the corresponding bit should be opened as 0.\r
	134	# For example, if keyboard interfaces provided CSM binary use legacy\r
	135	# keyboard interrupt in 8259 bit 1, then the value should be set to\r
	136	# 0xFFFC.\r
	137	# b) If all thunk call provied by CSM binary do not require legacy\r
	138	# interrupt support, value should be set to 0xFFFF or 0xFFFE.\r
	139	#\r
	140	# The default value of legacy mode mask could be changed by\r
	141	# EFI_LEGACY_8259_PROTOCOL->SetMask(). But it is rarely need change it\r
	142	# except some special cases such as when initializing the CSM binary, it\r
	143	# should be set to 0xFFFF to mask all legacy interrupt. Please restore the\r
	144	# original legacy mask value if changing is made for these special case.\r
	145	gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeMask\|0xFFFF\|UINT16\|0x3\r
	146	\r
	147	## Pcd8259LegacyModeEdgeLevel defines the default edge level for legacy\r
	148	# mode's interrrupt controller.\r
	149	# For the corresponding bits, 0 = Edge triggered and 1 = Level triggered.\r
	150	gUefiOvmfPkgTokenSpaceGuid.Pcd8259LegacyModeEdgeLevel\|0x0000\|UINT16\|0x5\r
	151	\r
70c66df5	152	[PcdsDynamic, PcdsDynamicEx]\r
85c0b5ee	153	gUefiOvmfPkgTokenSpaceGuid.PcdEmuVariableEvent\|0\|UINT64\|2\r
9d35ac26	154	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfFlashVariablesEnable\|FALSE\|BOOLEAN\|0x10\r
d55004da	155	gUefiOvmfPkgTokenSpaceGuid.PcdOvmfHostBridgePciDevId\|0\|UINT16\|0x1b\r
6fbef93e	156	gUefiOvmfPkgTokenSpaceGuid.PcdQemuSmbiosValidated\|FALSE\|BOOLEAN\|0x21\r
49ba9447	157	\r
c4df7fd0 LE	158	## The IO port aperture shared by all PCI root bridges.\r
	159	#\r
	160	gUefiOvmfPkgTokenSpaceGuid.PcdPciIoBase\|0x0\|UINT64\|0x22\r
	161	gUefiOvmfPkgTokenSpaceGuid.PcdPciIoSize\|0x0\|UINT64\|0x23\r
	162	\r
03845e90 LE	163	## The 32-bit MMIO aperture shared by all PCI root bridges.\r
	164	#\r
	165	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Base\|0x0\|UINT64\|0x24\r
	166	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio32Size\|0x0\|UINT64\|0x25\r
	167	\r
7e5b1b67 LE	168	## The 64-bit MMIO aperture shared by all PCI root bridges.\r
	169	#\r
	170	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Base\|0x0\|UINT64\|0x26\r
	171	gUefiOvmfPkgTokenSpaceGuid.PcdPciMmio64Size\|0x0\|UINT64\|0x27\r
	172	\r
966dbaf4	173	## The following setting controls how many megabytes we configure as TSEG on\r
d04b72c6 LE	174	# Q35, for SMRAM purposes. Permitted defaults are: 1, 2, 8. Other defaults\r
	175	# cause undefined behavior. During boot, the PCD is updated by PlatformPei\r
	176	# to reflect the extended TSEG size, if one is advertized by QEMU.\r
966dbaf4	177	#\r
d04b72c6	178	# This PCD is only accessed if PcdSmmSmramRequire is TRUE (see below).\r
966dbaf4 LE	179	gUefiOvmfPkgTokenSpaceGuid.PcdQ35TsegMbytes\|8\|UINT16\|0x20\r
966dbaf4 LE	180	\r
e05061c5	181	[PcdsFeatureFlag]\r
2f9c55cc	182	gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderPciTranslation\|TRUE\|BOOLEAN\|0x1c\r
43336916	183	gUefiOvmfPkgTokenSpaceGuid.PcdQemuBootOrderMmioTranslation\|FALSE\|BOOLEAN\|0x1d\r
1f695483 LE	184	\r
	185	## This feature flag enables SMM/SMRAM support. Note that it also requires\r
	186	# such support from the underlying QEMU instance; if that support is not\r
	187	# present, the firmware will reject continuing after a certain point.\r
	188	#\r
	189	# The flag also acts as a general "security switch"; when TRUE, many\r
	190	# components will change behavior, with the goal of preventing a malicious\r
	191	# runtime OS from tampering with firmware structures (special memory ranges\r
	192	# used by OVMF, the varstore pflash chip, LockBox etc).\r
	193	gUefiOvmfPkgTokenSpaceGuid.PcdSmmSmramRequire\|FALSE\|BOOLEAN\|0x1e\r